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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id 76-20020a63044f000000b003db141a5f26sm3868353pge.1.2022.05.19.11.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 11:25:07 -0700 (PDT) From: Kevin Hilman To: Chen-Yu Tsai , cw00.choi@samsung.com Cc: Roger Lu , Matthias Brugger , Enric Balletbo Serra , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel , Fan Chen , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Guenter Roeck , Jia-wei Chang , =?utf-8?B?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= Subject: Re: [PATCH v25 0/7] soc: mediatek: SVS: introduce MTK SVS In-Reply-To: References: <20220516004311.18358-1-roger.lu@mediatek.com> <7h4k1ndaui.fsf@baylibre.com> <7hy1yzbtb7.fsf@baylibre.com> Date: Thu, 19 May 2022 11:25:07 -0700 Message-ID: <7hmtfdbcsc.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Chen-Yu Tsai writes: > n Wed, May 18, 2022 at 8:03 AM Kevin Hilman wrote: >> >> Kevin Hilman writes: >> >> > Chen-Yu Tsai writes: >> > >> >> On Mon, May 16, 2022 at 8:43 AM Roger Lu wrote: >> >>> >> >>> The Smart Voltage Scaling(SVS) engine is a piece of hardware >> >>> which calculates suitable SVS bank voltages to OPP voltage table. >> >>> Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck >> >>> when receiving OPP_EVENT_ADJUST_VOLTAGE. >> >>> >> >>> 1. SVS driver uses OPP adjust event in [1] to update OPP table voltage part. >> >>> 2. SVS driver gets thermal/GPU device by node [2][3] and CPU device by get_cpu_device(). >> >>> After retrieving subsys device, SVS driver calls device_link_add() to make sure probe/suspend callback priority. >> >>> >> >>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/commit/?h=opp/linux-next&id=25cb20a212a1f989385dfe23230817e69c62bee5 >> >>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/commit/?h=opp/linux-next&id=b325ce39785b1408040d90365a6ab1aa36e94f87 >> >>> [3] https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.16-next/dts64&id=a8168cebf1bca1b5269e8a7eb2626fb76814d6e2 >> >>> >> >>> Change since v24: >> >>> - Rebase to Linux 5.18-rc6 >> >>> - Show specific fail log in svs_platform_probe() to help catch which step fails quickly >> >>> - Remove struct svs_bank member "pd_dev" because all subsys device's power domain has been merged into one node like above [3] >> >>> >> >>> Test in below environment: >> >>> SW: Integration Tree [4] + Thermal patch [5] + SVS v25 (this patchset) >> >>> HW: mt8183-Krane >> >>> >> >>> [4] https://github.com/wens/linux/commits/mt8183-cpufreq-cci-svs-test >> >> >> >> I've updated my branch to include all the latest versions of the relevant >> >> patch series: >> >> >> >> - anx7625 DPI bus type series v2 (so the display works) >> >> - MT8183 thermal series v9 (this seems to have been overlooked by the >> >> maintainer) >> >> - MTK SVS driver series v25 >> >> - devfreq: cpu based scaling support to passive governor series v5 >> >> - MTK CCI devfreq series v4 >> >> - MT8183 cpufreq series v7 >> >> - Additional WIP patches for panfrost MTK devfreq >> > >> > Thanks for preparing an integration branch Chen-Yu. >> > >> > I'm testing this on mt8183-pumpkin with one patch to add the CCI >> > regulator[1], and the defconfig you posted in a previous rev of this >> > series, but the CCI driver still causes a fault on boot[2] on my >> > platform. >> > >> > I mentioned in earlier reviews that I think there's potentially a race >> > between CCI and SVS loading since they are co-dependent. My hunch is >> > that this is still not being handled properly. >> >> Ah, actually it's crashing when I try to boot the platform with >> `maxcpus=4` on the cmdline (which I have to do because mt8183-pumpkin is >> unstable upstream with the 2nd cluster enabled.) >> >> The CCI driver should be a bit more robust about detecting >> available/online CPUs > > This all seems to be handled in the devfreq passive governor. Well, that's the initial crash. But the SVS driver will also go through its svs_mt8183_banks[] array (including both big & little clusters) and try to init SVS, so presumably that will have some problems also if only one cluster is enabled. > And presumably we'd like to have CCI devfreq running even if just one > core was booted. Yes, I assume so also. > Added Chanwoo for more ideas. OK, thanks. Kevin