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Fri, 13 Sep 2024 05:10:48 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 13 Sep 2024 10:10:09 +0100 From: "Jiaxun Yang" To: "Huacai Chen" Cc: "Xuerui Wang" , "Rafael J. Wysocki" , "Viresh Kumar" , "Thomas Gleixner" , "Thomas Bogendoerfer" , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, "linux-mips@vger.kernel.org" , kvm@vger.kernel.org Message-Id: <84c6e819-e2b8-40b6-8de4-9f550e652acc@app.fastmail.com> In-Reply-To: References: <20240912-iocsr-v2-0-e88f75b37da4@flygoat.com> <20240912-iocsr-v2-1-e88f75b37da4@flygoat.com> Subject: Re: [PATCH v2 1/4] LoongArch: Probe more CPU features from CPUCFG Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B49=E6=9C=8813=E6=97=A5=E4=B9=9D=E6=9C=88 =E4=B8=8A=E5= =8D=889:46=EF=BC=8CHuacai Chen=E5=86=99=E9=81=93=EF=BC=9A > Hi, Jiaxun, > > On Fri, Sep 13, 2024 at 4:56=E2=80=AFAM Jiaxun Yang wrote: >> >> Probe ISA level, TLB, IOCSR information from CPUCFG to >> improve kernel resilience to different core implementations. >> >> Signed-off-by: Jiaxun Yang >> --- >> arch/loongarch/include/asm/cpu.h | 4 +++ >> arch/loongarch/include/asm/loongarch.h | 3 +- >> arch/loongarch/kernel/cpu-probe.c | 54 ++++++++++++++++++++++++= ---------- >> 3 files changed, 44 insertions(+), 17 deletions(-) >> >> diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/includ= e/asm/cpu.h >> index 843f9c4ec980..251a15439cff 100644 >> --- a/arch/loongarch/include/asm/cpu.h >> +++ b/arch/loongarch/include/asm/cpu.h >> @@ -100,6 +100,8 @@ enum cpu_type_enum { >> #define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor= (running in VM) */ >> #define CPU_FEATURE_PTW 26 /* CPU has ha= rdware page table walker */ >> #define CPU_FEATURE_AVECINT 27 /* CPU has avec inter= rupt */ >> +#define CPU_FEATURE_IOCSR 28 /* CPU has IOCSR */ >> +#define CPU_FEATURE_LSPW 29 /* CPU has LSPW */ > I don't see LSPW being used, so just remove it now? I=E2=80=99m going to submit a page table walker for CPU without SPW late= r on :-) I=E2=80=99m fine with adding that later. Thanks - Jiaxun > >> >> #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) >> #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) >> @@ -129,5 +131,7 @@ enum cpu_type_enum { >> #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISO= R) >> #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW) >> #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) >> +#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR) >> +#define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW) >> >> #endif /* _ASM_CPU_H */ >> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/= include/asm/loongarch.h >> index 631d249b3ef2..23af28f00c3c 100644 >> --- a/arch/loongarch/include/asm/loongarch.h >> +++ b/arch/loongarch/include/asm/loongarch.h >> @@ -60,8 +60,7 @@ >> #define CPUCFG0_PRID GENMASK(31, 0) >> >> #define LOONGARCH_CPUCFG1 0x1 >> -#define CPUCFG1_ISGR32 BIT(0) >> -#define CPUCFG1_ISGR64 BIT(1) >> +#define CPUCFG1_ISA GENMASK(1, 0) >> #define CPUCFG1_PAGING BIT(2) >> #define CPUCFG1_IOCSR BIT(3) >> #define CPUCFG1_PABITS GENMASK(11, 4) >> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kerne= l/cpu-probe.c >> index 14f0449f5452..5dc8ca3c4387 100644 >> --- a/arch/loongarch/kernel/cpu-probe.c >> +++ b/arch/loongarch/kernel/cpu-probe.c >> @@ -92,11 +92,29 @@ static void cpu_probe_common(struct cpuinfo_loong= arch *c) >> unsigned long asid_mask; >> >> c->options =3D LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | >> - LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGAR= CH_CPU_WATCH; >> + LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; >> >> elf_hwcap =3D HWCAP_LOONGARCH_CPUCFG; >> >> config =3D read_cpucfg(LOONGARCH_CPUCFG1); >> + >> + switch (config & CPUCFG1_ISA) { >> + case 0: >> + set_isa(c, LOONGARCH_CPU_ISA_LA32R); >> + break; >> + case 1: >> + set_isa(c, LOONGARCH_CPU_ISA_LA32S); >> + break; >> + case 2: >> + set_isa(c, LOONGARCH_CPU_ISA_LA64); >> + break; >> + default: >> + pr_warn("Warning: unknown ISA level\n"); >> + } >> + if (config & CPUCFG1_PAGING) >> + c->options |=3D LOONGARCH_CPU_TLB; >> + if (config & CPUCFG1_IOCSR) >> + c->options |=3D LOONGARCH_CPU_IOCSR; >> if (config & CPUCFG1_UAL) { >> c->options |=3D LOONGARCH_CPU_UAL; >> elf_hwcap |=3D HWCAP_LOONGARCH_UAL; >> @@ -157,6 +175,8 @@ static void cpu_probe_common(struct cpuinfo_loong= arch *c) >> elf_hwcap |=3D HWCAP_LOONGARCH_LBT_MIPS; >> } >> #endif >> + if (config & CPUCFG2_LSPW) >> + c->options |=3D LOONGARCH_CPU_LSPW; >> >> config =3D read_cpucfg(LOONGARCH_CPUCFG6); >> if (config & CPUCFG6_PMP) >> @@ -222,6 +242,7 @@ static inline void cpu_probe_loongson(struct cpui= nfo_loongarch *c, unsigned int >> { >> uint64_t *vendor =3D (void *)(&cpu_full_name[VENDOR_OFFSET]); >> uint64_t *cpuname =3D (void *)(&cpu_full_name[CPUNAME_OFFSET]= ); >> + const char *core_name =3D "Unknown"; >> >> if (!__cpu_full_name[cpu]) >> __cpu_full_name[cpu] =3D cpu_full_name; >> @@ -232,40 +253,43 @@ static inline void cpu_probe_loongson(struct cp= uinfo_loongarch *c, unsigned int >> switch (c->processor_id & PRID_SERIES_MASK) { >> case PRID_SERIES_LA132: >> c->cputype =3D CPU_LOONGSON32; >> - set_isa(c, LOONGARCH_CPU_ISA_LA32S); >> __cpu_family[cpu] =3D "Loongson-32bit"; >> - pr_info("32-bit Loongson Processor probed (LA132 Core= )\n"); >> + core_name =3D "LA132"; >> break; >> case PRID_SERIES_LA264: >> c->cputype =3D CPU_LOONGSON64; >> - set_isa(c, LOONGARCH_CPU_ISA_LA64); >> __cpu_family[cpu] =3D "Loongson-64bit"; >> - pr_info("64-bit Loongson Processor probed (LA264 Core= )\n"); >> + core_name =3D "LA264"; >> break; >> case PRID_SERIES_LA364: >> c->cputype =3D CPU_LOONGSON64; >> - set_isa(c, LOONGARCH_CPU_ISA_LA64); >> __cpu_family[cpu] =3D "Loongson-64bit"; >> - pr_info("64-bit Loongson Processor probed (LA364 Core= )\n"); >> + core_name =3D "LA364"; >> break; >> case PRID_SERIES_LA464: >> c->cputype =3D CPU_LOONGSON64; >> - set_isa(c, LOONGARCH_CPU_ISA_LA64); >> __cpu_family[cpu] =3D "Loongson-64bit"; >> - pr_info("64-bit Loongson Processor probed (LA464 Core= )\n"); >> + core_name =3D "LA464"; >> break; >> case PRID_SERIES_LA664: >> c->cputype =3D CPU_LOONGSON64; >> - set_isa(c, LOONGARCH_CPU_ISA_LA64); >> __cpu_family[cpu] =3D "Loongson-64bit"; >> - pr_info("64-bit Loongson Processor probed (LA664 Core= )\n"); >> + core_name =3D "LA664"; >> break; >> default: /* Default to 64 bit */ >> - c->cputype =3D CPU_LOONGSON64; >> - set_isa(c, LOONGARCH_CPU_ISA_LA64); >> - __cpu_family[cpu] =3D "Loongson-64bit"; >> - pr_info("64-bit Loongson Processor probed (Unknown Co= re)\n"); >> + if (c->isa_level & LOONGARCH_CPU_ISA_LA64) { >> + c->cputype =3D CPU_LOONGSON64; >> + __cpu_family[cpu] =3D "Loongson-64bit"; >> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32S) { >> + c->cputype =3D CPU_LOONGSON32; >> + __cpu_family[cpu] =3D "Loongson-32bit"; >> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32R) { >> + c->cputype =3D CPU_LOONGSON32; >> + __cpu_family[cpu] =3D "Loongson-32bit Reduced= "; >> + } > I prefer to move this part before the switch-case of PRID (and it is > better to convert to a switch-case too), then the switch-case of PRID > can be only used for probing core-name. > > Huacai > >> } >> + >> + pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu],= core_name); >> } >> >> #ifdef CONFIG_64BIT >> >> -- >> 2.46.0 >> --=20 - Jiaxun