Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs

Thomas Gleixner
2021-08-26T23:04:13Z

On Wed, Aug 18 2021 at 17:43, Deepak Sharma wrote:

> AMD CPU which support C3 shares cache. Its not necessary to flush the
> caches in software before entering C3. This will cause performance drop
> for the cores which share some caches. ARB_DIS is not used with current
> AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> ---
> arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..62a5986d625a 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> */
> flags->bm_control = 0;
> }
> + if (c->x86_vendor == X86_VENDOR_AMD) {
> + /*
> + * For all AMD CPUs that support C3, caches should not be
> + * flushed by software while entering C3 type state. Set
> + * bm->check to 1 so that kernel doesn't need to execute
> + * cache flush operation.
> + */
> + flags->bm_check = 1;
> + /*
> + * In current AMD C state implementation ARB_DIS is no longer

Fine for current implementations, but what about older implementations?

Thanks,

tglx