From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Subject: Re: [PATCH] Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K" Date: Tue, 18 Dec 2018 17:58:34 +0100 Message-ID: <877eg6hiv9.fsf@bootlin.com> References: <87k1kowf7i.fsf@bootlin.com> <20181205101035.GA31059@e107155-lin> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181205101035.GA31059@e107155-lin> (Sudeep Holla's message of "Wed, 5 Dec 2018 10:10:35 +0000") List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Sudeep Holla Cc: Andrew Lunn , Baruch Siach , Jason Cooper , Sergey Matyukevich , linux-pm@vger.kernel.org, orenbh , Daniel Lezcano , "Rafael J. Wysocki" , Russell King , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth List-Id: linux-pm@vger.kernel.org SGkgU3VkZWVwLAogCiBPbiBtZXIuLCBkw6ljLiAwNSAyMDE4LCBTdWRlZXAgSG9sbGEgPHN1ZGVl cC5ob2xsYUBhcm0uY29tPiB3cm90ZToKCj4gT24gV2VkLCBEZWMgMDUsIDIwMTggYXQgMDk6Mjc6 NDVBTSArMDEwMCwgR3JlZ29yeSBDTEVNRU5UIHdyb3RlOgo+PiBIaSBCYXJ1Y2gsCj4+ICAKPj4g IE9uIG1lci4sIGTDqWMuIDA1IDIwMTgsIEJhcnVjaCBTaWFjaCA8YmFydWNoQHRrb3MuY28uaWw+ IHdyb3RlOgo+PiAKPj4gPiBIaSBHcmVnb3J5LAo+PiA+Cj4+ID4gT24gVHVlLCBEZWMgMDQsIDIw MTggYXQgMDY6NDg6NDNQTSArMDIwMCwgQmFydWNoIFNpYWNoIHdyb3RlOgo+PiA+PiBPbiBUdWUs IERlYyAwNCwgMjAxOCBhdCAwNToyMToyNVBNICswMTAwLCBHcmVnb3J5IENMRU1FTlQgd3JvdGU6 Cj4+ID4+ID4gIE9uIG1hci4sIGTDqWMuIDA0IDIwMTgsIEJhcnVjaCBTaWFjaCA8YmFydWNoQHRr b3MuY28uaWw+IHdyb3RlOgo+PiA+PiA+ID4gVGhpcyByZXZlcnRzIGNvbW1pdCA4ZWQ0NjM2ODc3 NmIzYmM5M2Q3NGMxZjhmMmJmYjlmZDhhOWFkODA1Lgo+PiA+PiA+ID4KPj4gPj4gPiA+IFRoaXMg Y29tbWl0IGJyZWFrcyBib290IG9uIEFybWFkYSA4SyBiYXNlZCBzeXN0ZW1zLiBSZXZlcnRpbmcg aXQgbWFrZXMKPj4gPj4gPiA+IGFmZmVjdGVkIHN5c3RlbXMgYm9vdCBhZ2Fpbi4KPj4gPj4gPiA+ Cj4+ID4+ID4gPiBSZXBvcnRlZC1ieTogU2VyZ2V5IE1hdHl1a2V2aWNoIDxnZW9tYXRzaUBnbWFp bC5jb20+Cj4+ID4+ID4gPiBTaWduZWQtb2ZmLWJ5OiBCYXJ1Y2ggU2lhY2ggPGJhcnVjaEB0a29z LmNvLmlsPgo+PiA+PiA+IAo+PiA+PiA+IEkgd291bGQgbGlrZSB0byBrbm93IG1vcmUgYWJvdXQg aXQgYmVjYXVzZSBvbiB0aGUgTWNCaW4gSSB1c2UgdGhlcmUgaXMKPj4gPj4gPiBubyBpc3N1ZSB3 aXRoIDQuMjAtcmMxLgo+PiA+PiA+IAo+PiA+PiA+IERvIHlvdSBvYnNlcnZlIHRoaXMgaXNzdWUg d2l0aCB0aGUgYXJtNjQgZGVmY29uZmlnIG9yIGRvIHlvdSBoYXZlIHNvbWUKPj4gPj4gPiBzcGVj aWZpYyBjb25maWd1cmF0aW9uIG9wdGlvbj8KPj4gPj4gCj4+ID4+IEkgdGVzdGVkIHRoZSBhdHRh Y2hlZCBkZWZjb25maWcgb24gQ2xlYXJmb2cgR1QtOEsgYW5kIG9uIGFub3RoZXIgY3VzdG9tIEFy bWFkYSAKPj4gPj4gOEsgYmFzZWQgYm9hcmQuCj4+ID4+IAo+PiA+PiBUb21vcnJvdyBJJ2xsIHRl c3QgTWFjY2hpYXRvYmluIHdpdGggdGhpcyBjb25maWcgYW5kIHRoZSBhcm02NCBkZWZjb25maWcu Cj4+ID4KPj4gPiBJIHJlcHJvZHVjZWQgc2FtZSBpc3N1ZSBvbiBhIE1hY2NoaWF0b2JpbiBib2Fy ZCB3aXRoIGJvdGggdGhpcyBjb25maWcgYW5kIHRoZSAKPj4gPiBhcm02NCBkZWZjb25maWcuIFRo ZSBsYXR0ZXIgcHJvZHVjZWQgdGhpcyBzcGxhdDoKPj4gCj4+IE9LIHRoYW5rcywgZm9yIHRoaXMs IEkgYWxzbyBnb3QgdGhlIGNvbmZpcm1hdGlvbiBieSBteSBjb2xsZWFndWVzLiBUaGUKPj4gb25s eSBkaWZmZXJlbmNlIEkgY2FuIHRoaW5rIG9mLCBpcyB0aGUgZmlybXdhcmUsIGJ1dCB0aGUgc3Vy cHJpc2luZwo+PiB0aGluZywgaXMgdGhhdCBJIGhhdmUgYW4gb2xkIGZpcm13YXJlOiAxNy4wNi4y IGFuZCB0aGF0IHdpdGggYSByZWNlbnQKPj4gb25lLCBpdCBkb2Vzbid0IHdvcmsuCj4+IAo+PiBT byBJIHdpbGwgYXBwbHkgaXQgaW4gbXZlYnUvZml4ZXMuCj4+IAo+Cj4gU29ycnkgaWYgaXQncyB0 b28gbGF0ZS4gQnV0IEkgd291bGQgcmF0aGVyIGRpc2FibGUgdGhlIHN0YXRlcyB0aGF0IGFyZQo+ IGJyb2tlbiBvbiBvbGQgZmlybXdhcmUgYW5kIHNlZSBpZiBpdCdzIHBvc3NpYmxlIGZvciBib290 bG9hZGVyIG9yIGJvb3QKPiBmaXJtd2FyZSBsb2FkaW5nIERUIGNhbiBtb2RpZnkgdGhlIHN0YXR1 cyB0byAiZW5hYmxlZCIgaWYgaXQgY2FuIGRldGVjdAo+IHRoZSBmaXJtd2FyZSB2ZXJzaW9uLgoK eW91IG1lYW4gYWRkaW5nIHN0YXR1cyA9ICJkaXNhYmxlIiBvbiBlYWNoIGlkbGUtc3RhdGUgc3Vi bm9kZT8KCkdyZWdvcnkKCj4KPiAtLQo+IFJlZ2FyZHMsCj4gU3VkZWVwCgotLSAKR3JlZ29yeSBD bGVtZW50LCBCb290bGluCkVtYmVkZGVkIExpbnV4IGFuZCBLZXJuZWwgZW5naW5lZXJpbmcKaHR0 cDovL2Jvb3RsaW4uY29tCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxp c3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0 aW5mby9saW51eC1hcm0ta2VybmVsCg==