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Content-Language: en-US To: Meng Li , "Rafael J . Wysocki" , Huang Rui Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-acpi@vger.kernel.org, Shuah Khan , linux-kselftest@vger.kernel.org, Nathan Fontenot , Deepak Sharma , Alex Deucher , Shimmer Huang , Perry Yuan , Xiaojian Du , Viresh Kumar , Borislav Petkov References: <20230815061546.3556083-1-li.meng@amd.com> <20230815061546.3556083-4-li.meng@amd.com> From: Mario Limonciello In-Reply-To: <20230815061546.3556083-4-li.meng@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN6PR08CA0028.namprd08.prod.outlook.com (2603:10b6:805:66::41) To MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN0PR12MB6101:EE_|DS0PR12MB7656:EE_ X-MS-Office365-Filtering-Correlation-Id: 6022f8b1-6a7d-4e1e-cb59-08db9da3a4ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bk+h211aUNl2c+YwUcgOWhm051yfq3u1icUP03SpcWzllSkMmYVamsKpNcFyf6Ij93PGiLaIuHf1iup7jmthn65EJsB4LKiKv8U5a5pQhQ+zsGvhmPmUK+M2tWDY65sUjpWTeLJLxZoKSIdbpH2x+PQ1YPqWYa+4bJinu2z7glOLBYJa+TxhyhnagXwWnVnR9rkcpPDSxR4zggTh/Gqq33cJao481PCPcNi2RuGL0TIbjXRqjKnV2xysfPO+bP5SdGKBQBNYEi4u08T2lAetSNclLc8RHJX4CHbfGJj4JjUuuLZot+NwmxECBTjdmOfwjfsp1+/5A2dfpw2vqUzOjhyt0VEOR0Q3lmdCAnof4sCMxXd+H2XM13VpiLhJg9yYW9Y8yvWKerDQfjtpAsdQ3tL8kWPP6bq87iZDOZllK9HzomEtfL/gn1bWVPNFQFLiX73FbNJ114Q9Ojcwdjj8fIMfVA9IG9Wf4Vv2KmGsELSXBp1nr7oXrM4n0QaXs+PTxt5pUDs0vu/Wh/ZGbnw6ie/by4SedEsjjXByf9JZRZqJzMoIre0m5dKhp2N+OGFpxt2frm/riRXcunStgp3xPi27JWmlK+yaHFMECc+wDX88IvdcqtNS8XGNusrg8mutSAceWfSbR7agx08X3z93tA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN0PR12MB6101.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(136003)(376002)(366004)(346002)(1800799009)(186009)(451199024)(2906002)(8936002)(8676002)(44832011)(4326008)(6486002)(478600001)(110136005)(54906003)(6512007)(83380400001)(6506007)(66476007)(66556008)(5660300002)(41300700001)(6636002)(66946007)(316002)(2616005)(86362001)(31686004)(36756003)(31696002)(6666004)(38100700002)(26005)(53546011)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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We call it AMD Pstate Preferrred Core. > > Here sched_set_itmt_core_prio() is called to set priorities and > sched_set_itmt_support() is called to enable ITMT feature. > AMD Pstate driver uses the highest performance value to indicate > the priority of CPU. The higher value has a higher priority. > > The initial core rankings are set up by AMD Pstate when the > system boots. > > Add device attribute for preferred core states. > > Add one new early parameter `enable` to allow user to s/enable/amd_prefcore/ > enable the preferred core if the processor and power > firmware can support preferred core feature. > > Signed-off-by: Meng Li > Signed-off-by: Perry Yuan You and Perry worked on this together, right? If so I believe you're missing a 'Co-Developed-By' tag here. Also the order should have you at the end as you're submitting the series. With those two nits fixed: Reviewed-by: Mario Limonciello > --- > drivers/cpufreq/amd-pstate.c | 120 ++++++++++++++++++++++++++++++----- > 1 file changed, 104 insertions(+), 16 deletions(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 9a1e194d5cf8..d02305675f66 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -37,6 +37,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -49,6 +50,8 @@ > > #define AMD_PSTATE_TRANSITION_LATENCY 20000 > #define AMD_PSTATE_TRANSITION_DELAY 1000 > +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 > +#define AMD_PSTATE_MAX_CPPC_PERF 255 > > /* > * TODO: We need more time to fine tune processors with shared memory solution > @@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver; > static int cppc_state = AMD_PSTATE_UNDEFINED; > static bool cppc_enabled; > > +/*Preferred Core featue is supported*/ > +static bool prefcore = true; > + > /* > * AMD Energy Preference Performance (EPP) > * The EPP is used in the CCLK DPM controller to drive > @@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable) > static int pstate_init_perf(struct amd_cpudata *cpudata) > { > u64 cap1; > - u32 highest_perf; > > int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, > &cap1); > if (ret) > return ret; > > - /* > - * TODO: Introduce AMD specific power feature. > - * > - * CPPC entry doesn't indicate the highest performance in some ASICs. > + /* For platforms that do not support the preferred core feature, the > + * highest_pef may be configured with 166 or 255, to avoid max frequency > + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as > + * the default max perf. > */ > - highest_perf = amd_get_highest_perf(); > - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) > - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); > - > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > + if (prefcore) > + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); > + else > + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); > > WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); > WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); > @@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) > static int cppc_init_perf(struct amd_cpudata *cpudata) > { > struct cppc_perf_caps cppc_perf; > - u32 highest_perf; > > int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); > if (ret) > return ret; > > - highest_perf = amd_get_highest_perf(); > - if (highest_perf > cppc_perf.highest_perf) > - highest_perf = cppc_perf.highest_perf; > - > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > + if (prefcore) > + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); > + else > + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); > > WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); > WRITE_ONCE(cpudata->lowest_nonlinear_perf, > @@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu) > wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); > } > > +/* > + * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks > + * due to locking, so queue the work for later. > + */ > +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) > +{ > + sched_set_itmt_support(); > +} > +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); > + > +/** > + * Get the highest performance register value. > + * @cpu: CPU from which to get highest performance. > + * @highest_perf: Return address. > + * > + * Return: 0 for success, -EIO otherwise. > + */ > +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) > +{ > + int ret; > + > + if (boot_cpu_has(X86_FEATURE_CPPC)) { > + u64 cap1; > + > + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); > + if (ret) > + return ret; > + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); > + } else { > + ret = cppc_get_highest_perf(cpu, highest_perf); > + } > + > + return (ret); > +} > + > +static void amd_pstate_init_prefcore(void) > +{ > + int cpu, ret; > + u64 highest_perf; > + > + if (!prefcore) > + return; > + > + for_each_online_cpu(cpu) { > + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); > + if (ret) > + break; > + > + sched_set_itmt_core_prio(highest_perf, cpu); > + > + /* check if CPPC preferred core feature is enabled*/ > + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { > + prefcore = false; > + return; > + } > + } > + > + /* > + * This code can be run during CPU online under the > + * CPU hotplug locks, so sched_set_amd_prefcore_support() > + * cannot be called from here. Queue up a work item > + * to invoke it. > + */ > + schedule_work(&sched_prefcore_work); > +} > + > static int amd_pstate_cpu_init(struct cpufreq_policy *policy) > { > int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; > @@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, > return ret < 0 ? ret : count; > } > > +static ssize_t prefcore_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); > +} > + > cpufreq_freq_attr_ro(amd_pstate_max_freq); > cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); > > @@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); > cpufreq_freq_attr_rw(energy_performance_preference); > cpufreq_freq_attr_ro(energy_performance_available_preferences); > static DEVICE_ATTR_RW(status); > +static DEVICE_ATTR_RO(prefcore); > > static struct freq_attr *amd_pstate_attr[] = { > &amd_pstate_max_freq, > @@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { > > static struct attribute *pstate_global_attributes[] = { > &dev_attr_status.attr, > + &dev_attr_prefcore.attr, > NULL > }; > > @@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void) > } > } > > + amd_pstate_init_prefcore(); > + > return ret; > > global_attr_free: > @@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str) > > return amd_pstate_set_driver(mode_idx); > } > + > +static int __init amd_prefcore_param(char *str) > +{ > + if (!strcmp(str, "disable")) > + prefcore = false; > + > + return 0; > +} > + > early_param("amd_pstate", amd_pstate_param); > +early_param("amd_prefcore", amd_prefcore_param); > > MODULE_AUTHOR("Huang Rui "); > MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");