Re: powercap ABI clarification

["Zhang, Rui" <rui.zhang@intel.com>]

On Mon, 2024-05-27 at 14:55 +0200, Daniel Lezcano wrote:
> 
> Hi Srinivas,
> 
> the powercap ABI exports some constraint files. Even if I suspect
> their 
> semantic it is not really clear how they should behave.
> 
>        │   ├──constraint_0_name
>        │   ├──constraint_0_power_limit_uw
>        │   ├──constraint_0_time_window_us
>        │   ├──constraint_1_name
>        │   ├──constraint_1_power_limit_uw
>        │   ├──constraint_1_time_window_us
> 
> Are the constraints controller specific? I mean, each controller
> defines 
> their constraints? Or is it supposed to behave the same way whatever
> the 
> controller?

Currently we have three controllers, MSR RAPL, MMIO RAPL and TPMI RAPL.
They are actually the same feature (RAPL) via different register
Interfaces.
So their behaviors are consistent.

> 
> Is the time window giving the duration of the power_limit_uw
> constraint? 
> Or is it an average power during this time window?

The average power during this time window.
The constraint is always effective after we set it.

> 
> What is the purpose of min|max_time_window_us?

It is the upper/lower limit for users to set a meaningful time window.

> 
> Can we set several constraints or are they mutually exclusive?

My understanding is that they can both take effect.
"Two power limits can be specified, corresponding to time windows of
different sizes. Each power limit provides inde-
pendent clamping control that would permit the processor cores to go
below OS-requested state to meet the power
limits."

> 
> Is there any documentation describing with more details the ABIs?
> 
Interesting, I just found this one,
Documentation/ABI/testing/sysfs-class-powercap, should we move it to
stable? Other than that, I don't know.

thanks,
rui