From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Tue, 30 Apr 2019 13:47:55 +0900 Message-ID: <9eb04a57-3e80-b0ba-334a-927493deb969@samsung.com> References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Lukasz Luba , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com List-Id: linux-pm@vger.kernel.org Hi, On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: > Define new IDs for clocks used by Dynamic Memory Controller in > Exynos5422 SoC. > > Acked-by: Rob Herring > Signed-off-by: Lukasz Luba > --- > include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h > index 355f469..abb1842 100644 > --- a/include/dt-bindings/clock/exynos5420.h > +++ b/include/dt-bindings/clock/exynos5420.h > @@ -60,6 +60,7 @@ > #define CLK_MAU_EPLL 159 > #define CLK_SCLK_HSIC_12M 160 > #define CLK_SCLK_MPHY_IXTAL24 161 > +#define CLK_SCLK_BPLL 162 > > /* gate clocks */ > #define CLK_UART0 257 > @@ -195,6 +196,18 @@ > #define CLK_ACLK432_CAM 518 > #define CLK_ACLK_FL1550_CAM 519 > #define CLK_ACLK550_CAM 520 > +#define CLK_CLKM_PHY0 521 > +#define CLK_CLKM_PHY1 522 > +#define CLK_ACLK_PPMU_DREX0_0 523 > +#define CLK_ACLK_PPMU_DREX0_1 524 > +#define CLK_ACLK_PPMU_DREX1_0 525 > +#define CLK_ACLK_PPMU_DREX1_1 526 > +#define CLK_PCLK_PPMU_DREX0_0 527 > +#define CLK_PCLK_PPMU_DREX0_1 528 > +#define CLK_PCLK_PPMU_DREX1_0 529 > +#define CLK_PCLK_PPMU_DREX1_1 530 > +#define CLK_CDREX_PAUSE 531 > +#define CLK_CDREX_TIMING_SET 532 I cannot find the usage code of both CLK_CDREX_PAUSE and CLK_CDREX_TIMING_SET in these patchset. Please remove them. (snip) -- Best Regards, Chanwoo Choi Samsung Electronics From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90590C43219 for ; Tue, 30 Apr 2019 04:46:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 552A721670 for ; Tue, 30 Apr 2019 04:46:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="FQqf6KGk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725554AbfD3Equ (ORCPT ); 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Tue, 30 Apr 2019 04:46:40 +0000 (GMT) Subject: Re: [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 To: Lukasz Luba , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com From: Chanwoo Choi Organization: Samsung Electronics Message-ID: <9eb04a57-3e80-b0ba-334a-927493deb969@samsung.com> Date: Tue, 30 Apr 2019 13:47:55 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> Content-Language: en-US Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNJsWRmVeSWpSXmKPExsWy7bCmga7h5eMxBlfuCVlsnLGe1WL+kXOs Fqs/Pma0mHxqLpPFme5ci/7Hr5ktzp/fwG5xtukNu8WtBhmLy7vmsFl87j3CaDHj/D4mi7VH 7rJb3G5cwWZx+E07q8X+K14Wt3/zWXw78YjRQcjj29dJLB6zGy6yeOycdZfdY9OqTjaP3uZ3 bB4H3+1h8ujbsorRY/Ppao/Pm+QCOKOybTJSE1NSixRS85LzUzLz0m2VvIPjneNNzQwMdQ0t LcyVFPISc1NtlVx8AnTdMnOAnlFSKEvMKQUKBSQWFyvp29kU5ZeWpCpk5BeX2CqlFqTkFFgW 6BUn5haX5qXrJefnWhkaGBiZAhUmZGcs77jBWjCbp2Ly526mBsY+ri5GTg4JAROJhU9vsHQx cnEICexglFiz7z0rhPOJUWJhVxszhPONUeLU8SWsMC33N96FqtrLKDHz6yoo5z2jRPPEh2wg VcICkRIrX09hAkmICCxnlNg39S4jiMMssJpJ4s/XtWCz2AS0JPa/uAHWwS+gKHH1x2OgIg4O XgE7iW27DUDCLAKqEud37WECsUUFIiTuH9sA1sorIChxcuYTFpByTgFviYtzZUHCzALiEree zGeCsOUlmrfOZoa4+hG7xP97ZRC2i0T/nQ6ob4QlXh3fwg5hS0l8freXDcKullh58ggbyMkS Ah2MElv2X4BqMJbYv3QyE8heZgFNifW79CF28Um8+9rDChKWEOCV6GgTgqhWlrj84C4ThC0p sbi9E2q8h8T1Y09ZJzAqzkLyzCwkH8xC8sEshGULGFlWMYqlFhTnpqcWGxYYI8f2JkZwQtcy 38G44ZzPIUYBDkYlHl6Pd8dihFgTy4orcw8xSnAwK4nwehw/GiPEm5JYWZValB9fVJqTWnyI 0RQY1hOZpUST84HZJq8k3tDUyNjY2MLE0MzU0FBJnHe9g3OMkEB6YklqdmpqQWoRTB8TB6dU A6MKp46WfhN/YuSGA/Nmamxyf/Pm7tNV/02v3lx8Mq36oGhAs2PMeR3jBn23Tc1bEhN+HZP3 md6jKnTe74/P8if6X94y2wsrJ8jl1b8MehK/zW+L1YdYh6SwC3Y31rDOWs5R2KL56ORBlmOS XqaW0ed3dcc0Xu7yKFPTln2ZtmfD1HjhHSLTHiqxFGckGmoxFxUnAgDBz3ur/gMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsWy7bCSvK7B5eMxBvemWVpsnLGe1WL+kXOs Fqs/Pma0mHxqLpPFme5ci/7Hr5ktzp/fwG5xtukNu8WtBhmLy7vmsFl87j3CaDHj/D4mi7VH 7rJb3G5cwWZx+E07q8X+K14Wt3/zWXw78YjRQcjj29dJLB6zGy6yeOycdZfdY9OqTjaP3uZ3 bB4H3+1h8ujbsorRY/Ppao/Pm+QCOKO4bFJSczLLUov07RK4MpZ33GAtmM1TMflzN1MDYx9X FyMnh4SAicT9jXdZuxi5OIQEdjNK9P47ygiRkJSYdvEocxcjB5AtLHH4cDFEzVtGia+/97KA 1AgLREqsfD2FCSQhIrCcUWLu36UsIA6zwGomiUkft7BBtNxnlHj5oY8NpIVNQEti/4sbYDa/ gKLE1R+PGUFW8ArYSWzbbQASZhFQlTi/aw8TiC0qECFx5v0KsG28AoISJ2c+YQEp5xTwlrg4 VxYkzCygLvFn3iVmCFtc4taT+UwQtrxE89bZzBMYhWch6Z6FpGUWkpZZSFoWMLKsYpRMLSjO Tc8tNiwwzEst1ytOzC0uzUvXS87P3cQIjm0tzR2Ml5fEH2IU4GBU4uH1eHcsRog1say4MvcQ owQHs5IIr8fxozFCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeZ/mHYsUEkhPLEnNTk0tSC2CyTJx cEo1MJqGHJW8kOpybf6rn8XRM50X5yn/+ZByz6VD4my61BORqiNHvQ1PHGhPDVp2V7oq5Ojh hrWXNP8suNustmxZ40fz84on+L8wx4lJqLGu2/IkdeKEtqrbVeeS925kilsr2dix3+Kl5oVz +4s+v9psH7TJb4lk9cMjO34Upr467DT90T7D+raMUw+UWIozEg21mIuKEwH+1W086QIAAA== X-CMS-MailID: 20190430044641epcas1p16b04ecf625625ca1ddd964392da9e638 X-Msg-Generator: CA Content-Type: text/plain; charset="UTF-8" CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Message-ID: <20190430044755.khjAxAnvrlqPC2aPtG71GnW68MownhffqdQl__9AxX0@z> Hi, On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: > Define new IDs for clocks used by Dynamic Memory Controller in > Exynos5422 SoC. > > Acked-by: Rob Herring > Signed-off-by: Lukasz Luba > --- > include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h > index 355f469..abb1842 100644 > --- a/include/dt-bindings/clock/exynos5420.h > +++ b/include/dt-bindings/clock/exynos5420.h > @@ -60,6 +60,7 @@ > #define CLK_MAU_EPLL 159 > #define CLK_SCLK_HSIC_12M 160 > #define CLK_SCLK_MPHY_IXTAL24 161 > +#define CLK_SCLK_BPLL 162 > > /* gate clocks */ > #define CLK_UART0 257 > @@ -195,6 +196,18 @@ > #define CLK_ACLK432_CAM 518 > #define CLK_ACLK_FL1550_CAM 519 > #define CLK_ACLK550_CAM 520 > +#define CLK_CLKM_PHY0 521 > +#define CLK_CLKM_PHY1 522 > +#define CLK_ACLK_PPMU_DREX0_0 523 > +#define CLK_ACLK_PPMU_DREX0_1 524 > +#define CLK_ACLK_PPMU_DREX1_0 525 > +#define CLK_ACLK_PPMU_DREX1_1 526 > +#define CLK_PCLK_PPMU_DREX0_0 527 > +#define CLK_PCLK_PPMU_DREX0_1 528 > +#define CLK_PCLK_PPMU_DREX1_0 529 > +#define CLK_PCLK_PPMU_DREX1_1 530 > +#define CLK_CDREX_PAUSE 531 > +#define CLK_CDREX_TIMING_SET 532 I cannot find the usage code of both CLK_CDREX_PAUSE and CLK_CDREX_TIMING_SET in these patchset. Please remove them. (snip) -- Best Regards, Chanwoo Choi Samsung Electronics