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From: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: Maxime Ripard
	<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	Quentin Schulz
	<quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	linux-arm-kernel
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	linux-kernel
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-clk <linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"open list:THERMAL"
	<linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-sunxi <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
Subject: Re: [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
Date: Sun, 9 Apr 2017 09:05:32 +0800	[thread overview]
Message-ID: <CAGb2v67qxuFhN_oB4YqSTa04pb7T-7CQcmOrSUoTGTKMjW9CPg@mail.gmail.com> (raw)
In-Reply-To: <20170408185025.53841-3-icenowy-h8G6r0blFSE@public.gmane.org>

Hi,

On Sun, Apr 9, 2017 at 2:50 AM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:

The subject can just say "set CLK_SET_RATE_PARENT for CPUX clock on H3".

> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
>
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX clock.
>

This paragraph needs some work, particularly the verbs you chose. In the
clk subsystem "setting parent clock" actually refers to re-parenting.

>From include/linux/clk-provider.h:

#define CLK_SET_RATE_PARENT     BIT(2) /* propagate rate change up one level */

So what you want to say is to propagate rate changes to CPUX up one
level, so PLL_CPUX gets changed as well.

The precise wording could be something like:

    The CPUX clock is the clock source for the ARM cores on the H3 SoC.
    It is a mux clock fed by, amongst other fixed clock sources, the
    configurable PLL_CPUX.

    Set CLK_SET_RATE_PARENT on the CPUX clock, so rate changes to it
    are propagated up one level to the PLL_CPUX clock.

ChenYu

> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index 4cbc1b701b7c..90b4e26a70bc 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
>  static const char * const cpux_parents[] = { "osc32k", "osc24M",
>                                              "pll-cpux" , "pll-cpux" };
>  static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> -                    0x050, 16, 2, CLK_IS_CRITICAL);
> +                    0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
>
> --
> 2.12.2
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> For more options, visit https://groups.google.com/d/optout.

  parent reply	other threads:[~2017-04-09  1:05 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-08 18:50 [PATCH 0/5] Some Allwinner CCU tweaks and basical DVFS support for H3/H2+ Icenowy Zheng
2017-04-08 18:50 ` [PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq Icenowy Zheng
     [not found]   ` <20170408185025.53841-2-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-08 21:59     ` 'Ondřej Jirman' via linux-sunxi
2017-04-08 18:50 ` [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Icenowy Zheng
     [not found]   ` <20170408185025.53841-3-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-09  1:05     ` Chen-Yu Tsai [this message]
2017-04-08 18:50 ` [PATCH 3/5] cpufreq: dt: Add support for some new Allwinner SoCs Icenowy Zheng
2017-04-11  7:03   ` Viresh Kumar
     [not found] ` <20170408185025.53841-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-08 18:50   ` [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU Icenowy Zheng
     [not found]     ` <20170408185025.53841-5-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-11  9:13       ` Maxime Ripard
2017-04-11 13:28         ` icenowy
     [not found]           ` <b37490ed1282f45542168701dea332bb-h8G6r0blFSE@public.gmane.org>
2017-04-16 20:57             ` Maxime Ripard
2017-04-16 21:00               ` Icenowy Zheng
     [not found]                 ` <40F4D1F2-EA59-4BD1-9A00-4C0AA7FED9D3-h8G6r0blFSE@public.gmane.org>
2017-04-17  7:46                   ` Maxime Ripard
2017-04-16 21:06               ` icenowy-h8G6r0blFSE
2017-04-08 18:50   ` [PATCH 5/5] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board Icenowy Zheng

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