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Wed, 16 Oct 2019 02:08:50 -0700 (PDT) MIME-Version: 1.0 References: <20191004090114.30694-1-glaroque@baylibre.com> <20191004090114.30694-7-glaroque@baylibre.com> In-Reply-To: <20191004090114.30694-7-glaroque@baylibre.com> From: Amit Kucheria Date: Wed, 16 Oct 2019 14:38:39 +0530 Message-ID: Subject: Re: [PATCH v7 6/7] arm64: dts: amlogic: g12b: add cooling properties To: Guillaume La Roque Cc: Zhang Rui , Eduardo Valentin , Daniel Lezcano , Linux PM list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , lakml , linux-amlogic@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Fri, Oct 4, 2019 at 2:31 PM Guillaume La Roque wrote: > > Add missing #colling-cells field for G12B SoC > Add cooling-map for passive and hot trip point > > Tested-by: Christian Hewitt > Tested-by: Kevin Hilman > Reviewed-by: Neil Armstrong > Signed-off-by: Guillaume La Roque Reviewed-by: Amit Kucheria > --- > arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 29 +++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > index 98ae8a7c8b41..4bb89bce758f 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > @@ -49,6 +49,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu1: cpu@1 { > @@ -57,6 +58,7 @@ > reg = <0x0 0x1>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu100: cpu@100 { > @@ -65,6 +67,7 @@ > reg = <0x0 0x100>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu101: cpu@101 { > @@ -73,6 +76,7 @@ > reg = <0x0 0x101>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu102: cpu@102 { > @@ -81,6 +85,7 @@ > reg = <0x0 0x102>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > cpu103: cpu@103 { > @@ -89,6 +94,7 @@ > reg = <0x0 0x103>; > enable-method = "psci"; > next-level-cache = <&l2>; > + #cooling-cells = <2>; > }; > > l2: l2-cache0 { > @@ -219,3 +225,26 @@ > &sd_emmc_a { > amlogic,dram-access-quirk; > }; > + > +&cpu_thermal { > + cooling-maps { > + map0 { > + trip = <&cpu_passive>; > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu_hot>; > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > +}; > -- > 2.17.1 >