* [PATCH v2] cpufreq: powerpc: add cpufreq transition latency for FSL e500mc Socs
@ 2014-03-18 5:41 Zhuoyu Zhang
2014-03-18 6:27 ` Viresh Kumar
0 siblings, 1 reply; 2+ messages in thread
From: Zhuoyu Zhang @ 2014-03-18 5:41 UTC (permalink / raw)
To: rjw; +Cc: viresh.kumar, cpufreq, linux-pm, Yuantian.Tang, Zhuoyu.Zhang
According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.
Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
---
drivers/cpufreq/ppc-corenet-cpufreq.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c
index 051000f..5977f57 100644
--- a/drivers/cpufreq/ppc-corenet-cpufreq.c
+++ b/drivers/cpufreq/ppc-corenet-cpufreq.c
@@ -21,6 +21,7 @@
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>
+#include <sysdev/fsl_soc.h>
/**
* struct cpu_data - per CPU data struct
@@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
for_each_cpu(i, per_cpu(cpu_mask, cpu))
per_cpu(cpu_data, i) = data;
- policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+ policy->cpuinfo.transition_latency =
+ (12 * NSEC_PER_SEC) / fsl_get_sys_freq();
of_node_put(np);
return 0;
--
1.8.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] cpufreq: powerpc: add cpufreq transition latency for FSL e500mc Socs
2014-03-18 5:41 [PATCH v2] cpufreq: powerpc: add cpufreq transition latency for FSL e500mc Socs Zhuoyu Zhang
@ 2014-03-18 6:27 ` Viresh Kumar
0 siblings, 0 replies; 2+ messages in thread
From: Viresh Kumar @ 2014-03-18 6:27 UTC (permalink / raw)
To: Zhuoyu Zhang
Cc: Rafael J. Wysocki, cpufreq@vger.kernel.org,
linux-pm@vger.kernel.org, Yuantian.Tang
On 18 March 2014 11:11, Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> wrote:
> According to the data provided by HW Team, at least 12 internal platform
> clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
> This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
> latency to make DFS governors work normally on Freescale e500mc boards.
>
> Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
> ---
> drivers/cpufreq/ppc-corenet-cpufreq.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c
> index 051000f..5977f57 100644
> --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
> +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c
> @@ -21,6 +21,7 @@
> #include <linux/of.h>
> #include <linux/slab.h>
> #include <linux/smp.h>
> +#include <sysdev/fsl_soc.h>
>
> /**
> * struct cpu_data - per CPU data struct
> @@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> for_each_cpu(i, per_cpu(cpu_mask, cpu))
> per_cpu(cpu_data, i) = data;
>
> - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
> + policy->cpuinfo.transition_latency =
> + (12 * NSEC_PER_SEC) / fsl_get_sys_freq();
> of_node_put(np);
>
> return 0;
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
^ permalink raw reply [flat|nested] 2+ messages in thread
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