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Wysocki" , "Daniel Lezcano" , "Zhang Rui" , "Lukasz Luba" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Krzysztof Kozlowski" , "Alim Akhtar" , "Bartlomiej Zolnierkiewicz" , "Kees Cook" , "Gustavo A. R. Silva" , "Peter Griffin" , =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: aerc 0.20.0 References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> <20260119-acpm-tmu-v2-1-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-1-e02a834f04c6@linaro.org> Hi Tudor, On Mon Jan 19, 2026 at 12:08 PM GMT, Tudor Ambarus wrote: > Document the Thermal Management Unit (TMU) found on the Google GS101 SoC. > > The GS101 TMU utilizes a hybrid control model shared between the > Application Processor (AP) and the ACPM (Alive Clock and Power Manager) > firmware. > > While the TMU is a standard memory-mapped IP block, on this platform this ^^ > the AP's direct register access is restricted to the interrupt pending > (INTPEND) registers for event identification. High-level functional > tasks, such as sensor initialization, threshold programming, and > temperature reads, are delegated to the ACPM firmware. > > Signed-off-by: Tudor Ambarus > --- > .../bindings/thermal/google,gs101-tmu-top.yaml | 67 ++++++++++++++++= ++++++ > 1 file changed, 67 insertions(+) > > diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-t= op.yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.ya= ml > new file mode 100644 > index 0000000000000000000000000000000000000000..b09e1ff5d89194b570810a042= c75836ca2e53950 > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google GS101 Thermal Management Unit (TMU) > + > +maintainers: > + - Tudor Ambarus > + > +description: > + The Google GS101 TMU is a thermal sensor block that supports both dire= ct > + register-level access and firmware-mediated management via the ACPM > + (Alive Clock and Power Manager) firmware. > + > + On this platform, the hardware is managed in a hybrid fashion. The > + Application Processor (AP) maintains direct memory-mapped access > + exclusively to the interrupt pending registers to identify thermal > + events. All other functional aspects - including sensor > + initialization, threshold configuration, and temperature acquisition > + - are handled by the ACPM firmware. The AP coordinates these > + operations through the ACPM IPC protocol. Is it Google TMU hardware block or Exynos/Samsung TMU block? My understanding at this point is that ACPM interface, ACPM protocols, etc appeared on Samsung SoCs before gs101 (maybe even before initial SCMI prototyping). It looks like ACPM firmware, communication via mailboxes, TMU channel, dealing with TMU behing ACPM, etc are actually a standard Samsung Exynos architectural feature, rather than a Google-specific implementation. I can't say though what was the first chipset where it was implemented. Given that this is a Samsung design that predates the gs101, would it make sense to use more generic name for this binding to reflect that it is Exynos-derived? That would save us from generalizing things later (if it happens, and I hope it happens). I was thinking that name for this schema could be smth like: samsung,acpm-tmu.yaml or samsung,exynos-acpm-tmu.yaml or whatever works. Thanks, Alexey