Re: [PATCH v3 3/3] riscv: dts: spacemit: Add thermal sensor for K1 SoC

Anand Moon
2026-04-23T03:46:57Z

Hi Shuwei,

On Wed, 22 Apr 2026 at 16:07, Shuwei Wu <shuwei.wu@mailbox.org> wrote:
>
> Hi Anand,
>
> Thank you for the careful review.
>
> On Wed Apr 22, 2026 at 1:56 PM CST, Anand Moon wrote:
> > Hi Shuwei,
> >
> > On Mon, 19 Jan 2026 at 08:13, Shuwei Wu <shuweiwoo@163.com> wrote:
> >>
> >> Include the Thermal Sensor node in the SpacemiT K1 dtsi
> >> with definitions for registers, clocks, and interrupts.
> >> Additionally, configure thermal zones for the soc, package, gpu, and
> >> clusters to enable temperature monitoring via the thermal framework.
> >>
> >> Signed-off-by: Shuwei Wu <shuweiwoo@163.com>
> >> ---
> >> Changes in v2:
> >> - Update compatible to "spacemit,k1-tsensor"
> >> ---
> >> arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++++++++++
> >> 1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> >> index 7818ca4979b6..0fe7396ea6e4 100644
> >> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> >> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> >> @@ -338,6 +338,96 @@ osc_32k: clock-32k {
> >> };
> >> };
> >>
> > I feel the thermal zones appear to be configured at significantly
> > higher temperatures
> > compared to the thresholds typically used in commercial-grade and
> > industrial-grade device
> > test environments 1.2 Test Environment
> >
> > [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k1/k1_hw/avl_veri_sop.md
>
> The official definition of this temperature range is as follows:
> "The CPU delivers stable and reliable computing power from -40°C to 85°C,
> complying with the demanding requirements of industrial applications."
>
> [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone
> /k1/k1_docs/root_overview.md
>
> Therefore, this does not mean that the chip cannot continue to work above
> this temperature.
>
> The datasheet also defines another temperature, the Junction Temperature,
> which represents the chip's temperature limit. Exceeding this temperature
> may permanently damage the chip.
>
> [2] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone
> /k1/k1_docs/k1_usermanual/4.Electrical_Characteristics.md
>
Ok,
> >
> > Thermal zones should be defined as part of the SBC board design,
> > with the option to integrate PWM-controlled fan support in the future.
>
> These thermal zones describe fixed hardware properties of the K1 SoC itself,
> and are common for all K1-based boards.
>
Ok,
> And this is also done in Allwinner D1, StarFive JH7110 and some other chips.
>
Ok thanks.
> >
> > Thanks
> > -Anand
> Best regards,
> Shuwei Wu
Thanks
-Anand