[PATCH 06/19] cpufreq: amd: add acpi cppc function as the backend for legacy processors

Huang Rui
2021-09-08T15:01:37Z

In some old Zen based processors, they are using the shared memory that
exposed from ACPI SBIOS.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/cpufreq/amd-pstate.c | 63 ++++++++++++++++++++++++++++++++----
1 file changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 32b4f6d79783..a46cd5dd9f7c 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -82,6 +82,19 @@ static inline int pstate_enable(bool enable)
return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0);
}

+static int cppc_enable(bool enable)
+{
+ int cpu, ret = 0;
+
+ for_each_online_cpu(cpu) {
+ ret = cppc_set_enable(cpu, enable ? 1 : 0);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
static int
amd_pstate_enable(struct amd_pstate_perf_funcs *funcs, bool enable)
{
@@ -113,6 +126,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
return 0;
}

+static int cppc_init_perf(struct amd_cpudata *cpudata)
+{
+ struct cppc_perf_caps cppc_perf;
+
+ int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
+ if (ret)
+ return ret;
+
+ WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf());
+
+ WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
+ WRITE_ONCE(cpudata->lowest_nonlinear_perf,
+ cppc_perf.lowest_nonlinear_perf);
+ WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
+
+ return 0;
+}
+
static int amd_pstate_init_perf(struct amd_cpudata *cpudata)
{
struct amd_pstate_perf_funcs *funcs = cpufreq_get_driver_data();
@@ -134,6 +165,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata,
READ_ONCE(cpudata->cppc_req_cached));
}

+static void cppc_update_perf(struct amd_cpudata *cpudata,
+ u32 min_perf, u32 des_perf,
+ u32 max_perf, bool fast_switch)
+{
+ struct cppc_perf_ctrls perf_ctrls;
+
+ perf_ctrls.max_perf = max_perf;
+ perf_ctrls.min_perf = min_perf;
+ perf_ctrls.desired_perf = des_perf;
+
+ cppc_set_perf(cpudata->cpu, &perf_ctrls);
+}
+
static int
amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
u32 des_perf, u32 max_perf, bool fast_switch)
@@ -370,6 +414,12 @@ static struct amd_pstate_perf_funcs pstate_funcs = {
.update_perf = pstate_update_perf,
};

+static struct amd_pstate_perf_funcs cppc_funcs = {
+ .enable = cppc_enable,
+ .init_perf = cppc_init_perf,
+ .update_perf = cppc_update_perf,
+};
+
static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
{
int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
@@ -416,7 +466,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
/* It will be updated by governor */
policy->cur = policy->cpuinfo.min_freq;

- policy->fast_switch_possible = true;
+ if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT))
+ policy->fast_switch_possible = true;

ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
FREQ_QOS_MIN, policy->cpuinfo.min_freq);
@@ -471,7 +522,6 @@ static struct cpufreq_driver amd_pstate_driver = {
.verify = amd_pstate_verify,
.target = amd_pstate_target,
.fast_switch = amd_pstate_fast_switch,
- .adjust_perf = amd_pstate_adjust_perf,
.init = amd_pstate_cpu_init,
.exit = amd_pstate_cpu_exit,
.name = "amd-pstate",
@@ -496,14 +546,15 @@ static int __init amd_pstate_init(void)
return -EEXIST;

/* capability check */
- if (!boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) {
+ if (boot_cpu_has(X86_FEATURE_AMD_CPPC_EXT)) {
pr_debug("%s, AMD CPPC extension functionality is supported\n",
__func__);
- return -ENODEV;
+ funcs = &pstate_funcs;
+ amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
+ } else {
+ funcs = &cppc_funcs;
}

- funcs = &pstate_funcs;
-
/* enable amd pstate feature */
ret = amd_pstate_enable(funcs, true);
if (ret) {
--
2.25.1