From: Drew Fustini <drew@pdp7.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
"Rafael J . Wysocki" <rafael@kernel.org>,
Pavel Machek <pavel@ucw.cz>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Len Brown <lenb@kernel.org>,
Anup Patel <anup@brainfault.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Atish Kumar Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v3 -next 0/3] RISC-V: ACPI: Add LPI support
Date: Thu, 14 Mar 2024 19:59:46 -0700 [thread overview]
Message-ID: <ZfO5oiVSVSmlP8eL@x1> (raw)
In-Reply-To: <20240118062930.245937-1-sunilvl@ventanamicro.com>
On Thu, Jan 18, 2024 at 11:59:27AM +0530, Sunil V L wrote:
> This series adds support for Low Power Idle (LPI) on ACPI based
> platforms.
>
> LPI is described in the ACPI spec [1]. RISC-V FFH spec required to
> enable this is available at [2].
I'm interested in trying out this series. Might you be able to provide
some guidance on how to setup a test environment?
Are there specific branches of qemu and edk2 that I should use?
thanks,
drew
next prev parent reply other threads:[~2024-03-15 2:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 6:29 [PATCH v3 -next 0/3] RISC-V: ACPI: Add LPI support Sunil V L
2024-01-18 6:29 ` [PATCH v3 -next 1/3] cpuidle: RISC-V: Move few functions to arch/riscv Sunil V L
2024-01-18 6:29 ` [PATCH v3 -next 2/3] ACPI: RISC-V: Add LPI driver Sunil V L
2024-03-18 5:33 ` Drew Fustini
2024-03-18 8:42 ` Sunil V L
2024-01-18 6:29 ` [PATCH v3 -next 3/3] ACPI: Enable ACPI_PROCESSOR for RISC-V Sunil V L
2024-02-15 4:37 ` [PATCH v3 -next 0/3] RISC-V: ACPI: Add LPI support Sunil V L
2024-03-15 12:31 ` Rafael J. Wysocki
2024-03-15 2:59 ` Drew Fustini [this message]
2024-03-15 5:53 ` Sunil V L
2024-03-20 20:50 ` patchwork-bot+linux-riscv
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