Re: [PATCH v3 -next 0/3] RISC-V: ACPI: Add LPI support

[Sunil V L <sunilvl@ventanamicro.com>]

Hi Drew,

On Thu, Mar 14, 2024 at 07:59:46PM -0700, Drew Fustini wrote:
> On Thu, Jan 18, 2024 at 11:59:27AM +0530, Sunil V L wrote:
> > This series adds support for Low Power Idle (LPI) on ACPI based
> > platforms. 
> > 
> > LPI is described in the ACPI spec [1]. RISC-V FFH spec required to
> > enable this is available at [2].
> 
> I'm interested in trying out this series. Might you be able to provide
> some guidance on how to setup a test environment?
> 
> Are there specific branches of qemu and edk2 that I should use?
> 
1) You need LPI objects in the platform. I have added dummy objects for
testing this for qemu virt machine. Please use below branch.

https://github.com/vlsunil/qemu/tree/lpi_exp

Since interrupt controllers are not merged yet in linux, we need to boot
without any IO devices and use only polling based console and ram disk.
Above qemu branch disables IO devices as well.

2) Enable below config options while building linux kernel.
RISCV_SBI_V01
HVC_RISCV_SBI

3) Use upstream EDK2 (RiscVVirt)

4) Boot:
qemu-system-riscv64 \
 -M virt,pflash0=pflash0,pflash1=pflash1 \
 -m 2G -smp 8 \
 -serial mon:stdio \
 -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
 -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \
 -kernel arch/riscv/boot/Image \
 -initrd buildroot/output/images/rootfs.cpio \
 -append "root=/dev/ram ro console=hvc earlycon=sbi"

Feel free to ping me if you have any difficulties.

Thanks!
Sunil