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* Re: ARM64: Where do I get CPU Sleep states parameters ?
       [not found] <CAO6a-9-cp7CazJ4+-b3gwD2Q5n4SaA=5=Ps3ycJ9Xq_ZidDB+A@mail.gmail.com>
@ 2024-10-08 15:52 ` Sudeep Holla
       [not found]   ` <CAO6a-98koymFJM3X1QDdoybz+SdR_g+C5=vbt_BjS=dYOQJBAg@mail.gmail.com>
  0 siblings, 1 reply; 2+ messages in thread
From: Sudeep Holla @ 2024-10-08 15:52 UTC (permalink / raw)
  To: Vivek yadav; +Cc: linux-pm, lpieralisi, ulf.hansson, Sudeep Holla

On Tue, Oct 08, 2024 at 08:46:52PM +0530, Vivek yadav wrote:
> Hi @all
>
> Recently I was exploring the CPUIdle menu governor. I found out that
> there are CPUIdle states. These C- states are defined in the device
> tree based on these `cpu-idle-state` parameters. The menu governor
> makes intelligent decisions. So it can save precious power resources.
>
> I had one custom SoC which had a CPU `arm,cortex-a55`. Now I am
> looking for CPU properties i.e exit_latency, entry_latency and
> min-residency.
>
> Below there are two different SoC using the same arm,cortex-a55 CPU. But
> they are using different values.
>
> Q.1: There are entry | exit | min-latency-us. Where will I get all that
> information? I searched into ARM manuals but I did not get it ? Please
> point me in the right direction if you know about this.

It is completely SoC/platform or even board specific parameter. One needs
to measure it for that configuration and then populate the value in DT.

> Q.2: It looks like every SoC is using any value ? Why is there no fixed
> latency time ?

There can't be a fixed value that works across platforms as the value
is depends on various characteristics of a given platform.

> Q.3:  What is the meaning of ``arm,psci-suspend-param`` ? Where do I get
> this information? It is some fixed value.

Even this is not fixed, but if you follow some guidelines in the spec,
you can have a fixed pattern based values. But that is completely optional.
The firmware may choose a value compliant to the spec and you just put that
in the DT for OS to use it when entering the required state.

> Q.4: Is it necessary to add  ``local-timer-stop`` ? In ``config`` file we
> are providing information about the CPU periodic tick whether we want to
> use a tickless governor or not ?

Again it depends. The DT bindings explain all these IIRC. Anyways if you
CPU local timers(it will be mostly architected timer on arm64) gets turned
off when the CPU enters the C state, then you need to add this boolean
property.

>
> FILE NAME :::   ``arch/arm64/boot/dts/mediatek/mt8186.dtsi``.
>
> ``` <Code Block>
>                 idle-states {
>                         entry-method = "psci";
>
>                         cpu_ret_l: cpu-retention-l {
>                                 compatible = "arm,idle-state";
>                                 arm,psci-suspend-param = <0x00010001>;
>                                 local-timer-stop;

It is unlikely a retention state will have its local CPU timer turned off
but it may be true on this platform. I don't know.

>                                 entry-latency-us = <50>;
>                                 exit-latency-us = <100>;
>                                 min-residency-us = <1600>;
>                         };
>
>                         cpu_ret_b: cpu-retention-b {
>                                 compatible = "arm,idle-state";
>                                 arm,psci-suspend-param = <0x00010001>;
>                                 local-timer-stop;
>                                 entry-latency-us = <50>;
>                                 exit-latency-us = <100>;
>                                 min-residency-us = <1400>;
>                         };
>
>                         cpu_off_l: cpu-off-l {
>                                 compatible = "arm,idle-state";
>                                 arm,psci-suspend-param = <0x01010001>;
>                                 local-timer-stop;
>                                 entry-latency-us = <100>;
>                                 exit-latency-us = <250>;
>                                 min-residency-us = <2100>;
>                         };
>
>                         cpu_off_b: cpu-off-b {
>                                 compatible = "arm,idle-state";
>                                 arm,psci-suspend-param = <0x01010001>;

These psci-suspend-param looks like they have followed the recommendation/
example in the specification.

--
Regards,
Sudeep

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: ARM64: Where do I get CPU Sleep states parameters ?
       [not found]   ` <CAO6a-98koymFJM3X1QDdoybz+SdR_g+C5=vbt_BjS=dYOQJBAg@mail.gmail.com>
@ 2024-10-09 10:45     ` Sudeep Holla
  0 siblings, 0 replies; 2+ messages in thread
From: Sudeep Holla @ 2024-10-09 10:45 UTC (permalink / raw)
  To: Vivek yadav; +Cc: linux-pm, lpieralisi, ulf.hansson, Sudeep Holla

On Wed, Oct 09, 2024 at 07:47:18AM +0530, Vivek yadav wrote:
> >> Hi @all
> >>
> >> Recently I was exploring the CPUIdle menu governor. I found out that
> >> there are CPUIdle states. These C- states are defined in the device
> >> tree based on these `cpu-idle-state` parameters. The menu governor
> >> makes intelligent decisions. So it can save precious power resources.
> >>
> >> I had one custom SoC which had a CPU `arm,cortex-a55`. Now I am
> >> looking for CPU properties i.e exit_latency, entry_latency and
> >> min-residency.
> >>
> >> Below there are two different SoC using the same arm,cortex-a55 CPU. But
> >> they are using different values.
> >>
> >> Q.1: There are entry | exit | min-latency-us. Where will I get all that
> >> information? I searched into ARM manuals but I did not get it ? Please
> >> point me in the right direction if you know about this.
> >
> >It is completely SoC/platform or even board specific parameter. One needs
> >to measure it for that configuration and then populate the value in DT.
>
> One needs to measure it means there are tools to measure CPUIdle time
> OR  do you mean these latency values need to be fine tuned by developer
> via hit and trial method. Which suits the SoC/board.
> Please correct me if I am wrong.
>

I wouldn't say trial and error. It involved trying to hit worst case scenario
and taking some timing info on the platform(via trace or whatever suits best
on the platform and the firmware running). E.g. Can you access cache memory on
DRAM in such a way that achieves maximum dirty cacheline ? Some power
measurements by forceful wakeup so that you can get better tuned value for
minimum residency.


--
Regards,
Sudeep

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2024-10-08 15:52 ` ARM64: Where do I get CPU Sleep states parameters ? Sudeep Holla
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