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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58f2b02sm19714077f8f.51.2025.05.14.04.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 04:23:53 -0700 (PDT) Date: Wed, 14 May 2025 13:23:51 +0200 From: Daniel Lezcano To: Anand Moon Cc: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba , Alim Akhtar , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , "open list:SAMSUNG THERMAL DRIVER" , "open list:SAMSUNG THERMAL DRIVER" , "moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" , open list , "open list:CLANG/LLVM BUILD SUPPORT:Keyword:b(?i:clang|llvm)b" Subject: Re: [PATCH v6 0/4] Exynos Thermal code improvement Message-ID: References: <20250430123306.15072-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250430123306.15072-1-linux.amoon@gmail.com> On Wed, Apr 30, 2025 at 06:02:56PM +0530, Anand Moon wrote: > Hi All, Hi Anand, if the goal of the changes is to do cleanups, I recommend to rework how the code is organized. Instead of having the data->soc check all around the functions, write per platform functions and store them in struct of_device_id data field instead of the soc version. Basically get rid of exynos_map_dt_data by settings the different ops in a per platform structure. Then the initialization routine would be simpler to clean. > This patch series is a rework of my previous patch series [1], > where the code changes were not adequately justified. > > In this new series, I have improved the commit subject > and commit message to better explain the changes. > > v6: Add new patch to use devm_clk_get_enabled > and Fix few typo in subject as suggested by Daniel. > v5: Drop the guard mutex patch > v4: Tried to address Lukasz review comments. > > Tested on Odroid U3 amd XU4 SoC boards. > Build with clang with W=1 enable. > > [4] https://lore.kernel.org/all/20250410063754.5483-2-linux.amoon@gmail.com/ > [3] https://lore.kernel.org/all/20250310143450.8276-2-linux.amoon@gmail.com/ > [2] https://lore.kernel.org/all/20250216195850.5352-2-linux.amoon@gmail.com/ > [1] https://lore.kernel.org/all/20220515064126.1424-1-linux.amoon@gmail.com/ > [0] https://lore.kernel.org/lkml/CANAwSgS=08fVsqn95WHzSF71WTTyD2-=K2C6-BEz0tY0t6A1-g@mail.gmail.com/T/#m77e57120d230d57f34c29e1422d7fc5f5587ac30 > > Thanks > -Anand > > Anand Moon (4): > thermal/drivers/exynos: Refactor clk_sec initialization inside > SOC-specific case > thermal/drivers/exynos: Use devm_clk_get_enabled() helpers > thermal/drivers/exynos: Remove redundant IS_ERR() checks for clk_sec > clock > thermal/drivers/exynos: Fixed the efuse min max value for exynos5422 > > drivers/thermal/samsung/exynos_tmu.c | 100 ++++++++++----------------- > 1 file changed, 35 insertions(+), 65 deletions(-) > > > base-commit: b6ea1680d0ac0e45157a819c41b46565f4616186 > -- > 2.49.0 > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog