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Mon, 12 Jan 2026 01:45:55 +0100 (CET) Date: Mon, 12 Jan 2026 01:45:55 +0100 From: Sebastian Reichel To: Matti Vaittinen Cc: Matti Vaittinen , Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, Andreas Kemnade Subject: Re: [PATCH RESEND v6 15/17] power: supply: bd71828: Support wider register addresses Message-ID: References: <57c87f7e2082a666f0adeafcd11f673c0af7d326.1765804226.git.mazziesaccount@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="p53qtk3uydhqcv77" Content-Disposition: inline In-Reply-To: <57c87f7e2082a666f0adeafcd11f673c0af7d326.1765804226.git.mazziesaccount@gmail.com> X-Zoho-Virus-Status: 1 X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-1.5.1/268.172.5 X-ZohoMailClient: External --p53qtk3uydhqcv77 Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH RESEND v6 15/17] power: supply: bd71828: Support wider register addresses MIME-Version: 1.0 Hi, On Mon, Dec 15, 2025 at 03:21:03PM +0200, Matti Vaittinen wrote: > From: Matti Vaittinen >=20 > The BD71828 power-supply driver assumes register addresses to be 8-bit. > The new BD72720 will use stacked register maps to hide paging which is > done using secondary I2C slave address. This requires use of 9-bit > register addresses in the power-supply driver (added offset 0x100 to > the 8-bit hardware register addresses). >=20 > The cost is slightly used memory consumption as the members in the > struct pwr_regs will be changed from u8 to unsigned int, which means 3 > byte increase / member / instance. > This is currently 14 members (expected to possibly be increased when > adding new variants / new functionality which may introduce new > registers, but not expected to grow much) and 2 instances (will be 3 > instances when BD72720 gets added). >=20 > So, even if the number of registers grew to 50 it'd be 150 bytes / > instance. Assuming we eventually supported 5 variants, it'd be > 5 * 150 bytes, which stays very reasonable considering systems we are > dealing with. >=20 > As a side note, we can reduce the "wasted space / member / instance" from > 3 bytes to 1 byte, by using u16 instead of the unsigned int if needed. I > rather use unsigned int to be initially prepared for devices with 32 bit > registers if there is no need to count bytes. >=20 > Signed-off-by: Matti Vaittinen > --- Reviewed-by: Sebastian Reichel Greetings, -- Sebastian > Revision history: > v2 =3D> : > - No changes >=20 > RFCv1 =3D> v2: > - New patch > --- > drivers/power/supply/bd71828-power.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/power/supply/bd71828-power.c b/drivers/power/supply/= bd71828-power.c > index f667baedeb77..ce73c0f48397 100644 > --- a/drivers/power/supply/bd71828-power.c > +++ b/drivers/power/supply/bd71828-power.c > @@ -44,19 +44,19 @@ > #define VBAT_LOW_TH 0x00D4 > =20 > struct pwr_regs { > - u8 vbat_avg; > - u8 ibat; > - u8 ibat_avg; > - u8 btemp_vth; > - u8 chg_state; > - u8 bat_temp; > - u8 dcin_stat; > - u8 dcin_collapse_limit; > - u8 chg_set1; > - u8 chg_en; > - u8 vbat_alm_limit_u; > - u8 conf; > - u8 vdcin; > + unsigned int vbat_avg; > + unsigned int ibat; > + unsigned int ibat_avg; > + unsigned int btemp_vth; > + unsigned int chg_state; > + unsigned int bat_temp; > + unsigned int dcin_stat; > + unsigned int dcin_collapse_limit; > + unsigned int chg_set1; > + unsigned int chg_en; > + unsigned int vbat_alm_limit_u; > + unsigned int conf; > + unsigned int vdcin; > }; > =20 > static const struct pwr_regs pwr_regs_bd71828 =3D { > --=20 > 2.52.0 >=20 --p53qtk3uydhqcv77 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmlkREAACgkQ2O7X88g7 +prsXA/9Eyvov5f12fyRIhmjYutdiaP1GuAKhRbEGDFkORkT6ugco4syK9vPy6Nz tgkcW9JgdAZGyJLN+DIfdV207IigO2u2v2pKebeCVE0QcP1nHDW1SvM+s+yqAnxQ fEITKr+r8AYhGsHUowtpeRwG5ZFWdqqBboqxJIwmKcRiFKqk94dL+qy5uZ3omhyX DRmRuYtm8Zof8bPH4tafWQjocvw7Hi9rsgODvy78+ubKosSHEz/x9VJ3K3Bs3s4d DUyHFQciqP+mxBALwSCnMKrAojyi7kICS1Sb4JcUJ0vWeFR6iSfPYdVbrtHDmv8c CEOcZiU54nFicBTcqe3ttHc/TUD3absKgvQW6Z7kUPQFmuCJIH+Qdv/y4tbxi7q6 iPZVgFE+R+39DOx/f/cjnp/Bo0Si+LSnSG3lWB6zZkF8FCevdEDZkKyHdTBG/lOO rDQmwryrjtwtiQ9ALXK8odD0JPBxs8mSBhrgVjV6nRxxrWxa9K9/mMl6gXsMZfbD g8w+y+KbFxDEPo+Oave8z0b+s5y9mWvCwbrmlnbP7uSks0+WHj7hBuFOrBLbz2vg 9soeu2L7RFwCUbIUk07u/UFPEiL453f1EN2VpHOu/uDtzW9j+y5aORO0EBPb03Tq +dId3gphxAQJTMm8+rosZOWVA/GVs6kal4OizAMjrDFZ1HXnMkY= =O5nq -----END PGP SIGNATURE----- --p53qtk3uydhqcv77--