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X-CSE-ConnectionGUID: cpGBxTezQ7m+AKjDpWy40g== X-CSE-MsgGUID: CChaLPZmQKWS5RgbYKai3g== X-IronPort-AV: E=McAfee;i="6800,10657,11670"; a="73311197" X-IronPort-AV: E=Sophos;i="6.21,225,1763452800"; d="scan'208";a="73311197" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2026 00:57:09 -0800 X-CSE-ConnectionGUID: JwC21BClT52N5BFbRPnySQ== X-CSE-MsgGUID: RAtdZy/tSs2IStYTIHc58g== X-ExtLoop1: 1 Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.244.83]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2026 00:56:59 -0800 Date: Wed, 14 Jan 2026 10:56:57 +0200 From: Andy Shevchenko To: AngeloGioacchino Del Regno Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, sre@kernel.org, sboyd@kernel.org, krzk@kernel.org, dmitry.baryshkov@oss.qualcomm.com, quic_wcheng@quicinc.com, melody.olvera@oss.qualcomm.com, quic_nsekar@quicinc.com, ivo.ivanov.ivanov1@gmail.com, abelvesa@kernel.org, luca.weiss@fairphone.com, konrad.dybcio@oss.qualcomm.com, mitltlatltl@gmail.com, krishna.kurapati@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add() Message-ID: References: <20260114083957.9945-1-angelogioacchino.delregno@collabora.com> <20260114083957.9945-6-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260114083957.9945-6-angelogioacchino.delregno@collabora.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote: > Some Qualcomm PMICs integrate a SDAM device, internally located in > a specific address range reachable through SPMI communication. > > Instead of using the parent SPMI device (the main PMIC) as a kind > of syscon in this driver, register a new SPMI sub-device for SDAM > and initialize its own regmap with this sub-device's specific base > address, retrieved from the devicetree. > > This allows to stop manually adding the register base address to > every R/W call in this driver, as this can be, and is now, handled > by the regmap API instead. ... > + struct regmap_config sdam_regmap_config = { > + .reg_bits = 16, > + .val_bits = 8, > + .max_register = 0x100, Are you sure? This might be a bad naming, but here max == the last accessible. I bet it has to be 0xff (but since the address is 16-bit it might be actually 257 registers, but sounds very weird). > + .fast_io = true, > + }; ... > + rc = of_property_read_u32(dev->of_node, "reg", &sdam_regmap_config.reg_base); Why not device_property_read_u32(dev, ...) ? ... > + sdam->regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &sdam_regmap_config); > + if (IS_ERR(sdam->regmap)) > + return dev_err_probe(&pdev->dev, PTR_ERR(sdam->regmap), You have "dev". > + "Failed to get regmap handle\n"); -- With Best Regards, Andy Shevchenko