[PATCH v1 0/2] Add MSR-based RAPL PMU support

[PATCH v1 0/2] Add MSR-based RAPL PMU support

[Kuppuswamy Sathyanarayanan]

This patch series enables MSR-based PMU support for the Intel RAPL
driver in the Linux powercap subsystem.

Following are the patch details:

Patch 1/2 - Preparatory patch that updates the read_raw() interface
            to allow atomic-context callers.

Patch 2/2 - More details about motivation of this series and adds
            MSR-based RAPL PMU access support.

This series has been tested and verified in the Panther Lake and
Wildcat Lake platforms using perf tool.

Please let me know your review comments.

Kuppuswamy Sathyanarayanan (2):
  powercap: intel_rapl: Prepare read_raw interface for atomic-context
    callers
  powercap: intel_rapl: Enable MSR-based RAPL PMU support

 drivers/powercap/intel_rapl_common.c          | 36 +++++++++--------
 drivers/powercap/intel_rapl_msr.c             | 40 +++++++++++++++++--
 drivers/powercap/intel_rapl_tpmi.c            |  2 +-
 .../int340x_thermal/processor_thermal_rapl.c  |  2 +-
 include/linux/intel_rapl.h                    |  2 +-
 5 files changed, 59 insertions(+), 23 deletions(-)

-- 
2.43.0

[PATCH v1 1/2] powercap: intel_rapl: Prepare read_raw interface for atomic-context callers

[Kuppuswamy Sathyanarayanan]

The current read_raw() implementation of the TPMI, MMIO and MSR
interfaces does not distinguish between atomic and non-atomic callers.

rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
event handlers can invoke this function from atomic context where
sleeping or rescheduling is not allowed. In atomic context, the caller
is already executing on the target CPU, so a direct rdmsrq() is
sufficient.

To support such usage, introduce an atomic flag to the read_raw()
interface to allow callers pass the context information. Modify the
common RAPL code to propagate this flag, and set the flag to reflect
the calling contexts.

Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
read with rdmsrq() when running in atomic context, and a sanity check
to ensure target CPU matches the current CPU for such use cases.

The TPMI and MMIO implementations do not require special atomic
handling, so the flag is ignored in those paths.

This is a preparatory patch for adding MSR-based RAPL PMU support.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
 drivers/powercap/intel_rapl_common.c          | 24 ++++++++++---------
 drivers/powercap/intel_rapl_msr.c             | 16 ++++++++++++-
 drivers/powercap/intel_rapl_tpmi.c            |  2 +-
 .../int340x_thermal/processor_thermal_rapl.c  |  2 +-
 include/linux/intel_rapl.h                    |  2 +-
 5 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index c7e7f9bf5313..066779460bc8 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -253,7 +253,8 @@ struct rapl_primitive_info {
 static void rapl_init_domains(struct rapl_package *rp);
 static int rapl_read_data_raw(struct rapl_domain *rd,
 			      enum rapl_primitives prim,
-			      bool xlate, u64 *data);
+			      bool xlate, u64 *data,
+			      bool atomic);
 static int rapl_write_data_raw(struct rapl_domain *rd,
 			       enum rapl_primitives prim,
 			       unsigned long long value);
@@ -289,7 +290,7 @@ static int get_energy_counter(struct powercap_zone *power_zone,
 	cpus_read_lock();
 	rd = power_zone_to_rapl_domain(power_zone);
 
-	if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
+	if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now, false)) {
 		*energy_raw = energy_now;
 		cpus_read_unlock();
 
@@ -830,7 +831,8 @@ prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim)
  * 63-------------------------- 31--------------------------- 0
  */
 static int rapl_read_data_raw(struct rapl_domain *rd,
-			      enum rapl_primitives prim, bool xlate, u64 *data)
+			      enum rapl_primitives prim, bool xlate, u64 *data,
+			      bool atomic)
 {
 	u64 value;
 	enum rapl_primitives prim_fixed = prim_fixups(rd, prim);
@@ -852,7 +854,7 @@ static int rapl_read_data_raw(struct rapl_domain *rd,
 
 	ra.mask = rpi->mask;
 
-	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
+	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, atomic)) {
 		pr_debug("failed to read reg 0x%llx for %s:%s\n", ra.reg.val, rd->rp->name, rd->name);
 		return -EIO;
 	}
@@ -904,7 +906,7 @@ static int rapl_read_pl_data(struct rapl_domain *rd, int pl,
 	if (!is_pl_valid(rd, pl))
 		return -EINVAL;
 
-	return rapl_read_data_raw(rd, prim, xlate, data);
+	return rapl_read_data_raw(rd, prim, xlate, data, false);
 }
 
 static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
@@ -941,7 +943,7 @@ static int rapl_check_unit_core(struct rapl_domain *rd)
 
 	ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
 	ra.mask = ~0;
-	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
+	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) {
 		pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
 			ra.reg.val, rd->rp->name, rd->name);
 		return -ENODEV;
@@ -969,7 +971,7 @@ static int rapl_check_unit_atom(struct rapl_domain *rd)
 
 	ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
 	ra.mask = ~0;
-	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
+	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) {
 		pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
 			ra.reg.val, rd->rp->name, rd->name);
 		return -ENODEV;
@@ -1156,7 +1158,7 @@ static int rapl_check_unit_tpmi(struct rapl_domain *rd)
 
 	ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
 	ra.mask = ~0;
-	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
+	if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) {
 		pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
 			ra.reg.val, rd->rp->name, rd->name);
 		return -ENODEV;
@@ -1325,7 +1327,7 @@ static void rapl_update_domain_data(struct rapl_package *rp)
 			struct rapl_primitive_info *rpi = get_rpi(rp, prim);
 
 			if (!rapl_read_data_raw(&rp->domains[dmn], prim,
-						rpi->unit, &val))
+						rpi->unit, &val, false))
 				rp->domains[dmn].rdd.primitives[prim] = val;
 		}
 	}
@@ -1425,7 +1427,7 @@ static int rapl_check_domain(int domain, struct rapl_package *rp)
 	 */
 
 	ra.mask = ENERGY_STATUS_MASK;
-	if (rp->priv->read_raw(get_rid(rp), &ra) || !ra.value)
+	if (rp->priv->read_raw(get_rid(rp), &ra, false) || !ra.value)
 		return -ENODEV;
 
 	return 0;
@@ -1636,7 +1638,7 @@ static u64 event_read_counter(struct perf_event *event)
 	if (event->hw.idx < 0)
 		return 0;
 
-	ret = rapl_read_data_raw(&rp->domains[event->hw.idx], ENERGY_COUNTER, false, &val);
+	ret = rapl_read_data_raw(&rp->domains[event->hw.idx], ENERGY_COUNTER, false, &val, true);
 
 	/* Return 0 for failed read */
 	if (ret)
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index 4ed06c71a3ac..46b716ea45b2 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -102,12 +102,26 @@ static int rapl_cpu_down_prep(unsigned int cpu)
 	return 0;
 }
 
-static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
+static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool atomic)
 {
+	/*
+	 * When called from atomic-context (eg PMU event handler)
+	 * perform MSR read directly using rdmsrq().
+	 */
+	if (atomic) {
+		if (unlikely(smp_processor_id() != cpu))
+			return -EIO;
+
+		rdmsrq(ra->reg.msr, ra->value);
+		goto out;
+	}
+
 	if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) {
 		pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu);
 		return -EIO;
 	}
+
+out:
 	ra->value &= ra->mask;
 	return 0;
 }
diff --git a/drivers/powercap/intel_rapl_tpmi.c b/drivers/powercap/intel_rapl_tpmi.c
index 82201bf4685d..0a0b85f4528b 100644
--- a/drivers/powercap/intel_rapl_tpmi.c
+++ b/drivers/powercap/intel_rapl_tpmi.c
@@ -60,7 +60,7 @@ static DEFINE_MUTEX(tpmi_rapl_lock);
 
 static struct powercap_control_type *tpmi_control_type;
 
-static int tpmi_rapl_read_raw(int id, struct reg_action *ra)
+static int tpmi_rapl_read_raw(int id, struct reg_action *ra, bool atomic)
 {
 	if (!ra->reg.mmio)
 		return -EINVAL;
diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
index bde2cc386afd..bf51a17c5be6 100644
--- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
+++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
@@ -19,7 +19,7 @@ static const struct rapl_mmio_regs rapl_mmio_default = {
 	.limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2),
 };
 
-static int rapl_mmio_read_raw(int cpu, struct reg_action *ra)
+static int rapl_mmio_read_raw(int cpu, struct reg_action *ra, bool atomic)
 {
 	if (!ra->reg.mmio)
 		return -EINVAL;
diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h
index c0397423d3a8..e9ade2ff4af6 100644
--- a/include/linux/intel_rapl.h
+++ b/include/linux/intel_rapl.h
@@ -152,7 +152,7 @@ struct rapl_if_priv {
 	union rapl_reg reg_unit;
 	union rapl_reg regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
 	int limits[RAPL_DOMAIN_MAX];
-	int (*read_raw)(int id, struct reg_action *ra);
+	int (*read_raw)(int id, struct reg_action *ra, bool atomic);
 	int (*write_raw)(int id, struct reg_action *ra);
 	void *defaults;
 	void *rpi;
-- 
2.43.0

Re: [PATCH v1 1/2] powercap: intel_rapl: Prepare read_raw interface for atomic-context callers

[Raag Jadav]

On Thu, Nov 20, 2025 at 04:05:38PM -0800, Kuppuswamy Sathyanarayanan wrote:
> The current read_raw() implementation of the TPMI, MMIO and MSR
> interfaces does not distinguish between atomic and non-atomic callers.
> 
> rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
> issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
> event handlers can invoke this function from atomic context where
> sleeping or rescheduling is not allowed. In atomic context, the caller
> is already executing on the target CPU, so a direct rdmsrq() is
> sufficient.
> 
> To support such usage, introduce an atomic flag to the read_raw()
> interface to allow callers pass the context information. Modify the
> common RAPL code to propagate this flag, and set the flag to reflect
> the calling contexts.
> 
> Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
> read with rdmsrq() when running in atomic context, and a sanity check
> to ensure target CPU matches the current CPU for such use cases.
> 
> The TPMI and MMIO implementations do not require special atomic
> handling, so the flag is ignored in those paths.
> 
> This is a preparatory patch for adding MSR-based RAPL PMU support.

...

> -static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
> +static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool atomic)
>  {
> +	/*
> +	 * When called from atomic-context (eg PMU event handler)
> +	 * perform MSR read directly using rdmsrq().
> +	 */
> +	if (atomic) {
> +		if (unlikely(smp_processor_id() != cpu))
> +			return -EIO;

This series breaks[1] our application[2] in cases where the reads are
issued from any available CPU it is scheduled on. This issue is not seen on
older platforms which use the original arch/x86 RAPL implementation.

Can someone please shed some light on the change of userspace expectations?
Or did I miss any points in the documentation?

[1] https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6935
[2] https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/lib/igt_power.c

Raag

> +		rdmsrq(ra->reg.msr, ra->value);
> +		goto out;
> +	}
> +
>  	if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) {
>  		pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu);
>  		return -EIO;
>  	}
> +
> +out:
>  	ra->value &= ra->mask;
>  	return 0;
>  }

Re: [PATCH v1 1/2] powercap: intel_rapl: Prepare read_raw interface for atomic-context callers

[Sathyanarayanan Kuppuswamy]

On 2/13/26 10:37 PM, Raag Jadav wrote:
> On Thu, Nov 20, 2025 at 04:05:38PM -0800, Kuppuswamy Sathyanarayanan wrote:
>> The current read_raw() implementation of the TPMI, MMIO and MSR
>> interfaces does not distinguish between atomic and non-atomic callers.
>>
>> rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
>> issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
>> event handlers can invoke this function from atomic context where
>> sleeping or rescheduling is not allowed. In atomic context, the caller
>> is already executing on the target CPU, so a direct rdmsrq() is
>> sufficient.
>>
>> To support such usage, introduce an atomic flag to the read_raw()
>> interface to allow callers pass the context information. Modify the
>> common RAPL code to propagate this flag, and set the flag to reflect
>> the calling contexts.
>>
>> Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
>> read with rdmsrq() when running in atomic context, and a sanity check
>> to ensure target CPU matches the current CPU for such use cases.
>>
>> The TPMI and MMIO implementations do not require special atomic
>> handling, so the flag is ignored in those paths.
>>
>> This is a preparatory patch for adding MSR-based RAPL PMU support.
> ...
>
>> -static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
>> +static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool atomic)
>>   {
>> +	/*
>> +	 * When called from atomic-context (eg PMU event handler)
>> +	 * perform MSR read directly using rdmsrq().
>> +	 */
>> +	if (atomic) {
>> +		if (unlikely(smp_processor_id() != cpu))
>> +			return -EIO;
> This series breaks[1] our application[2] in cases where the reads are
> issued from any available CPU it is scheduled on. This issue is not seen on
> older platforms which use the original arch/x86 RAPL implementation.
>
> Can someone please shed some light on the change of userspace expectations?
> Or did I miss any points in the documentation?
>
> [1] https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6935
> [2] https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/lib/igt_power.c

The access with non-lead CPUs is fixed by following series:

https://lore.kernel.org/linux-pm/CAJZ5v0gh_3y4+2qepC5Mqos+y+kBfGgeEKdmL5s6J4MBGcrQzw@mail.gmail.com/T/#mabe68b0d5c3e5571c9333ff915d38562ec7fed71

Can you please re-test with this above series?


> Raag
>
>> +		rdmsrq(ra->reg.msr, ra->value);
>> +		goto out;
>> +	}
>> +
>>   	if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) {
>>   		pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu);
>>   		return -EIO;
>>   	}
>> +
>> +out:
>>   	ra->value &= ra->mask;
>>   	return 0;
>>   }

-- 
Sathyanarayanan Kuppuswamy
Linux Kernel Developer

Re: [PATCH v1 1/2] powercap: intel_rapl: Prepare read_raw interface for atomic-context callers

[Raag Jadav]

On Sat, Feb 14, 2026 at 07:31:04AM -0800, Sathyanarayanan Kuppuswamy wrote:
> On 2/13/26 10:37 PM, Raag Jadav wrote:
> > On Thu, Nov 20, 2025 at 04:05:38PM -0800, Kuppuswamy Sathyanarayanan wrote:
> > > The current read_raw() implementation of the TPMI, MMIO and MSR
> > > interfaces does not distinguish between atomic and non-atomic callers.
> > > 
> > > rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
> > > issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
> > > event handlers can invoke this function from atomic context where
> > > sleeping or rescheduling is not allowed. In atomic context, the caller
> > > is already executing on the target CPU, so a direct rdmsrq() is
> > > sufficient.
> > > 
> > > To support such usage, introduce an atomic flag to the read_raw()
> > > interface to allow callers pass the context information. Modify the
> > > common RAPL code to propagate this flag, and set the flag to reflect
> > > the calling contexts.
> > > 
> > > Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
> > > read with rdmsrq() when running in atomic context, and a sanity check
> > > to ensure target CPU matches the current CPU for such use cases.
> > > 
> > > The TPMI and MMIO implementations do not require special atomic
> > > handling, so the flag is ignored in those paths.
> > > 
> > > This is a preparatory patch for adding MSR-based RAPL PMU support.
> > ...
> > 
> > > -static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
> > > +static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool atomic)
> > >   {
> > > +	/*
> > > +	 * When called from atomic-context (eg PMU event handler)
> > > +	 * perform MSR read directly using rdmsrq().
> > > +	 */
> > > +	if (atomic) {
> > > +		if (unlikely(smp_processor_id() != cpu))
> > > +			return -EIO;
> > This series breaks[1] our application[2] in cases where the reads are
> > issued from any available CPU it is scheduled on. This issue is not seen on
> > older platforms which use the original arch/x86 RAPL implementation.
> > 
> > Can someone please shed some light on the change of userspace expectations?
> > Or did I miss any points in the documentation?
> > 
> > [1] https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6935
> > [2] https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/lib/igt_power.c
> 
> The access with non-lead CPUs is fixed by following series:
> 
> https://lore.kernel.org/linux-pm/CAJZ5v0gh_3y4+2qepC5Mqos+y+kBfGgeEKdmL5s6J4MBGcrQzw@mail.gmail.com/T/#mabe68b0d5c3e5571c9333ff915d38562ec7fed71
> 
> Can you please re-test with this above series?

Working now, thanks for the fix :)

Raag

> > > +		rdmsrq(ra->reg.msr, ra->value);
> > > +		goto out;
> > > +	}
> > > +
> > >   	if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) {
> > >   		pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu);
> > >   		return -EIO;
> > >   	}
> > > +
> > > +out:
> > >   	ra->value &= ra->mask;
> > >   	return 0;
> > >   }
> 
> -- 
> Sathyanarayanan Kuppuswamy
> Linux Kernel Developer
> 

[PATCH v1 2/2] powercap: intel_rapl: Enable MSR-based RAPL PMU support

[Kuppuswamy Sathyanarayanan]

Currently, RAPL PMU support requires adding CPU model entries to
arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are
not architectural and require platform-specific customization, making
arch/x86 an inappropriate location for this functionality.

The powercap subsystem already handles RAPL functionality and is the
natural place to consolidate all RAPL features. The powercap RAPL
driver already includes PMU support for TPMI-based RAPL interfaces,
making it straightforward to extend this support to MSR-based RAPL
interfaces as well.

This consolidation eliminates the need to maintain RAPL support in
multiple subsystems and provides a unified approach for both TPMI and
MSR-based RAPL implementations.

The MSR-based PMU support includes the following updates:

1. Register MSR-based PMU support for the supported platforms
   and unregister it when no online CPUs remain in the package.
2. Remove existing checks that restrict RAPL PMU support to TPMI-based
   interfaces and extend the logic to allow MSR-based RAPL interfaces.
   atomic-safe MSR reads when invoked from PMU event handlers
3. Define a CPU model list to determine which processors should
   register RAPL PMU interface through the powercap driver for
   MSR-based RAPL, excluding those that support TPMI interface.
   This list prevents conflicts with existing arch/x86 PMU code
   that already registers RAPL PMU for some processors. Add
   Panther Lake & Wildcat Lake to the CPU models list.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
 drivers/powercap/intel_rapl_common.c | 12 ++++++------
 drivers/powercap/intel_rapl_msr.c    | 24 ++++++++++++++++++++++--
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 066779460bc8..03979d32aa34 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -1594,11 +1594,11 @@ static int get_pmu_cpu(struct rapl_package *rp)
 	if (!rp->has_pmu)
 		return nr_cpu_ids;
 
-	/* Only TPMI RAPL is supported for now */
-	if (rp->priv->type != RAPL_IF_TPMI)
+	/* Only TPMI & MSR RAPL are supported for now */
+	if (rp->priv->type != RAPL_IF_TPMI && rp->priv->type != RAPL_IF_MSR)
 		return nr_cpu_ids;
 
-	/* TPMI RAPL uses any CPU in the package for PMU */
+	/* TPMI/MSR RAPL uses any CPU in the package for PMU */
 	for_each_online_cpu(cpu)
 		if (topology_physical_package_id(cpu) == rp->id)
 			return cpu;
@@ -1611,11 +1611,11 @@ static bool is_rp_pmu_cpu(struct rapl_package *rp, int cpu)
 	if (!rp->has_pmu)
 		return false;
 
-	/* Only TPMI RAPL is supported for now */
-	if (rp->priv->type != RAPL_IF_TPMI)
+	/* Only TPMI & MSR RAPL are supported for now */
+	if (rp->priv->type != RAPL_IF_TPMI && rp->priv->type != RAPL_IF_MSR)
 		return false;
 
-	/* TPMI RAPL uses any CPU in the package for PMU */
+	/* TPMI/MSR RAPL uses any CPU in the package for PMU */
 	return topology_physical_package_id(cpu) == rp->id;
 }
 
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index 46b716ea45b2..15660c6ea5a7 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -33,6 +33,8 @@
 /* private data for RAPL MSR Interface */
 static struct rapl_if_priv *rapl_msr_priv;
 
+static bool rapl_msr_pmu __ro_after_init;
+
 static struct rapl_if_priv rapl_msr_priv_intel = {
 	.type = RAPL_IF_MSR,
 	.reg_unit.msr = MSR_RAPL_POWER_UNIT,
@@ -79,6 +81,8 @@ static int rapl_cpu_online(unsigned int cpu)
 		rp = rapl_add_package_cpuslocked(cpu, rapl_msr_priv, true);
 		if (IS_ERR(rp))
 			return PTR_ERR(rp);
+		if (rapl_msr_pmu)
+			rapl_package_add_pmu(rp);
 	}
 	cpumask_set_cpu(cpu, &rp->cpumask);
 	return 0;
@@ -95,10 +99,14 @@ static int rapl_cpu_down_prep(unsigned int cpu)
 
 	cpumask_clear_cpu(cpu, &rp->cpumask);
 	lead_cpu = cpumask_first(&rp->cpumask);
-	if (lead_cpu >= nr_cpu_ids)
+	if (lead_cpu >= nr_cpu_ids) {
+		if (rapl_msr_pmu)
+			rapl_package_remove_pmu(rp);
 		rapl_remove_package_cpuslocked(rp);
-	else if (rp->lead_cpu == cpu)
+	} else if (rp->lead_cpu == cpu) {
 		rp->lead_cpu = lead_cpu;
+	}
+
 	return 0;
 }
 
@@ -168,6 +176,13 @@ static const struct x86_cpu_id pl4_support_ids[] = {
 	{}
 };
 
+/* List of MSR-based RAPL PMU support CPUs */
+static const struct x86_cpu_id pmu_support_ids[] = {
+	X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
+	X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
+	{}
+};
+
 static int rapl_msr_probe(struct platform_device *pdev)
 {
 	const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
@@ -195,6 +210,11 @@ static int rapl_msr_probe(struct platform_device *pdev)
 		pr_info("PL4 support detected.\n");
 	}
 
+	if (x86_match_cpu(pmu_support_ids)) {
+		rapl_msr_pmu = true;
+		pr_info("MSR-based RAPL PMU support enabled\n");
+	}
+
 	rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
 	if (IS_ERR(rapl_msr_priv->control_type)) {
 		pr_debug("failed to register powercap control_type.\n");
-- 
2.43.0

Re: [PATCH v1 0/2] Add MSR-based RAPL PMU support

[Pandruvada, Srinivas]

On Thu, 2025-11-20 at 16:05 -0800, Kuppuswamy Sathyanarayanan wrote:
> This patch series enables MSR-based PMU support for the Intel RAPL
> driver in the Linux powercap subsystem.
> 
> Following are the patch details:
> 
> Patch 1/2 - Preparatory patch that updates the read_raw() interface
>             to allow atomic-context callers.
> 
> Patch 2/2 - More details about motivation of this series and adds
>             MSR-based RAPL PMU access support.
> 
> This series has been tested and verified in the Panther Lake and
> Wildcat Lake platforms using perf tool.
> 
> Please let me know your review comments.
> 

Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>


> Kuppuswamy Sathyanarayanan (2):
>   powercap: intel_rapl: Prepare read_raw interface for atomic-context
>     callers
>   powercap: intel_rapl: Enable MSR-based RAPL PMU support
> 
>  drivers/powercap/intel_rapl_common.c          | 36 +++++++++--------
>  drivers/powercap/intel_rapl_msr.c             | 40
> +++++++++++++++++--
>  drivers/powercap/intel_rapl_tpmi.c            |  2 +-
>  .../int340x_thermal/processor_thermal_rapl.c  |  2 +-
>  include/linux/intel_rapl.h                    |  2 +-
>  5 files changed, 59 insertions(+), 23 deletions(-)
> 

Re: [PATCH v1 0/2] Add MSR-based RAPL PMU support

[Rafael J. Wysocki]

On Fri, Nov 21, 2025 at 2:50 AM Pandruvada, Srinivas
<srinivas.pandruvada@intel.com> wrote:
>
> On Thu, 2025-11-20 at 16:05 -0800, Kuppuswamy Sathyanarayanan wrote:
> > This patch series enables MSR-based PMU support for the Intel RAPL
> > driver in the Linux powercap subsystem.
> >
> > Following are the patch details:
> >
> > Patch 1/2 - Preparatory patch that updates the read_raw() interface
> >             to allow atomic-context callers.
> >
> > Patch 2/2 - More details about motivation of this series and adds
> >             MSR-based RAPL PMU access support.
> >
> > This series has been tested and verified in the Panther Lake and
> > Wildcat Lake platforms using perf tool.
> >
> > Please let me know your review comments.
> >
>
> Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>

Both patches applied as 6.19 material, thanks!