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[83.9.30.30]) by smtp.gmail.com with ESMTPSA id z6-20020a2e9646000000b002b47a15a2eesm1743320ljh.45.2023.06.23.06.46.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 06:46:53 -0700 (PDT) Message-ID: Date: Fri, 23 Jun 2023 15:46:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes Content-Language: en-US To: Neil Armstrong , Andy Gross , Bjorn Andersson , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-0-709474b151cc@linaro.org> <20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-2-709474b151cc@linaro.org> From: Konrad Dybcio In-Reply-To: <20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-2-709474b151cc@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On 23.06.2023 14:50, Neil Armstrong wrote: > Set the proper enable_mask to nodes requiring such value > to be used instead of a bandwidth when voting. > > The masks were copied from the downstream implementation at [1]. > > [1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-05600-WAIPIOLE.0/drivers/interconnect/qcom/waipio.c > > Signed-off-by: Neil Armstrong > --- Reviewed-by: Konrad Dybcio Konrad > drivers/interconnect/qcom/sm8450.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c > index 2d7a8e7b85ec..e64c214b4020 100644 > --- a/drivers/interconnect/qcom/sm8450.c > +++ b/drivers/interconnect/qcom/sm8450.c > @@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { > > static struct qcom_icc_bcm bcm_acv = { > .name = "ACV", > + .enable_mask = 0x8, > .num_nodes = 1, > .nodes = { &ebi }, > }; > @@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = { > > static struct qcom_icc_bcm bcm_cn0 = { > .name = "CN0", > + .enable_mask = 0x1, > .keepalive = true, > .num_nodes = 55, > .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, > @@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = { > > static struct qcom_icc_bcm bcm_co0 = { > .name = "CO0", > + .enable_mask = 0x1, > .num_nodes = 2, > .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, > }; > @@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = { > > static struct qcom_icc_bcm bcm_mm1 = { > .name = "MM1", > + .enable_mask = 0x1, > .num_nodes = 12, > .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, > &qnm_camnoc_sf, &qnm_mdp, > @@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = { > > static struct qcom_icc_bcm bcm_sh1 = { > .name = "SH1", > + .enable_mask = 0x1, > .num_nodes = 7, > .nodes = { &alm_gpu_tcu, &alm_sys_tcu, > &qnm_nsp_gemnoc, &qnm_pcie, > @@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = { > > static struct qcom_icc_bcm bcm_sn1 = { > .name = "SN1", > + .enable_mask = 0x1, > .num_nodes = 4, > .nodes = { &qhm_gic, &qxm_pimem, > &xm_gic, &qns_gemnoc_gc }, > @@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = { > > static struct qcom_icc_bcm bcm_acv_disp = { > .name = "ACV", > + .enable_mask = 0x1, > .num_nodes = 1, > .nodes = { &ebi_disp }, > }; > @@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { > > static struct qcom_icc_bcm bcm_mm1_disp = { > .name = "MM1", > + .enable_mask = 0x1, > .num_nodes = 3, > .nodes = { &qnm_mdp_disp, &qnm_rot_disp, > &qns_mem_noc_sf_disp }, > @@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { > > static struct qcom_icc_bcm bcm_sh1_disp = { > .name = "SH1", > + .enable_mask = 0x1, > .num_nodes = 1, > .nodes = { &qnm_pcie_disp }, > }; >