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> }; > > - wcn6750-pmu { > + wcn6750_pmu: wcn6750-pmu { > compatible = "qcom,wcn6750-pmu"; > pinctrl-0 = <&bt_en>; > pinctrl-names = "default"; > @@ -901,7 +901,7 @@ pcie1_switch0_dsp1: pcie@1,0 { > bus-range = <0x3 0xff>; > }; > > - pcie@2,0 { > + pcie0_m2_e: pcie@2,0 { > reg = <0x21000 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > One correction for this patch: After re-checking the composed devicetree and the device enumeration, the QCC2072-facing PCIe path is behind the Industrial mezzanine PCIe0 switch: /soc@0/pcie@1c00000/pcie@0/pcie@0,0/pcie@2,0 The pcie@2,0 node labelled in qcs6490-rb3gen2.dts by this patch is under the base RB3 PCIe1 topology, so it is not the right endpoint for the BT UART variant. I will fix this in v3 once the endpoint modelling approach is clarified. Regards, Rahul