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Thu, 24 Sep 2026 23:40:05 -0700 (PDT) X-Received: by 2002:a05:701b:21c8:b0:143:5c2a:e488 with SMTP id a92af1059eb24-14503f6e17amr3456550c88.0.1790318404841; Thu, 24 Sep 2026 23:40:04 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-145adcc5b00sm3614535c88.15.2026.09.24.23.39.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Sep 2026 23:40:04 -0700 (PDT) Message-ID: Date: Fri, 25 Sep 2026 12:09:56 +0530 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible To: Krzysztof Kozlowski , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Konrad Dybcio , Dmitry Baryshkov , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org References: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> <20260921-ipq_clk_changes-v1-5-d242e3d49648@oss.qualcomm.com> <62a5fabc-3a06-42fa-9c6b-6504650e712b@kernel.org> <7bcffc7c-5dda-4ead-a053-7eb4980e43a4@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDAyNiBTYWx0ZWRfX5Xw/DHcn1jD4 XaVlbTzbfLGrTJVKwud0LHJF/IKnIQo+VrmzwLGQhQG3scDFcwbwKVbj6dgWKsomRJnvx3tk0Ry PzDNHw4sZXQMC6FO55qZncLXHh606hLvkt6a5K/29J6zO7O4fmhIOohLRK544OrzUNMtBTTE6gQ pFNd/sfX5/Mq2IfPCoVBArHta84gwW82x9IcC8BLsqtbZjfHJdaT5QLpUFkxPaGxQ/2rJ8QrEue YEEoUIdPP/B7XlM40PseJ1H3bzt1PHoz6fPjl8/uOdoTl2sTeNWfsElfLOWqxpMf3qyGYHwjEpg xAUxP5TRLqCIhYV2gdwD5bbuhEW1H6WtazvXgm++Z8gjKMGwlQB5vtriPn1W/ZKJQfatlO5TVLT 1EEnSI9XgUY8agpc3l8ydx9Rfale6L4Z1vsrhiMzk4B+kOkCsKo4TPisQt62NftHyee9OMh2RmS 0bNABFpjdl+lJBgeMdg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDAyNiBTYWx0ZWRfX5vr5s5umGvZh //Y/0mrlWBG202KtzZ3Hp9Ofl8fsCrDdexSXJBCO+FrSSt7CHZOWIAAVmnqdvS7fF0ido2LqUW6 sWo2X2Ij2BSAanT/MI6OMQ7VV/ROcvc= X-Proofpoint-GUID: RKooz63m_BgcfK2gbttZVgBWfGD7McBK X-Proofpoint-ORIG-GUID: RKooz63m_BgcfK2gbttZVgBWfGD7McBK X-Authority-Analysis: v=2.4 cv=EJWTQFZC c=1 sm=1 tr=0 ts=6ab61746 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=iYr-Yv8LbTbqzJeusKwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250026 On 9/24/2026 4:28 PM, Krzysztof Kozlowski wrote: > On 24/09/2026 11:15, Kathiravan Thirumoorthy wrote: >> On 9/23/2026 2:17 PM, Krzysztof Kozlowski wrote: >>> On 21/09/2026 08:19, Kathiravan Thirumoorthy wrote: >>>> The IPQ5332 and IPQ5424 GCC blocks use different clock input orderings. >>>> Document the clock inputs in compatible-specific schema constraints instead >>>> of using a common clock description. >>>> >>>> Also add the 375 MHz PPE clock generated by the CMN PLL to the IPQ5424 >>>> clock input list. >>>> >>>> This keeps the binding aligned with the clock ordering used by the >>>> existing DTS and GCC driver implementations. >>>> >>>> Signed-off-by: Kathiravan Thirumoorthy >>>> --- >>>> .../bindings/clock/qcom,ipq5332-gcc.yaml | 26 +++++++++++++--------- >>>> 1 file changed, 16 insertions(+), 10 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>> index 1230183fc0a9..fb39dffca988 100644 >>>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >>>> @@ -25,14 +25,7 @@ properties: >>>> >>>> clocks: >>>> minItems: 5 >>>> - items: >>>> - - description: Board XO clock source >>>> - - description: Sleep clock source >>>> - - description: PCIE 2lane PHY pipe clock source >>>> - - description: PCIE 2lane x1 PHY pipe clock source (For second lane) >>>> - - description: USB PCIE wrapper pipe clock source >>>> - - description: PCIE 2-lane PHY2 pipe clock source >>>> - - description: PCIE 2-lane PHY3 pipe clock source >>> You are changing the order which is ABI break. Describe the actual >>> problem to justify such change. Are you saying this was broken since >>> beginning or what exactly is not working here? The driver was added by >>> Qualcomm in 2024, so how did it even work? It's not some 10 yo legacy >>> where we did some mistakes in binding while converting from TXT. >>> >>> Also, I do not get why the list cannot be shared. >> When the bindings was posted, list is combined for both IPQ5332 and >> IPQ5424. But the driver wasn't updated and it was following the below >> order, so was DTS, which is not compatible the DT binding description. >> >> enum { >>         DT_XO, >>         DT_SLEEP_CLK, >>         DT_PCIE30_PHY0_PIPE_CLK, >>         DT_PCIE30_PHY1_PIPE_CLK, >>         DT_PCIE30_PHY2_PIPE_CLK, >>         DT_PCIE30_PHY3_PIPE_CLK, >>         DT_USB_PCIE_WRAPPER_PIPE_CLK, >>         DT_CMN_PLL_NSS_375M_CLK, >> }; >> >> So I'm splitting the description between IPQ5332 and IPQ5424 to matching >> with the DTS and the driver description. > So we asked back in 2024 to have the common part of the list. I even did > the effort to dig it: > > https://lore.kernel.org/all/ruti7hmkxkayzmqfbme6rw6j2vbhlx4ul4ptcckwamcpd4cyfx@owufhxwpvlcj/ > > Authors implemented it partially, broken drivers. Now you basically > revert what we asked, which is BTW logical option. It's logical and > reasonable, but leaves bitter feeling. > > I have feeling there is no accountability and no responsibility of the > IPQ at all. > > No, that's not going to work. You cannot come 1.5 year later and revert > what reviewer asked you, even if issue was just by mistake in the first > place. And you should not even try to do that. I understand the concern, and I agree this should have been caught much earlier. I only discovered the mismatch while working on the IPQ5424 clock additions. My intent here is resolve the inconsistency that currently exists between the binding and implementation. > > NAK I'm happy to explore an alternative approach if updating the binding is not considered acceptable. > > Best regards, > Krzysztof