From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8377C0650F for ; Sun, 11 Aug 2019 19:16:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8352E20820 for ; Sun, 11 Aug 2019 19:16:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="K6ERdW8y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726502AbfHKTQx (ORCPT ); Sun, 11 Aug 2019 15:16:53 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14883 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726014AbfHKTQx (ORCPT ); Sun, 11 Aug 2019 15:16:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 11 Aug 2019 12:16:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 11 Aug 2019 12:16:52 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 11 Aug 2019 12:16:52 -0700 Received: from [10.2.167.88] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 11 Aug 2019 19:16:50 +0000 Subject: Re: [PATCH v8 13/21] clk: tegra210: Use fence_udelay during PLLU init To: Dmitry Osipenko , , , , , , , , CC: , , , , , , , , , , , , , , , , References: <1565308020-31952-1-git-send-email-skomatineni@nvidia.com> <1565308020-31952-14-git-send-email-skomatineni@nvidia.com> <1d09a2c5-4973-340f-fdfc-d4e665c8b55d@gmail.com> From: Sowjanya Komatineni Message-ID: Date: Sun, 11 Aug 2019 12:16:49 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <1d09a2c5-4973-340f-fdfc-d4e665c8b55d@gmail.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565551014; bh=B6ddjnEKl0ua+Tada6d8Tb7SUSLehPfPuF8MM3YYMj8=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=K6ERdW8yThtfsPaINCIqakd5gFwkxjyduawu95MVejzx32Fq0TqO1jaMsLabDvmE5 /DFiAeD/BMuLmfdN3gkXnnb1GTiQ32zkFxz8IiH3pP6C6ORCCdE4/Bl5BGtZKn07hj U4kFIXRuMra4yyN3wXhdMtXeNfFVCBIgcc/YKPqAy3I57uYbrOVBVwDUXNFBfoW1Jv jDRLNih5SeR2PIhu0BznbHvZRZcF69Cm0yhf0za2gRcFZJKgOBz6JxJGgC9MqWqUum Bd63yHkGj5tyui/8MEMsf79d8GtFQCboBZQCglK65t40mmcM++wpwhVvbDfOmT69j5 xtlCDuflo1isA== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On 8/11/19 11:02 AM, Dmitry Osipenko wrote: > 09.08.2019 2:46, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> This patch uses fence_udelay rather than udelay during PLLU >> initialization to ensure writes to clock registers happens before >> waiting for specified delay. >> >> Acked-by: Thierry Reding >> Signed-off-by: Sowjanya Komatineni >> --- >> drivers/clk/tegra/clk-tegra210.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-te= gra210.c >> index 4721ee030d1c..998bf60b219a 100644 >> --- a/drivers/clk/tegra/clk-tegra210.c >> +++ b/drivers/clk/tegra/clk-tegra210.c >> @@ -2841,7 +2841,7 @@ static int tegra210_enable_pllu(void) >> reg =3D readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); >> reg &=3D ~BIT(pllu.params->iddq_bit_idx); >> writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); >> - udelay(5); >> + fence_udelay(5, clk_base); >> =20 >> reg =3D readl_relaxed(clk_base + PLLU_BASE); >> reg &=3D ~GENMASK(20, 0); >> @@ -2849,7 +2849,7 @@ static int tegra210_enable_pllu(void) >> reg |=3D fentry->n << 8; >> reg |=3D fentry->p << 16; >> writel(reg, clk_base + PLLU_BASE); >> - udelay(1); >> + fence_udelay(1, clk_base); >> reg |=3D PLL_ENABLE; >> writel(reg, clk_base + PLLU_BASE); >> =20 >> @@ -2895,12 +2895,12 @@ static int tegra210_init_pllu(void) >> reg =3D readl_relaxed(clk_base + XUSB_PLL_CFG0); >> reg &=3D ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; >> writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); >> - udelay(1); >> + fence_udelay(1, clk_base); >> =20 >> reg =3D readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); >> reg |=3D PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; >> writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); >> - udelay(1); >> + fence_udelay(1, clk_base); >> =20 >> reg =3D readl_relaxed(clk_base + PLLU_BASE); >> reg &=3D ~PLLU_BASE_CLKENABLE_USB; >> > The clk_base corresponds to the RESET controller's part of Clock-and-Rese= t hardware, is it > okay to read-back the RST register and not the clock for the fencing? Yes as both reset and clocks are all in same CAR