From: Bjorn Andersson <andersson@kernel.org>
To: Richard Acayan <mailingradian@gmail.com>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Amit Kucheria <amitk@kernel.org>,
Thara Gopinath <thara.gopinath@gmail.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Zhang Rui <rui.zhang@intel.com>,
Lukasz Luba <lukasz.luba@arm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: Re: [PATCH v5 1/2] thermal/qcom/lmh: support SDM670 and its CPU clusters
Date: Mon, 6 Jul 2026 19:23:20 -0500 [thread overview]
Message-ID: <akxG4bzq7qAprz0M@baldur> (raw)
In-Reply-To: <20260330165237.101045-2-mailingradian@gmail.com>
On Mon, Mar 30, 2026 at 12:52:36PM -0400, Richard Acayan wrote:
> The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but
> some SoCs divide the CPUs into different sizes of clusters. In SDM670,
> the first 6 CPUs are in the little cluster and the next 2 are in the big
> cluster. Define the clusters in the match data and define the different
> cluster configuration for SDM670.
>
> Currently, this tolerates linking to any CPU in a given cluster.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> drivers/thermal/qcom/lmh.c | 54 ++++++++++++++++++++++++--------------
> 1 file changed, 34 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
> index 3d072b7a4a6d..81ab2f0be9c8 100644
> --- a/drivers/thermal/qcom/lmh.c
> +++ b/drivers/thermal/qcom/lmh.c
> @@ -30,14 +30,17 @@
>
> #define LMH_REG_DCVS_INTR_CLR 0x8
>
> -#define LMH_ENABLE_ALGOS 1
> -
> struct lmh_hw_data {
> void __iomem *base;
> struct irq_domain *domain;
> int irq;
> };
>
> +struct lmh_soc_data {
> + bool enable_algos;
> + unsigned int clus1_start_idx;
> +};
> +
> static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
> {
> struct lmh_hw_data *lmh_data = data;
> @@ -100,8 +103,8 @@ static int lmh_probe(struct platform_device *pdev)
> struct device_node *np = dev->of_node;
> struct device_node *cpu_node;
> struct lmh_hw_data *lmh_data;
> + const struct lmh_soc_data *match_data;
> int temp_low, temp_high, temp_arm, cpu_id, ret;
> - unsigned int enable_alg;
> u32 node_id;
>
> if (!qcom_scm_is_available())
> @@ -121,6 +124,11 @@ static int lmh_probe(struct platform_device *pdev)
> cpu_id = of_cpu_node_to_id(cpu_node);
> of_node_put(cpu_node);
>
> + if (cpu_id < 0) {
> + dev_err(dev, "Wrong CPU id associated with LMh node\n");
> + return -EINVAL;
> + }
> +
> ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
> if (ret) {
> dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
> @@ -139,26 +147,16 @@ static int lmh_probe(struct platform_device *pdev)
> return ret;
> }
>
> - /*
> - * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
> - * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
> - * of a dt match table.
> - */
> - if (cpu_id == 0) {
> + match_data = of_device_get_match_data(dev);
> + if (cpu_id < match_data->clus1_start_idx)
> node_id = LMH_CLUSTER0_NODE_ID;
> - } else if (cpu_id == 4) {
> + else
> node_id = LMH_CLUSTER1_NODE_ID;
> - } else {
> - dev_err(dev, "Wrong CPU id associated with LMh node\n");
> - return -EINVAL;
> - }
>
> if (!qcom_scm_lmh_dcvsh_available())
> return -EINVAL;
>
> - enable_alg = (uintptr_t)of_device_get_match_data(dev);
> -
> - if (enable_alg) {
> + if (match_data->enable_algos) {
> ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
> LMH_NODE_DCVS, node_id, 0);
> if (ret)
> @@ -231,10 +229,26 @@ static int lmh_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct lmh_soc_data sdm670_lmh_data = {
> + .enable_algos = true,
> + .clus1_start_idx = 6,
> +};
> +
> +static const struct lmh_soc_data sdm845_lmh_data = {
> + .enable_algos = true,
> + .clus1_start_idx = 4,
> +};
> +
> +static const struct lmh_soc_data sm8150_lmh_data = {
> + .enable_algos = false,
> + .clus1_start_idx = 4,
> +};
> +
> static const struct of_device_id lmh_table[] = {
> - { .compatible = "qcom,sc8180x-lmh", },
> - { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
> - { .compatible = "qcom,sm8150-lmh", },
> + { .compatible = "qcom,sc8180x-lmh", .data = &sm8150_lmh_data },
> + { .compatible = "qcom,sdm670-lmh", .data = &sdm670_lmh_data },
> + { .compatible = "qcom,sdm845-lmh", .data = &sdm845_lmh_data },
> + { .compatible = "qcom,sm8150-lmh", .data = &sm8150_lmh_data },
> {}
> };
> MODULE_DEVICE_TABLE(of, lmh_table);
> --
> 2.53.0
>
next prev parent reply other threads:[~2026-07-07 0:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-30 16:52 [PATCH v5 0/2] SDM670 Basic SoC thermal zones Richard Acayan
2026-03-30 16:52 ` [PATCH v5 1/2] thermal/qcom/lmh: support SDM670 and its CPU clusters Richard Acayan
2026-03-30 18:43 ` Dmitry Baryshkov
2026-03-31 8:30 ` Konrad Dybcio
2026-03-31 17:44 ` Richard Acayan
2026-04-01 8:30 ` Konrad Dybcio
2026-07-07 0:23 ` Bjorn Andersson [this message]
2026-03-30 16:52 ` [PATCH v5 2/2] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Richard Acayan
2026-03-30 18:44 ` Dmitry Baryshkov
2026-03-31 8:36 ` Konrad Dybcio
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