Linux Power Management development
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From: Thomas Gleixner <tglx@linutronix.de>
To: "dbasehore ." <dbasehore@chromium.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>,
	x86@kernel.org,
	Platform Driver <platform-driver-x86@vger.kernel.org>,
	"Rafael J . Wysocki" <rjw@rjwysocki.net>,
	Len Brown <len.brown@intel.com>,
	Linux-pm mailing list <linux-pm@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH v5 5/5] intel_idle: Add S0ix validation
Date: Thu, 13 Jul 2017 07:11:22 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1707130655200.2332@nanos> (raw)
In-Reply-To: <CAGAzgsqZvfR9WtYDq5yaSDiKK8LSivE5uOTsUorVtWxfy18SEA@mail.gmail.com>

On Wed, 12 Jul 2017, dbasehore . wrote:
> On Wed, Jul 12, 2017 at 3:16 PM, Thomas Gleixner <tglx@linutronix.de> wrote:
> > There are more issues with this: If there is a hrtimer scheduled on that
> > last CPU which enters the idle freeze state and that timer is 10 minutes
> > away, then the check timer can't be programmed and the system will happily
> > stay for 10 minutes in some shallow C state without notice. Not really
> > useful.
> 
> Are hrtimers not suspended after timekeeping_suspend is called?

They are. As I said I forgot about the inner workings and that check for
state != shutdown confused me even more, as it just looked like this might
be a valid state.

> > You know upfront whether the i915 power wells (or whatever other machinery)
> > is not powered off to allow the system to enter a specific power state. If
> > you think hard enough about creating infrastructure which allows you to
> > register power related facilities and then check them in that idle freeze
> > enter state, then you get immediate information WHY this happens and not
> > just the by chance notification about the fact that it happened.
> 
> It's not always something that can be checked by software. There was
> one case where an ordering for powering down audio hardware prevented
> proper PC10 entry, but there didn't seem to be any way to check that.
> Hardware watchdogs also have the same lack of clarity, but most if not
> all desktop and mobile processors ship with one. Overall, this seems
> to be the best that can be done at this point in freeze, and we can't
> really rely on every part of the system properly validating it's state
> in its suspend operation.

So if I understand correctly, this is the last resort of catching problems
which can't be detected upfront or are caused by a software bug.

I'm fine with that, but please explain and document it proper. The current
explanation is confusing at best.

Thanks,

	tglx

  reply	other threads:[~2017-07-13  5:11 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-08  0:02 [PATCH v5 1/5] x86: stub out pmc function Derek Basehore
2017-07-08  0:03 ` [PATCH v5 2/5] tick: Add freeze timer events Derek Basehore
2017-07-08 16:05   ` Andy Shevchenko
2017-07-10 21:11     ` dbasehore .
2017-07-10 12:53   ` Rafael J. Wysocki
2017-07-12 21:25   ` Thomas Gleixner
2017-07-13  1:18     ` dbasehore .
2017-07-13  4:54       ` Thomas Gleixner
2017-07-13  7:32   ` Peter Zijlstra
2017-07-13 15:09     ` Rafael J. Wysocki
2017-07-13 22:58       ` dbasehore .
2017-07-15 12:39         ` Rafael J. Wysocki
2017-07-18  0:30           ` dbasehore .
2017-07-18  1:33             ` Rafael J. Wysocki
2017-07-18  3:52               ` dbasehore .
2017-07-18  6:40                 ` Thomas Gleixner
2017-07-18 20:09                   ` dbasehore .
2017-07-18 21:53                     ` Thomas Gleixner
2017-07-18 22:03                       ` dbasehore .
2017-07-18 22:22                         ` Thomas Gleixner
2017-07-18 22:37                           ` dbasehore .
2017-07-18 22:39                             ` Thomas Gleixner
2017-07-08  0:03 ` [PATCH v5 3/5] x86, apic: Add freeze event support Derek Basehore
2017-07-13  5:13   ` Thomas Gleixner
2017-07-08  0:03 ` [PATCH v5 4/5] freeze: Add error reporting Derek Basehore
2017-07-08  0:03 ` [PATCH v5 5/5] intel_idle: Add S0ix validation Derek Basehore
2017-07-09  7:13   ` kbuild test robot
2017-07-10 13:33   ` Rafael J. Wysocki
2017-07-10 21:57     ` dbasehore .
2017-07-10 22:09       ` Rafael J. Wysocki
2017-07-10 22:24         ` dbasehore .
2017-07-11 14:57           ` Rafael J. Wysocki
2017-07-11 15:43             ` Len Brown
2017-07-12 22:16   ` Thomas Gleixner
2017-07-12 23:14     ` dbasehore .
2017-07-13  5:11       ` Thomas Gleixner [this message]
2017-07-13 22:49         ` dbasehore .
2017-07-13  1:06     ` dbasehore .
2017-07-08 16:00 ` [PATCH v5 1/5] x86: stub out pmc function Andy Shevchenko

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