From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44A5D1A072A; Mon, 28 Apr 2025 18:43:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745865828; cv=none; b=JcHKApxjcu8yhYqu4mgLkYZznQbRwFxzb6BIZZax68jLB73Axxv4dtjY9TFaKkWjwQZoNcR2fzSJS6TUNxZVUBW0cyU6cRZJXmH/xc4KRbJihzOqgTvSqXWj4bEs1pA6w8ixP09rNf9nL5mp5n07RK7SKF5184xT/vJZ8aCx+Yk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745865828; c=relaxed/simple; bh=roBx4174EPVNwqb/2muJ+YfV1TCurFebANGCAVMu5pg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=CKLb8dJrlVa/aTLJTZWjlAX/2PuwULbC7RRJoSUU4NbMJRw6aAznYikP/ST83np0TGq7fR/ZyIlORKkhcb4SwmCqRK+gDywrZvP5reGOpxe/yP0IeLhvWGH80usJfZMG5Oe9YPC+FJIyMvJJC467U0RtcVYskVQjMGZFCyF6/aQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mJjtSrK/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mJjtSrK/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83518C4CEE4; Mon, 28 Apr 2025 18:43:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745865825; bh=roBx4174EPVNwqb/2muJ+YfV1TCurFebANGCAVMu5pg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=mJjtSrK/fy0kRj//K3SWS51EEUW+Au2yU6I3MdDlEZMhN2K6YHpoUn9Aeles/poUA lKdXgguwk8ylYI4WICR4Eo07aKHnfmTRETcVe92cxbijAcmIr1hq5FgzXk9BMAtnZQ Emlu2rNA9lmdm1nbwL39hsnVN/RadZnnhYKc5af4eSeRLZ2KvEaaLA2a1E7tDK04KY MVCz6jrplDtGJ3+H7P+3qQCW1KjmmE2KZtVMOguJViu7FwqH+DGg8gn2AKyq8d+Y86 nDwMOneQN+41BJ6ugHZWu5KVexTQzvwRK6kO/4/l/+3WLKbNbgZebt8RjoqwAsztEw 4XaH8+c029klw== Message-ID: Date: Mon, 28 Apr 2025 13:43:42 -0500 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation To: Konrad Rzeszutek Wilk Cc: Hans de Goede , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , "open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER" , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:DOCUMENTATION" , "open list:AMD PSTATE DRIVER" , Bagas Sanjaya References: <20250423014631.3224338-1-superm1@kernel.org> <20250423014631.3224338-2-superm1@kernel.org> Content-Language: en-US From: Mario Limonciello In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/28/2025 1:39 PM, Konrad Rzeszutek Wilk wrote: > ..snip.. >> +Implementation details for Linux >> +-------------------------------- >> + >> +The implementation of threads scheduling consists of the following steps: >> + >> +1. A thread is spawned and scheduled to the ideal core using the default >> + heterogeneous scheduling policy. >> +2. The processor profiles thread execution and assigns an enumerated >> + classification ID. >> + This classification is communicated to the OS via logical processor >> + scope MSR. >> +3. During the thread context switch out the operating system consumes the >> + workload(WL) classification which resides in a logical processor scope MSR. >> +4. The OS triggers the hardware to clear its history by writing to an MSR, >> + after consuming the WL classification and before switching in the new thread. >> +5. If due to the classification, ranking table, and processor availability, >> + the thread is not on its ideal processor, the OS will then consider >> + scheduling the thread on its ideal processor (if available). > > Can you expand on 5) please? The one patch in this patchset that > touches the process file just does an WRMSR. Hi, thanks for looking. This scheduler change is not first part of the series and is going to be a follow up series. I left it in the documentation as it explains the intended implementation.