Re: [PATCH v3 7/8] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node

[Matt Coster <Matt.Coster@imgtec.com>]

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On 05/06/2025 10:57, Ulf Hansson wrote:
> On Wed, 4 Jun 2025 at 18:48, Matt Coster <Matt.Coster@imgtec.com> wrote:
>>
>> On 03/06/2025 13:27, Ulf Hansson wrote:
>>> On Fri, 30 May 2025 at 00:24, Michal Wilczynski
>>> <m.wilczynski@samsung.com> wrote:
>>>>
>>>> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
>>>> TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
>>>> the GPU using the drm/imagination driver.
>>>>
>>>> By adding this node, the kernel can recognize and initialize the GPU,
>>>> providing graphics acceleration capabilities on the Lichee Pi 4A and
>>>> other boards based on the TH1520 SoC.
>>>>
>>>> Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
>>>> controlled programatically.
>>>>
>>>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
>>>> ---
>>>>  arch/riscv/boot/dts/thead/th1520.dtsi | 22 ++++++++++++++++++++++
>>>>  1 file changed, 22 insertions(+)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> index 6170eec79e919b606a2046ac8f52db07e47ef441..ee937bbdb7c08439a70306f035b1cc82ddb4bae2 100644
>>>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 {
>>>>                 #clock-cells = <0>;
>>>>         };
>>>>
>>>> +       gpu_mem_clk: mem-clk {
>>>> +               compatible = "fixed-clock";
>>>> +               clock-frequency = <0>;
>>>> +               clock-output-names = "gpu_mem_clk";
>>>> +               #clock-cells = <0>;
>>>> +       };
>>>> +
>>>>         stmmac_axi_config: stmmac-axi-config {
>>>>                 snps,wr_osr_lmt = <15>;
>>>>                 snps,rd_osr_lmt = <15>;
>>>> @@ -504,6 +511,21 @@ clk: clock-controller@ffef010000 {
>>>>                         #clock-cells = <1>;
>>>>                 };
>>>>
>>>> +               gpu: gpu@ffef400000 {
>>>> +                       compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
>>>> +                                    "img,img-rogue";
>>>> +                       reg = <0xff 0xef400000 0x0 0x100000>;
>>>> +                       interrupt-parent = <&plic>;
>>>> +                       interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                       clocks = <&clk_vo CLK_GPU_CORE>,
>>>> +                                <&gpu_mem_clk>,
>>>> +                                <&clk_vo CLK_GPU_CFG_ACLK>;
>>>> +                       clock-names = "core", "mem", "sys";
>>>> +                       power-domains = <&aon TH1520_GPU_PD>;
>>>> +                       power-domain-names = "a";
>>>
>>> If the power-domain-names are really needed, please pick a
>>> useful/descriptive name.
>>
>> This isn't the first time our unfortunate power domain names have come
>> up [1][2]. Sadly, we're stuck with them for Rogue.
> 
> Wow, that's really crazy.
> 
> BTW, are there any reasons why you can't rely on attaching them by
> index instead, via dev_pm_domain_attach_by_id() for example? Thus
> entirely drop the names in the DT docs?
> 
> It sounds like the names don't really have a meaning, or do they?

These ABC names don't have a special meaning, indices would work just
fine here. I was thinking ahead towards our current-gen Volcanic
architecture when I added power-domain-names to the schema, since that
does have actual useful names and I wanted to keep the two as close as
possible. Plus it's nice for them to line up with the docs.

> 
>>
>> Matt
>>
>> [1]: https://lore.kernel.org/r/ff4e96e4-ebc2-4c50-9715-82ba3d7b8612@imgtec.com/ 
>> [2]: https://lore.kernel.org/r/cc6a19b3-ba35-465c-9fa6-a764df7c01c1@imgtec.com/ 
>>
>>>
> 
> [...]
> 
> Kind regards
> Uffe


-- 
Matt Coster
E: matt.coster@imgtec.com

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