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[77.231.59.95]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43617e3a486sm8256763f8f.16.2026.02.04.09.46.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Feb 2026 09:46:05 -0800 (PST) Message-ID: Date: Wed, 4 Feb 2026 18:46:03 +0100 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 To: "irving.ch.lin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Matthias Brugger , AngeloGioacchino Del Regno Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Qiqi Wang , sirius.wang@mediatek.com, vince-wl.liu@mediatek.com, jh.hsu@mediatek.com References: <20260202064820.347550-1-irving-ch.lin@mediatek.com> <20260202064820.347550-3-irving-ch.lin@mediatek.com> Content-Language: en-US, ca-ES, es-ES From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 02/02/2026 07:48, irving.ch.lin wrote: > From: Irving-CH Lin > > In MT8189 mminfra power domain, the bus protect policy separates > into two parts, one is set before subsys clocks enabled, and another > need to enable after subsys clocks enable. > > Signed-off-by: Irving-CH Lin Reviewed-by: Matthias Brugger > --- > drivers/pmdomain/mediatek/mtk-pm-domains.c | 31 ++++++++++++++++++---- > drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 ++++ > 2 files changed, 31 insertions(+), 5 deletions(-) > > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c > index 0f0662676c07..3eeb0dabf7d7 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c > @@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd, > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > } > > -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > +static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags) > { > for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { > const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; > @@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > if (!bpd->bus_prot_set_clr_mask) > break; > > + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != > + (flags & BUS_PROT_IGNORE_SUBCLK)) > + continue; > + > if (bpd->flags & BUS_PROT_INVERTED) > ret = scpsys_bus_protect_clear(pd, bpd); > else > @@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > return 0; > } > > -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) > +static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags) > { > for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { > const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; > @@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) > if (!bpd->bus_prot_set_clr_mask) > continue; > > + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != > + (flags & BUS_PROT_IGNORE_SUBCLK)) > + continue; > + > if (bpd->flags & BUS_PROT_INVERTED) > ret = scpsys_bus_protect_set(pd, bpd); > else > @@ -632,6 +640,15 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > if (ret) > goto err_pwr_ack; > > + /* > + * In MT8189 mminfra power domain, the bus protect policy separates > + * into two parts, one is set before subsys clocks enabled, and another > + * need to enable after subsys clocks enable. > + */ > + ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK); > + if (ret < 0) > + goto err_pwr_ack; > + > /* > * In few Mediatek platforms(e.g. MT6779), the bus protect policy is > * stricter, which leads to bus protect release must be prior to bus > @@ -648,7 +665,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > if (ret < 0) > goto err_disable_subsys_clks; > > - ret = scpsys_bus_protect_disable(pd); > + ret = scpsys_bus_protect_disable(pd, 0); > if (ret < 0) > goto err_disable_sram; > > @@ -662,7 +679,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > return 0; > > err_enable_bus_protect: > - scpsys_bus_protect_enable(pd); > + scpsys_bus_protect_enable(pd, 0); > err_disable_sram: > scpsys_sram_disable(pd); > err_disable_subsys_clks: > @@ -683,7 +700,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > bool tmp; > int ret; > > - ret = scpsys_bus_protect_enable(pd); > + ret = scpsys_bus_protect_enable(pd, 0); > if (ret < 0) > return ret; > > @@ -697,6 +714,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > > clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); > > + ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK); > + if (ret < 0) > + return ret; > + > if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) > scpsys_modem_pwrseq_off(pd); > else > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h > index f608e6ec4744..a5dca24cbc2f 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h > @@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags { > BUS_PROT_REG_UPDATE = BIT(1), > BUS_PROT_IGNORE_CLR_ACK = BIT(2), > BUS_PROT_INVERTED = BIT(3), > + BUS_PROT_IGNORE_SUBCLK = BIT(4), > }; > > enum scpsys_bus_prot_block { > @@ -95,6 +96,10 @@ enum scpsys_bus_prot_block { > _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ > BUS_PROT_REG_UPDATE) > > +#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \ > + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ > + BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK) > + > #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ > BUS_PROT_UPDATE(INFRA, _mask, \ > INFRA_TOPAXI_PROTECTEN, \