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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1783597989; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cfmRBwpMkOAL1gdqiVsz8y3IJffq2RYA84kWTiYDvV8=; b=DOOtB6P8+pOLeA4ezin/VGU3dZ/2eAbqKz0Rm/2pZxSeukm/lorAVbfc68T7EQvZan9PiD 8eDFhl+etBS6dr/LrnEEjo69DVUUmoEZdX6SNeqf7K8Yik2bmxPr6YxfW1L4h/x1+bUXtX HDRgOmafzDfBZi7gbMAg+aF6QCjVj3cToFLLZc6/wiSkBpOdRxbSdL0ifwWbAALBQ9K8n2 m8WXdXok25uC1/CO2Nr9s8IKLPOE/DMZ0BW5IGjBGxFxCoa4eJAsNW6JSlYqYxCxlkKFzd 5/JZvXB/pBcgJB5UB4iLO4yCnSkyoBGVuoGytn9nOlj3P5EhqR9q45BejKkYIQ== Date: Thu, 9 Jul 2026 13:24:00 +0200 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 6/6] arm64: dts: renesas: r8a78000: Add MDLC nodes To: Geert Uytterhoeven Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Ulf Hansson , Philipp Zabel , Wolfram Sang , Marek Vasut , Kuninori Morimoto , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <59725f93-5269-4b0e-8633-48821219877f@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-META: 3um84g88ek55xnbu4c56jy8ahwccrd9w X-MBO-RS-ID: 50f867c705c83dacbe1 X-Rspamd-Queue-Id: 4gwtdM40ZMzKw0Q On 7/9/26 12:24 PM, Geert Uytterhoeven wrote: Hello Geert, >>> + mdlc_ddr7: system-controller@e8380000 { >>> + compatible = "renesas,r8a78000-mdlc"; >>> + reg = <0 0xe8380000 0 0x1000>; >>> + #power-domain-cells = <2>; >>> + #reset-cells = <1>; >>> + bootph-all; >>> + }; >>> + >>> + mdlc_hscn: system-controller@c9c90000 { >>> + compatible = "renesas,r8a78000-mdlc"; >>> + reg = <0 0xc9c90000 0 0x1000>; >>> + #power-domain-cells = <2>; >>> + #reset-cells = <1>; >>> + bootph-all; >>> + }; >>> + >>> + mdlc_rt: system-controller@19440000 { >> >> Please keep the list sorted (0x19440000 should be before 0xc9c90000). > > These are sorted by instance (Module Number), as per Table 18.1 > ("Target Module hierarchy of Module Power Gating and Module Standby") > in the documentation. This order is indeed a bit odd, as it differs > from both alphabetical label order (unlike e.g. hscifN), and numerical > unit address order... > > Any guidance? Do you think those MDLC instances might be on different sub-busses and we might need to model those busses using simple-bus in DT ?