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Wed, 09 Sep 2026 04:57:46 -0700 (PDT) X-Received: by 2002:a05:620a:9c4:b0:939:9205:4d78 with SMTP id af79cd13be357-93992054effmr1798961285a.3.1788955061188; Wed, 09 Sep 2026 04:57:41 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a94f2e167fsm1614641a12.26.2026.09.09.04.57.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Sep 2026 04:57:40 -0700 (PDT) Message-ID: Date: Wed, 9 Sep 2026 13:57:35 +0200 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/7] arm64: dts: qcom: glymur: Add ADC support for Glymur CRD To: Jishnu Prakash , Jonathan Cameron , David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> <20260731-pmic5_gen4_adc-v1-6-9c49b2eea6f9@oss.qualcomm.com> <52c023c0-a61f-4116-851f-ed19de4d23f2@oss.qualcomm.com> <695dfc01-2c1f-4503-9049-2ae266774ed2@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <695dfc01-2c1f-4503-9049-2ae266774ed2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDEzMiBTYWx0ZWRfX71/EHa4xF1Tj hTgy6DgmQ8Ho2B8jw98E86FlS9U0mUu8yWBJ10Q/rJ7aCvMF1NplJG+IEluC64s1RaO8Z6xiUe9 FKLOv1p2KCQidCEdMwHsz7gnk/jF2Z4= X-Authority-Analysis: v=2.4 cv=J52aKgnS c=1 sm=1 tr=0 ts=6aa149c0 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=CY4bWrPPlyhwilDFwNAA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: 1FhgC2WbF0-bZHl12iYYBvwlPXFTKTpY X-Proofpoint-GUID: 1FhgC2WbF0-bZHl12iYYBvwlPXFTKTpY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDEzMiBTYWx0ZWRfX487evFWeH+MF Jkn3r6OBdn4yddCDF+4wHpbrF8DK8hrdBj0ZG6NcXgfp1Jr4eez+yum+Gb5yfR/OTVlbvEdRR2s xqd9IvMsph8G1zOGThGv42tYP8DB7PJRjr3cZ7NlOyMonjmZ0HfWtl/pJ6eaJ/rxF7NY2q49Ys3 4MnEoKRmHmt8bcmR2pz0uUEeRfwKmR7aONryIJbsN9GyhYzpb8ToAzcw/8jOGd6xUVX5+vwhxAP ZFxlfIB8fchgj44sb/CbHttCRqncslngrQPAemnwOdfldqhMvNPRuqVEDHqMnpRLFbHokQkB4F3 39/1puDll50loGX03W/S/ayMbt4Em4smNihrqCrUOvxE4ki8q4Twuo4n4tSV1uWV3xsXvUml8Ur MdHUBOnMviLawS9YgLfWmVoBlAWJHH4z4y5UQ8RRC6H5QLt+lEgYk7/15v0kkKwJT6bnI+OOaqi rCZ+XQWAiYB7PsYNThQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090132 On 9/9/26 12:39 PM, Jishnu Prakash wrote: > Hi Konrad, > > On 9/3/2026 2:19 PM, Konrad Dybcio wrote: >> On 7/31/26 8:06 PM, Jishnu Prakash wrote: >>> Add the ADC channels under the PMK8850 ADC node for the >>> other PMICS on the board with ADC peripherals. This includes >>> die temperature and VPH power channels per PMIC. >> >> [...] >> >>> + thermal-zones { >>> + sys-0-thermal { >> >> Please name it xo-therm or something similar to make the connection >> more obvious > > Sure, I'll update the node name to "xo-thermal" and make similar changes > in the other patch too. > >> >> [...] >> >>> +&pmcx0102_c_e0_temp_alarm { >>> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 2)>; >>> + io-channel-names = "thermal"; >>> +}; >>> + >>> +&pmcx0102_c_e1_temp_alarm { >>> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 2)>; >>> + io-channel-names = "thermal"; >>> +}; >>> + >>> +&pmcx0102_d_e0_temp_alarm { >>> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>; >>> + io-channel-names = "thermal"; >>> +}; >>> + >>> +&pmcx0102_d_e1_temp_alarm { >>> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 3)>; >>> + io-channel-names = "thermal"; >>> +}; >> >> Are these going to be always wired up this way on all Glymur boards? > > I'm not sure what you mean here - each temp-alarm peripheral here > is using the die_temp channel from the ADC on the same PMIC to > read the PMIC die temperature. Die_temp is an internal sensor > and the die_temp ADC channel is always present on any PMIC > which has ADC, it is not like thermistors which are optionally > connected to AMUX/GPIO pins and can change between boards, so > I think we can consider the above configuration will not change > between Glymur boards. > > Does this answer your question? Yes, thanks, I overlooked this Konrad