From: Shazad Hussain <quic_shazhuss@quicinc.com>
To: Eric Chanudet <echanude@redhat.com>, Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Sebastian Reichel <sre@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
<linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>,
"Parikshit Pareek (QUIC)" <quic_ppareek@quicinc.com>
Subject: Re: [PATCH v4 2/5] arm64: dts: qcom: sa8775p: add the pcie smmu node
Date: Wed, 19 Apr 2023 09:09:17 +0530 [thread overview]
Message-ID: <dc9ae9b8-57db-d5b2-4e3b-145105b0a45e@quicinc.com> (raw)
In-Reply-To: <20230418165224.vmok75fwcjqdxspe@echanude>
On 4/18/2023 10:22 PM, Eric Chanudet wrote:
> On Mon, Apr 17, 2023 at 02:58:41PM +0200, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>
>> Add the PCIe SMMU node for sa8775p platforms.
>>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
>> 1 file changed, 74 insertions(+)
>
> Hi Bartosz,
>
> Adding Shazad.
>
> I upgraded to the meta Shazad mentioned in v2[1], but I still get a
> synchronous external abort on reboot:
>
> [ 8.285500] arm-smmu 15200000.iommu: disabling translation
> 4 12.145913 Injecting instruction/data abort to VM 3, original ESR_EL2 = 0x93800047, fault VA = 0xffff80000a080000, fault IPA = 0x15200000, ELR_EL2 = 0xffffae99a42c96e4
> [ 8.310145] Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
> [ 8.316561] Modules linked in: qcom_pon crct10dif_ce gpucc_sa8775p i2c_qcom_geni spi_geni_qcom ufs_qcom phy_qcom_qmp_ufs socinfo fuse ipv6
> [ 8.331284] CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 6.3.0-rc7-next-20230417-00014-g93340f644112 #136
> [ 8.341365] Hardware name: Qualcomm SA8775P Ride (DT)
> [ 8.346555] pstate: 00400005 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 8.353705] pc : arm_smmu_device_shutdown+0x64/0x154
> [ 8.358815] lr : arm_smmu_device_shutdown+0x3c/0x154
> [ 8.363915] sp : ffff80000805bc00
> [ 8.367322] x29: ffff80000805bc00 x28: ffff69c250ca0000 x27: 0000000000000000
> [ 8.374643] x26: ffffae99a53357f8 x25: 0000000000000001 x24: ffffae99a60d5028
> [ 8.381963] x23: ffff69c2516ab890 x22: ffffae99a614e218 x21: ffff69c251668c10
> [ 8.389283] x20: ffff69c2516ab810 x19: ffff69c251479a80 x18: 0000000000000006
> [ 8.396603] x17: 0000000000000014 x16: 0000000000000030 x15: ffff80000805b5d0
> [ 8.403923] x14: 0000000000000000 x13: ffffae99a5ce1a28 x12: 00000000000005eb
> [ 8.411243] x11: 00000000000001f9 x10: ffffae99a5d39a28 x9 : ffffae99a5ce1a28
> [ 8.418563] x8 : 00000000ffffefff x7 : ffffae99a5d39a28 x6 : 80000000fffff000
> [ 8.425884] x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000
> [ 8.433204] x2 : 0000000000000000 x1 : ffff80000a080000 x0 : 0000000000000001
> [ 8.440524] Call trace:
> [ 8.443039] arm_smmu_device_shutdown+0x64/0x154
> [ 8.447784] platform_shutdown+0x24/0x34
> [ 8.451821] device_shutdown+0x150/0x258
> [ 8.455857] kernel_restart+0x40/0xc0
> [ 8.459623] __do_sys_reboot+0x1f0/0x274
> [ 8.463656] __arm64_sys_reboot+0x24/0x30
> [ 8.467778] invoke_syscall+0x48/0x114
> [ 8.471633] el0_svc_common+0x40/0xf4
> [ 8.475397] do_el0_svc+0x3c/0x9c
> [ 8.478806] el0_svc+0x2c/0x84
> [ 8.481947] el0t_64_sync_handler+0xf4/0x120
> [ 8.486334] el0t_64_sync+0x190/0x194
> [ 8.490100] Code: f9400404 b50005e4 f9400661 52800020 (b9000020)
> [ 8.496361] ---[ end trace 0000000000000000 ]---
>
> [1] https://lore.kernel.org/linux-arm-kernel/24804682-6ead-03b1-8b21-3ac413187c4a@quicinc.com/
>
Adding Parikshit to comment.
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 2343df7e0ea4..a23175352a20 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
>> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + pcie_smmu: iommu@15200000 {
>> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0x0 0x15200000 0x0 0x80000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <2>;
>> +
>> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> intc: interrupt-controller@17a00000 {
>> compatible = "arm,gic-v3";
>> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
>> --
>> 2.37.2
>>
>
-Shazad
next prev parent reply other threads:[~2023-04-19 3:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 12:58 [PATCH v4 0/5] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski
2023-04-17 12:58 ` [PATCH v4 1/5] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski
2023-04-17 12:58 ` [PATCH v4 2/5] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski
2023-04-18 7:32 ` Krzysztof Kozlowski
2023-04-18 16:52 ` Eric Chanudet
2023-04-18 20:48 ` Konrad Dybcio
2023-04-19 3:39 ` Shazad Hussain [this message]
2023-04-17 12:58 ` [PATCH v4 3/5] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski
2023-04-17 12:58 ` [PATCH v4 4/5] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Bartosz Golaszewski
2023-05-16 10:07 ` Bartosz Golaszewski
2023-05-16 10:33 ` Krzysztof Kozlowski
2023-05-16 11:34 ` Bartosz Golaszewski
2023-05-16 11:42 ` Krzysztof Kozlowski
2023-05-30 9:47 ` Bartosz Golaszewski
2023-05-30 13:17 ` Krzysztof Kozlowski
2023-06-05 15:29 ` Will Deacon
2023-04-17 12:58 ` [PATCH v4 5/5] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski
2023-05-15 3:33 ` (subset) [PATCH v4 0/5] arm64: dts: qcom: sa8775p: add more IOMMUs Bjorn Andersson
2023-06-05 16:35 ` Will Deacon
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