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Fri, 11 Sep 2026 10:42:36 -0700 (PDT) X-Received: by 2002:a05:6a00:4ac6:b0:84e:89a:b8ec with SMTP id d2e1a72fcca58-86b31ef6e46mr7785156b3a.11.1789148556310; Fri, 11 Sep 2026 10:42:36 -0700 (PDT) Received: from [192.168.0.6] ([49.204.105.169]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-86b286c49d2sm1515413b3a.10.2026.09.11.10.42.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Sep 2026 10:42:35 -0700 (PDT) Message-ID: Date: Fri, 11 Sep 2026 23:12:28 +0530 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/9] i2c: qcom-geni: Vote for SE clock rate using OPP To: Konrad Dybcio , Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-7-091697dbeb02@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: CT7yF_fF0hdOFIvQT-RbR934UU194-tR X-Authority-Analysis: v=2.4 cv=PLmaavqC c=1 sm=1 tr=0 ts=6aa43d8e cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=KFINdI5Z0390/lZYonNNQw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=NZ9nq7LxGt4YLS7AZqcA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: CT7yF_fF0hdOFIvQT-RbR934UU194-tR X-Proofpoint-Spam-Info: AW1haW4tMjYwOTExMDI0OCBTYWx0ZWRfX4EkNOSf1fa5t BJCQ6/f38tiYDZzENk5SeqbGOI/H0li2umiyUV4Ox7qzo9/HFFC3WTbTyuNC/0g420X3pI0aXRa hp84/iRBnr0YX2P38SEBL6HVEXUUx14= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTExMDI0OCBTYWx0ZWRfXzWSo88+43Uid K6g5wanjCpmsNybbM/XqcvR1uPHjGEd7a6udOKmTdSehiRSKyU59bjUVzmDw6pdpCTMWuwezxPG 2TlMDVoNtoqDH+UJ0wA83PIVqOwkhglrFD5yQLf1lzruP1/b3KVxyO1E7SjFUOu1H83eNUC4QrI xeL0v8SdVEUYkKYmdRV2snOyHAupOG470Xq/MbMPwfgQ0qA/NckM2mGShiAfKo/LRd/up11ispp fNsr1VgHUTMCevPIQtThzP6QHT9AAKngEoI1xlTkR6x51uMD65F3jHAtf22r8q1j3m5Oyr/3Ssn sx7TncFRS8vKl19zhU3vfjafile2aRw4wFN6sYxH6JOAUOmGcTyDhfNchtliex6XJL8Ih4F64g1 MvVH97yyMjh7wCcWRRwq/bzL9B6Y/C68xM6sIzOaCE+JG9q3q3bRzC7MJfvsT6PLTFOuI6jzu3i AyBKTz0B8h9ibSGmdQQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-11_06,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609110248 Hi Konrad, On 04-09-2026 14:22, Konrad Dybcio wrote: > On 8/27/26 7:59 PM, Praveen Talari wrote: >> The I2C driver currently assumes a fixed source clock selection and always >> programs SE_GENI_CLK_SEL to 0, which is not sufficient when the controller >> needs to switch between different source clocks. >> >> Add the source clock index and frequency to the I2C clock map entries and >> use them while configuring the controller. Request the required >> source clock rate through dev_pm_opp_set_rate() and program SE_GENI_CLK_SEL >> with the matching source index. >> >> Signed-off-by: Praveen Talari >> --- > [...] > >> + dev_pm_opp_set_rate(dev, 0); > This and the below call are unnecessary, rate and enablement/disablement > of a clock are orthogonal operations Yes, you are correct. However, in this case the rate change is primarily used to satisfy the voltage/performance requirements associated with the selected source clock frequency rather than the clock enable/disable state itself. The runtime PM handling follows the same approach currently used by the SPI and UART GENI drivers, where the performance vote is restored during runtime resume and released during runtime suspend. Please let me know if I'm overlooking something here. Thanks, Praveen Talari > > Konrad > >> + >> return 0; >> } >> >> @@ -1236,6 +1249,12 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) >> int ret = 0; >> struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); >> >> + if (gi2c->clk_fld && gi2c->clk_fld->src_clk_freq) { >> + ret = dev_pm_opp_set_rate(dev, gi2c->clk_fld->src_clk_freq); >> + if (ret) >> + return ret; >> + } >> + >> if (gi2c->dev_data->power_on) { >> ret = gi2c->dev_data->power_on(&gi2c->se); >> if (ret) >>