[PATCH v2 0/6] amd_pstate: Add guided autonomous mode support

[PATCH v2 0/6] amd_pstate: Add guided autonomous mode support

[Wyes Karny]

From ACPI spec[1] below 3 modes for CPPC can be defined:
1. Non autonomous: OS scaling governor specifies operating frequency/
   performance level through `Desired Performance` register and platform
follows that.
2. Guided autonomous: OS scaling governor specifies min and max
   frequencies/ performance levels through `Minimum Performance` and
`Maximum Performance` register, and platform can autonomously select an
operating frequency in this range.
3. Fully autonomous: OS only hints (via EPP) to platform for the required
   energy performance preference for the workload and platform autonomously
scales the frequency.

Currently (1) is supported by amd_pstate as passive mode, and (3) is
implemented by EPP support[2]. This change is to support (2).

In guided autonomous mode the min_perf is based on the input from the
scaling governor. For example, in case of schedutil this value depends
on the current utilization. And max_perf is set to max capacity.

To activate guided auto mode ``amd_pstate=guided`` command line
parameter has to be passed in the kernel.

Below are the results (normalized) of benchmarks with this patch:
System: Genoa 96C 192T
Kernel: v6.1-rc6 + patch
Scaling governor: schedutil

================ tbench  ================
tbench result comparison: (higher the better)
Here results are throughput (MB/s)
Clients 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
    1	   1.00 (0.00 pct)	   1.16 (16.00 pct)	   2.20 (120.00 pct)
    2	   1.97 (0.00 pct)	   2.29 (16.24 pct)	   4.38 (122.33 pct)
    4	   3.95 (0.00 pct)	   4.51 (14.17 pct)	   8.50 (115.18 pct)
    8	   7.83 (0.00 pct)	   8.89 (13.53 pct)	  16.62 (112.26 pct)
   16	  15.28 (0.00 pct)	  16.81 (10.01 pct)	  31.02 (103.01 pct)
   32	  41.64 (0.00 pct)	  30.67 (-26.34 pct)	  55.63 (33.59 pct)
   64	  91.29 (0.00 pct)	  79.67 (-12.72 pct)	  91.74 (0.49 pct)
  128	 118.06 (0.00 pct)	 122.34 (3.62 pct)	 122.04 (3.37 pct)
  256	 260.47 (0.00 pct)	 264.31 (1.47 pct)	 264.49 (1.54 pct)
  512	 254.16 (0.00 pct)	 245.25 (-3.50 pct)	 245.50 (-3.40 pct)
tbench power comparison: (lower the better)
Clients 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
    1	   1.00 (0.00 pct)	   1.00 (0.00 pct)	   1.15 (15.00 pct)
    2	   0.99 (0.00 pct)	   1.00 (1.01 pct)	   1.17 (18.18 pct)
    4	   1.01 (0.00 pct)	   1.02 (0.99 pct)	   1.24 (22.77 pct)
    8	   1.05 (0.00 pct)	   1.06 (0.95 pct)	   1.36 (29.52 pct)
   16	   1.15 (0.00 pct)	   1.13 (-1.73 pct)	   1.58 (37.39 pct)
   32	   1.71 (0.00 pct)	   1.30 (-23.97 pct)	   1.96 (14.61 pct)
   64	   2.35 (0.00 pct)	   2.15 (-8.51 pct)	   2.36 (0.42 pct)
  128	   2.77 (0.00 pct)	   2.77 (0.00 pct)	   2.78 (0.36 pct)
  256	   3.39 (0.00 pct)	   3.41 (0.58 pct)	   3.43 (1.17 pct)
  512	   3.42 (0.00 pct)	   3.40 (-0.58 pct)	   3.41 (-0.29 pct)

================ dbench  ================
dbench result comparison: (higher the better)
Here results are throughput (MB/s)
Clients 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
    1	   1.00 (0.00 pct)	   0.96 (-4.00 pct)	   1.02 (2.00 pct)
    2	   1.89 (0.00 pct)	   1.90 (0.52 pct)	   1.91 (1.05 pct)
    4	   3.39 (0.00 pct)	   3.31 (-2.35 pct)	   3.38 (-0.29 pct)
    8	   5.56 (0.00 pct)	   5.46 (-1.79 pct)	   5.60 (0.71 pct)
   16	   7.25 (0.00 pct)	   7.90 (8.96 pct)	   8.29 (14.34 pct)
   32	  10.85 (0.00 pct)	  10.00 (-7.83 pct)	  10.40 (-4.14 pct)
   64	  12.30 (0.00 pct)	  11.94 (-2.92 pct)	  11.82 (-3.90 pct)
  128	  12.56 (0.00 pct)	  12.30 (-2.07 pct)	  12.98 (3.34 pct)
  256	   6.55 (0.00 pct)	   6.54 (-0.15 pct)	   7.38 (12.67 pct)
  512	   1.61 (0.00 pct)	   1.58 (-1.86 pct)	   1.95 (21.11 pct)
dbench power comparison: (lower the better)
Clients 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
    1	   1.00 (0.00 pct)	   1.01 (1.00 pct)	   1.05 (5.00 pct)
    2	   1.07 (0.00 pct)	   1.07 (0.00 pct)	   1.09 (1.86 pct)
    4	   1.15 (0.00 pct)	   1.15 (0.00 pct)	   1.16 (0.86 pct)
    8	   1.26 (0.00 pct)	   1.26 (0.00 pct)	   1.27 (0.79 pct)
   16	   1.39 (0.00 pct)	   1.41 (1.43 pct)	   1.43 (2.87 pct)
   32	   1.60 (0.00 pct)	   1.56 (-2.50 pct)	   1.59 (-0.62 pct)
   64	   1.75 (0.00 pct)	   1.75 (0.00 pct)	   1.74 (-0.57 pct)
  128	   1.90 (0.00 pct)	   1.91 (0.52 pct)	   1.93 (1.57 pct)
  256	   1.76 (0.00 pct)	   1.77 (0.56 pct)	   1.85 (5.11 pct)
  512	   1.55 (0.00 pct)	   1.49 (-3.87 pct)	   1.73 (11.61 pct)

================ git-source  ================
git-source result comparison: (higher the better)
Here results are throughput (compilations per 1000 sec)
Threads 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
  192	   1.00 (0.00 pct)	   0.94 (-5.70 pct)	   1.00 (0.00 pct)
git-source power comparison: (lower the better)
Threads 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
  192	   1.00 (0.00 pct)	   1.03 (3.00 pct)	   1.02 (2.00 pct)

================ kernbench  ================
kernbench result comparison: (higher the better)
Here results are throughput (compilations per 1000 sec)
Load 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
32	   1.00 (0.00 pct)	   0.94 (-6.00 pct)	   1.02 (2.00 pct)
48	   1.24 (0.00 pct)	   1.16 (-6.45 pct)	   1.24 (0.00 pct)
64	   1.35 (0.00 pct)	   1.30 (-3.70 pct)	   1.39 (2.96 pct)
96	   1.42 (0.00 pct)	   1.28 (-9.85 pct)	   1.48 (4.22 pct)
128	   1.39 (0.00 pct)	   1.29 (-7.19 pct)	   1.41 (1.43 pct)
192	   1.32 (0.00 pct)	   1.18 (-10.60 pct)	   1.32 (0.00 pct)
256	   1.28 (0.00 pct)	   1.14 (-10.93 pct)	   1.29 (0.78 pct)
384	   1.28 (0.00 pct)	   1.13 (-11.71 pct)	   1.27 (-0.78 pct)
git-source power comparison: (lower the better)
Clients 	acpi-cpufreq			amd_pst+passive			amd_pst+guided
   32	   1.00 (0.00 pct)	   1.04 (4.00 pct)	   0.95 (-5.00 pct)
   48	   0.83 (0.00 pct)	   0.90 (8.43 pct)	   0.82 (-1.20 pct)
   64	   0.80 (0.00 pct)	   0.82 (2.50 pct)	   0.75 (-6.25 pct)
   96	   0.77 (0.00 pct)	   0.81 (5.19 pct)	   0.75 (-2.59 pct)
  128	   0.78 (0.00 pct)	   0.82 (5.12 pct)	   0.75 (-3.84 pct)
  192	   0.84 (0.00 pct)	   0.89 (5.95 pct)	   0.83 (-1.19 pct)
  256	   0.84 (0.00 pct)	   0.89 (5.95 pct)	   0.84 (0.00 pct)
  384	   0.84 (0.00 pct)	   0.90 (7.14 pct)	   0.84 (0.00 pct)

Note: this series is based on top of EPP v9 [3] series

Change log:
v1 -> v2:
- Fix issue with shared mem systems.
- Rebase on top of EPP series.

[1]: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
[2]: https://lore.kernel.org/lkml/20221110175847.3098728-1-Perry.Yuan@amd.com/
[3]: https://lore.kernel.org/linux-pm/20221225163442.2205660-1-perry.yuan@amd.com/

Wyes Karny (6):
  acpi: cppc: Add min and max perf reg writing support
  acpi: cppc: Add auto select register read/write support
  cpufreq: amd_pstate: Add guided autonomous mode
  Documentation: amd_pstate: Move amd_pstate param to alphabetical order
  cpufreq: amd_pstate: Add guided mode control support via sysfs
  Documentation: amd_pstate: Update amd_pstate status sysfs for guided

 .../admin-guide/kernel-parameters.txt         |  41 +++--
 Documentation/admin-guide/pm/amd-pstate.rst   |  29 ++-
 drivers/acpi/cppc_acpi.c                      | 113 +++++++++++-
 drivers/cpufreq/amd-pstate.c                  | 173 ++++++++++++++----
 include/acpi/cppc_acpi.h                      |  11 ++
 include/linux/amd-pstate.h                    |   2 +
 6 files changed, 297 insertions(+), 72 deletions(-)

-- 
2.34.1

[PATCH v2 1/6] acpi: cppc: Add min and max perf reg writing support

[Wyes Karny]

Currently writing of min and max perf register is deferred in
cppc_set_perf function. In CPPC guided mode, these registers needed to
be written to guide PMFW about min and max perf levels. Add this support
to make guided mode work properly on shared memory systems.

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 drivers/acpi/cppc_acpi.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 02d83c807271..c936ff503965 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1487,7 +1487,7 @@ EXPORT_SYMBOL_GPL(cppc_set_enable);
 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 {
 	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
-	struct cpc_register_resource *desired_reg;
+	struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
 	int ret = 0;
@@ -1498,6 +1498,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	}
 
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
+	min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
+	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
 
 	/*
 	 * This is Phase-I where we want to write to CPC registers
@@ -1506,7 +1508,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * Since read_lock can be acquired by multiple CPUs simultaneously we
 	 * achieve that goal here
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (pcc_ss_id < 0) {
 			pr_debug("Invalid pcc_ss_id\n");
 			return -ENODEV;
@@ -1529,13 +1531,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 		cpc_desc->write_cmd_status = 0;
 	}
 
-	/*
-	 * Skip writing MIN/MAX until Linux knows how to come up with
-	 * useful values.
-	 */
 	cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
+	cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
+	cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
 
-	if (CPC_IN_PCC(desired_reg))
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
 		up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
 	/*
 	 * This is Phase-II where we transfer the ownership of PCC to Platform
@@ -1583,7 +1583,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * case during a CMD_READ and if there are pending writes it delivers
 	 * the write command before servicing the read command
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
 			/* Update only if there are pending write commands */
 			if (pcc_ss_data->pending_pcc_write_cmd)
-- 
2.34.1

[PATCH v2 2/6] acpi: cppc: Add auto select register read/write support

[Wyes Karny]

For some shared memory based systems, the autonomous selection bit
needed to be set explicitly. Add autonomous selection register related
APIs to acpi driver, which amd_pstate driver uses later.

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 drivers/acpi/cppc_acpi.c | 97 ++++++++++++++++++++++++++++++++++++++++
 include/acpi/cppc_acpi.h | 11 +++++
 2 files changed, 108 insertions(+)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index c936ff503965..e47b2cfe022e 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1432,6 +1432,103 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
 }
 EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
 
+/*
+ * cppc_get_auto_sel_caps - Read autonomous selection register.
+ * @cpunum : CPU from which to read register.
+ * @perf_caps : struct where autonomous selection register value is updated.
+ */
+int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
+{
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
+	struct cpc_register_resource *auto_sel_reg;
+	u64  auto_sel;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
+		return -ENODEV;
+	}
+
+	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+
+	if (!CPC_SUPPORTED(auto_sel_reg))
+		pr_warn_once("Autonomous mode is not unsupported!\n");
+
+	if (CPC_IN_PCC(auto_sel_reg)) {
+		int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
+		struct cppc_pcc_data *pcc_ss_data = NULL;
+		int ret = 0;
+
+		if (pcc_ss_id < 0)
+			return -ENODEV;
+
+		pcc_ss_data = pcc_data[pcc_ss_id];
+
+		down_write(&pcc_ss_data->pcc_lock);
+
+		if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
+			cpc_read(cpunum, auto_sel_reg, &auto_sel);
+			perf_caps->auto_sel = (bool)auto_sel;
+		} else {
+			ret = -EIO;
+		}
+
+		up_write(&pcc_ss_data->pcc_lock);
+
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
+
+/*
+ * cppc_set_auto_sel - Write autonomous selection register.
+ * @cpunum : CPU to which to write register.
+ * @enable : the desired value of autonomous selection resiter to be updated.
+ */
+int cppc_set_auto_sel(int cpu, bool enable)
+{
+	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+	struct cpc_register_resource *auto_sel_reg;
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+	struct cppc_pcc_data *pcc_ss_data = NULL;
+	int ret = -EINVAL;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+		return -ENODEV;
+	}
+
+	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+
+	if (CPC_IN_PCC(auto_sel_reg)) {
+		if (pcc_ss_id < 0) {
+			pr_debug("Invalid pcc_ss_id\n");
+			return -ENODEV;
+		}
+
+		if (CPC_SUPPORTED(auto_sel_reg)) {
+			ret = cpc_write(cpu, auto_sel_reg, enable);
+			if (ret)
+				return ret;
+		}
+
+		pcc_ss_data = pcc_data[pcc_ss_id];
+
+		down_write(&pcc_ss_data->pcc_lock);
+		/* after writing CPC, transfer the ownership of PCC to platform */
+		ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+		up_write(&pcc_ss_data->pcc_lock);
+	} else {
+		ret = -ENOTSUPP;
+		pr_debug("_CPC in PCC is not supported\n");
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
+
+
 /**
  * cppc_set_enable - Set to enable CPPC on the processor by writing the
  * Continuous Performance Control package EnableRegister field.
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 6b487a5bd638..6126c977ece0 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -109,6 +109,7 @@ struct cppc_perf_caps {
 	u32 lowest_freq;
 	u32 nominal_freq;
 	u32 energy_perf;
+	bool auto_sel;
 };
 
 struct cppc_perf_ctrls {
@@ -153,6 +154,8 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
 extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
 extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf);
 extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable);
+extern int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps);
+extern int cppc_set_auto_sel(int cpu, bool enable);
 #else /* !CONFIG_ACPI_CPPC_LIB */
 static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
 {
@@ -214,6 +217,14 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_set_auto_sel(int cpu, bool enable)
+{
+	return -ENOTSUPP;
+}
+static inline int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
+{
+	return -ENOTSUPP;
+}
 #endif /* !CONFIG_ACPI_CPPC_LIB */
 
 #endif /* _CPPC_ACPI_H*/
-- 
2.34.1

[PATCH v2 3/6] cpufreq: amd_pstate: Add guided autonomous mode

[Wyes Karny]

From ACPI spec below 3 modes for CPPC can be defined:
1. Non autonomous: OS scaling governor specifies operating frequency/
   performance level through `Desired Performance` register and platform
follows that.
2. Guided autonomous: OS scaling governor specifies min and max
   frequencies/ performance levels through `Minimum Performance` and
`Maximum Performance` register, and platform can autonomously select an
operating frequency in this range.
3. Fully autonomous: OS only hints (via EPP) to platform for the required
   energy performance preference for the workload and platform autonomously
scales the frequency.

Currently (1) is supported by amd_pstate as passive mode, and (3) is
implemented by EPP support. This change is to support (2).

In guided autonomous mode the min_perf is based on the input from the
scaling governor. For example, in case of schedutil this value depends
on the current utilization. And max_perf is set to max capacity.

To activate guided auto mode ``amd_pstate=guided`` command line
parameter has to be passed in the kernel.

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 .../admin-guide/kernel-parameters.txt         | 15 ++++++----
 drivers/cpufreq/amd-pstate.c                  | 29 ++++++++++++++++---
 include/linux/amd-pstate.h                    |  2 ++
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index e3618dfdb36a..0d8486325c9a 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -7015,11 +7015,11 @@
 			  Do not enable amd_pstate as the default
 			  scaling driver for the supported processors
 			passive
-			  Use amd_pstate as a scaling driver, driver requests a
-			  desired performance on this abstract scale and the power
-			  management firmware translates the requests into actual
-			  hardware states (core frequency, data fabric and memory
-			  clocks etc.)
+			  Use amd_pstate with passive mode as a scaling driver.
+			  In this mode autonomous selection is disabled.
+			  Driver requests a desired performance level and platform
+			  tires to match the same performance level (if it is
+			  satisfied by guaranteed performance level).
 			active
 			  Use amd_pstate_epp driver instance as the scaling driver,
 			  driver provides a hint to the hardware if software wants
@@ -7027,3 +7027,8 @@
 			  to the CPPC firmware. then CPPC power algorithm will
 			  calculate the runtime workload and adjust the realtime cores
 			  frequency.
+			guided
+			  Activate guided autonomous mode. Driver requests minimum and
+			  maximum performance level and the platform autonomously
+			  selects a performance level in this range and appropriate
+			  to the current workload.
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 87450413cf45..20d78dad712d 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -267,6 +267,20 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
 		   cppc_perf.lowest_nonlinear_perf);
 	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
 
+	ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf);
+	if (ret) {
+		pr_warn("failed to get auto_sel\n");
+		return 0;
+	}
+
+	if (cppc_state == AMD_PSTATE_PASSIVE)
+		ret = cppc_set_auto_sel(cpudata->cpu, 0);
+	else if (cppc_state == AMD_PSTATE_GUIDED)
+		ret = cppc_set_auto_sel(cpudata->cpu, 1);
+
+	if (ret)
+		pr_warn("failed to set auto_sel\n");
+
 	return 0;
 }
 
@@ -344,12 +358,18 @@ static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
 }
 
 static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
-			      u32 des_perf, u32 max_perf, bool fast_switch)
+			      u32 des_perf, u32 max_perf, bool fast_switch, int guv_flags)
 {
 	u64 prev = READ_ONCE(cpudata->cppc_req_cached);
 	u64 value = prev;
 
 	des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
+
+	if ((cppc_state == AMD_PSTATE_GUIDED) && (guv_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) {
+		min_perf = des_perf;
+		des_perf = 0;
+	}
+
 	value &= ~AMD_CPPC_MIN_PERF(~0L);
 	value |= AMD_CPPC_MIN_PERF(min_perf);
 
@@ -404,7 +424,7 @@ static int amd_pstate_target(struct cpufreq_policy *policy,
 
 	cpufreq_freq_transition_begin(policy, &freqs);
 	amd_pstate_update(cpudata, min_perf, des_perf,
-			  max_perf, false);
+			  max_perf, false, policy->governor->flags);
 	cpufreq_freq_transition_end(policy, &freqs, false);
 
 	return 0;
@@ -438,7 +458,8 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
 	if (max_perf < min_perf)
 		max_perf = min_perf;
 
-	amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true);
+	amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true,
+			policy->governor->flags);
 	cpufreq_cpu_put(policy);
 }
 
@@ -1233,7 +1254,7 @@ static int __init amd_pstate_init(void)
 	/* capability check */
 	if (boot_cpu_has(X86_FEATURE_CPPC)) {
 		pr_debug("AMD CPPC MSR based functionality is supported\n");
-		if (cppc_state == AMD_PSTATE_PASSIVE)
+		if (cppc_state != AMD_PSTATE_ACTIVE)
 			default_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
 	} else {
 		pr_debug("AMD CPPC shared memory based functionality is supported\n");
diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
index 15761a581e82..e07cfbd63560 100644
--- a/include/linux/amd-pstate.h
+++ b/include/linux/amd-pstate.h
@@ -92,6 +92,7 @@ enum amd_pstate_mode {
 	AMD_PSTATE_DISABLE = 0,
 	AMD_PSTATE_PASSIVE,
 	AMD_PSTATE_ACTIVE,
+	AMD_PSTATE_GUIDED,
 	AMD_PSTATE_MAX,
 };
 
@@ -99,6 +100,7 @@ static const char * const amd_pstate_mode_string[] = {
 	[AMD_PSTATE_DISABLE]     = "disable",
 	[AMD_PSTATE_PASSIVE]     = "passive",
 	[AMD_PSTATE_ACTIVE]      = "active",
+	[AMD_PSTATE_GUIDED]      = "guided",
 	NULL,
 };
 
-- 
2.34.1

[PATCH v2 4/6] Documentation: amd_pstate: Move amd_pstate param to alphabetical order

[Wyes Karny]

Move amd_pstate command line param description to correct alphabetical
order.

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 .../admin-guide/kernel-parameters.txt         | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 0d8486325c9a..5f6a3a34251e 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -339,6 +339,29 @@
 			             This mode requires kvm-amd.avic=1.
 			             (Default when IOMMU HW support is present.)
 
+	amd_pstate=	[X86]
+			disable
+			  Do not enable amd_pstate as the default
+			  scaling driver for the supported processors
+			passive
+			  Use amd_pstate with passive mode as a scaling driver.
+			  In this mode autonomous selection is disabled.
+			  Driver requests a desired performance level and platform
+			  tires to match the same performance level (if it is
+			  satisfied by guaranteed performance level).
+			active
+			  Use amd_pstate_epp driver instance as the scaling driver,
+			  driver provides a hint to the hardware if software wants
+			  to bias toward performance (0x0) or energy efficiency (0xff)
+			  to the CPPC firmware. then CPPC power algorithm will
+			  calculate the runtime workload and adjust the realtime cores
+			  frequency.
+			guided
+			  Activate guided autonomous mode. Driver requests minimum and
+			  maximum performance level and the platform autonomously
+			  selects a performance level in this range and appropriate
+			  to the current workload.
+
 	amijoy.map=	[HW,JOY] Amiga joystick support
 			Map of devices attached to JOY0DAT and JOY1DAT
 			Format: <a>,<b>
@@ -7009,26 +7032,3 @@
 				memory, and other data can't be written using
 				xmon commands.
 			off	xmon is disabled.
-
-	amd_pstate=	[X86]
-			disable
-			  Do not enable amd_pstate as the default
-			  scaling driver for the supported processors
-			passive
-			  Use amd_pstate with passive mode as a scaling driver.
-			  In this mode autonomous selection is disabled.
-			  Driver requests a desired performance level and platform
-			  tires to match the same performance level (if it is
-			  satisfied by guaranteed performance level).
-			active
-			  Use amd_pstate_epp driver instance as the scaling driver,
-			  driver provides a hint to the hardware if software wants
-			  to bias toward performance (0x0) or energy efficiency (0xff)
-			  to the CPPC firmware. then CPPC power algorithm will
-			  calculate the runtime workload and adjust the realtime cores
-			  frequency.
-			guided
-			  Activate guided autonomous mode. Driver requests minimum and
-			  maximum performance level and the platform autonomously
-			  selects a performance level in this range and appropriate
-			  to the current workload.
-- 
2.34.1

[PATCH v2 5/6] cpufreq: amd_pstate: Add guided mode control support via sysfs

[Wyes Karny]

amd_pstate driver's `status` sysfs entry helps to control the driver's
mode dynamically by user. After the addition of guided mode the
combinations of mode transitions have been increased (16 combinations).
Therefore optimise the amd_pstate_update_status function by implementing
a state transition table.

There are 4 states amd_pstate supports, namely: 'disable', 'passive',
'active', and 'guided'.  The transition from any state to any other
state is possible after this change. Only if the state requested matches
with the current state then -EBUSY value is returned.

Sysfs interface:

To disable amd_pstate driver:
 # echo disable > /sys/devices/system/cpu/amd_pstate/status

To enable passive mode:
 # echo passive > /sys/devices/system/cpu/amd_pstate/status

To change mode to active:
 # echo active > /sys/devices/system/cpu/amd_pstate/status

To change mode to guided:
 # echo guided > /sys/devices/system/cpu/amd_pstate/status

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 144 ++++++++++++++++++++++++++---------
 1 file changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 20d78dad712d..4a2b559fd712 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -65,6 +65,8 @@ static struct cpufreq_driver amd_pstate_epp_driver;
 static int cppc_state = AMD_PSTATE_DISABLE;
 struct kobject *amd_pstate_kobj;
 
+typedef int (*cppc_mode_transition_fn)(int);
+
 static inline int get_mode_idx_from_str(const char *str, size_t size)
 {
 	int i;
@@ -806,55 +808,127 @@ static ssize_t amd_pstate_show_status(char *buf)
 
 static void amd_pstate_driver_cleanup(void)
 {
+	amd_pstate_enable(false);
+	cppc_state = AMD_PSTATE_DISABLE;
 	default_pstate_driver = NULL;
 }
 
-static int amd_pstate_update_status(const char *buf, size_t size)
+static int amd_pstate_register_driver(int mode)
 {
 	int ret;
-	int mode_idx;
 
-	if (size > 7 || size < 3)
+	if (mode == AMD_PSTATE_PASSIVE || mode == AMD_PSTATE_GUIDED)
+		default_pstate_driver = &amd_pstate_driver;
+	else if (mode == AMD_PSTATE_ACTIVE)
+		default_pstate_driver = &amd_pstate_epp_driver;
+	else
 		return -EINVAL;
-	mode_idx = get_mode_idx_from_str(buf, size);
 
-	switch(mode_idx) {
-	case AMD_PSTATE_DISABLE:
-		if (!default_pstate_driver)
-			return -EINVAL;
-		if (cppc_state == AMD_PSTATE_ACTIVE)
-			return -EBUSY;
-		ret = cpufreq_unregister_driver(default_pstate_driver);
+	ret = cpufreq_register_driver(default_pstate_driver);
+	if (ret) {
 		amd_pstate_driver_cleanup();
-		break;
-	case AMD_PSTATE_PASSIVE:
-		if (default_pstate_driver) {
-			if (default_pstate_driver == &amd_pstate_driver)
-				return 0;
-			cpufreq_unregister_driver(default_pstate_driver);
-			cppc_state = AMD_PSTATE_PASSIVE;
-			default_pstate_driver = &amd_pstate_driver;
-		}
+		return ret;
+	}
 
-		ret = cpufreq_register_driver(default_pstate_driver);
-		break;
-	case AMD_PSTATE_ACTIVE:
-		if (default_pstate_driver) {
-			if (default_pstate_driver == &amd_pstate_epp_driver)
-				return 0;
-			cpufreq_unregister_driver(default_pstate_driver);
-			default_pstate_driver = &amd_pstate_epp_driver;
-			cppc_state = AMD_PSTATE_ACTIVE;
+	cppc_state = mode;
+	return 0;
+}
+
+static int amd_pstate_unregister_driver(int dummy)
+{
+	int ret;
+
+	ret = cpufreq_unregister_driver(default_pstate_driver);
+
+	if (ret)
+		return ret;
+
+	amd_pstate_driver_cleanup();
+	return 0;
+}
+
+static void amd_pstate_change_mode_without_dvr_change(int mode)
+{
+	int cpu = 0;
+
+	cppc_state = mode;
+	if (!boot_cpu_has(X86_FEATURE_CPPC)) {
+		if (cppc_state == AMD_PSTATE_PASSIVE) {
+			for_each_present_cpu(cpu) {
+				cppc_set_auto_sel(cpu, 0);
+			}
+		} else if (cppc_state == AMD_PSTATE_GUIDED) {
+				for_each_present_cpu(cpu) {
+					cppc_set_auto_sel(cpu, 1);
+				}
 		}
+	}
+}
 
-		ret = cpufreq_register_driver(default_pstate_driver);
-		break;
-	default:
-		break;
-		ret = -EINVAL;
+static int amd_pstate_change_driver_mode(int mode)
+{
+	int ret;
+
+	if ((mode == AMD_PSTATE_GUIDED && cppc_state == AMD_PSTATE_PASSIVE) ||
+			(mode == AMD_PSTATE_PASSIVE && cppc_state == AMD_PSTATE_GUIDED)) {
+		amd_pstate_change_mode_without_dvr_change(mode);
+		return 0;
 	}
 
-	return ret;
+	ret = amd_pstate_unregister_driver(0);
+	if (ret)
+		return ret;
+
+	ret = amd_pstate_register_driver(mode);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Mode transition table */
+cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = {
+	[AMD_PSTATE_DISABLE]         = {
+		[AMD_PSTATE_DISABLE]     = NULL,
+		[AMD_PSTATE_PASSIVE]     = amd_pstate_register_driver,
+		[AMD_PSTATE_ACTIVE]      = amd_pstate_register_driver,
+		[AMD_PSTATE_GUIDED]      = amd_pstate_register_driver,
+	},
+	[AMD_PSTATE_PASSIVE]         = {
+		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
+		[AMD_PSTATE_PASSIVE]     = NULL,
+		[AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
+		[AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
+	},
+	[AMD_PSTATE_ACTIVE]          = {
+		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
+		[AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
+		[AMD_PSTATE_ACTIVE]      = NULL,
+		[AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
+	},
+	[AMD_PSTATE_GUIDED]          = {
+		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
+		[AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
+		[AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
+		[AMD_PSTATE_GUIDED]      = NULL,
+	},
+};
+
+static int amd_pstate_update_status(const char *buf, size_t size)
+{
+	int mode_idx;
+
+	if (size > 7 || size < 3)
+		return -EINVAL;
+	mode_idx = get_mode_idx_from_str(buf, size);
+
+	if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX)
+		return -EINVAL;
+
+	if (mode_state_machine[cppc_state][mode_idx])
+		return mode_state_machine[cppc_state][mode_idx](mode_idx);
+
+	return -EBUSY;
 }
 
 static ssize_t show_status(struct kobject *kobj,
-- 
2.34.1

[PATCH v2 6/6] Documentation: amd_pstate: Update amd_pstate status sysfs for guided

[Wyes Karny]

Update amd_pstate status sysfs for guided mode.

Signed-off-by: Wyes Karny <wyes.karny@amd.com>
---
 Documentation/admin-guide/pm/amd-pstate.rst | 29 ++++++++++++++++-----
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
index 55396981266a..92fa22e45a2b 100644
--- a/Documentation/admin-guide/pm/amd-pstate.rst
+++ b/Documentation/admin-guide/pm/amd-pstate.rst
@@ -303,13 +303,16 @@ efficiency frequency management method on AMD processors.
 AMD Pstate Driver Operation Modes
 =================================
 
-``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and
-CPPC non-autonomous(passive) mode.
-active mode and passive mode can be chosen by different kernel parameters.
-When in Autonomous mode, CPPC ignores requests done in the Desired Performance
-Target register and takes into account only the values set to the Minimum requested
-performance, Maximum requested performance, and Energy Performance Preference
-registers. When Autonomous is disabled, it only considers the Desired Performance Target.
+``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, guided
+autonomous (guided) mode and non-autonomous (passive) mode.
+Active/passive/guided mode can be chosen by different kernel parameters. In
+autonomous mode, platform ignores the desired performance level request and
+takes into account only the values set to the Minimum requested performance,
+Maximum requested performance and Energy Performance Preference registers. In
+non-autonomous mode, platform gets desired performance level from OS directly
+through Desired Performance Register. In guided-autonomous mode, platform sets
+operating performance level autonomously according to the current workload and
+within the limits set by OS through min and max performance registers.
 
 Active Mode
 ------------
@@ -338,6 +341,15 @@ to the Performance Reduction Tolerance register. Above the nominal performance l
 processor must provide at least nominal performance requested and go higher if current
 operating conditions allow.
 
+Guided Mode
+-----------
+
+``amd_pstate=guided``
+
+If ``amd_pstate=guided`` is passed to kernel command line option then this mode
+is activated.  In this mode, driver requests minimum and maximum performance
+level and the platform autonomously selects a performance level in this range
+and appropriate to the current workload.
 
 User Space Interface in ``sysfs``
 =================================
@@ -358,6 +370,9 @@ control its functionality at the system level.  They are located in the
 	"passive"
 		The driver is functional and in the ``passive mode``
 
+        "guided"
+                The driver is functional and in the ``guided mode``
+
 	"disable"
 		The driver is unregistered and not functional now.
 
-- 
2.34.1

Re: [PATCH v2 1/6] acpi: cppc: Add min and max perf reg writing support

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
> Currently writing of min and max perf register is deferred in
> cppc_set_perf function. In CPPC guided mode, these registers needed to
> be written to guide PMFW about min and max perf levels. Add this support

This is generic code, so  I think rather than PMFW you should just say 
"the platform".

> to make guided mode work properly on shared memory systems.

on AMD shared memory systems.

> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>

With the commit message cleaned up:

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   drivers/acpi/cppc_acpi.c | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index 02d83c807271..c936ff503965 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -1487,7 +1487,7 @@ EXPORT_SYMBOL_GPL(cppc_set_enable);
>   int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>   {
>   	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> -	struct cpc_register_resource *desired_reg;
> +	struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
>   	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
>   	struct cppc_pcc_data *pcc_ss_data = NULL;
>   	int ret = 0;
> @@ -1498,6 +1498,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>   	}
>   
>   	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
> +	min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
> +	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
>   
>   	/*
>   	 * This is Phase-I where we want to write to CPC registers
> @@ -1506,7 +1508,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>   	 * Since read_lock can be acquired by multiple CPUs simultaneously we
>   	 * achieve that goal here
>   	 */
> -	if (CPC_IN_PCC(desired_reg)) {
> +	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
>   		if (pcc_ss_id < 0) {
>   			pr_debug("Invalid pcc_ss_id\n");
>   			return -ENODEV;
> @@ -1529,13 +1531,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>   		cpc_desc->write_cmd_status = 0;
>   	}
>   
> -	/*
> -	 * Skip writing MIN/MAX until Linux knows how to come up with
> -	 * useful values.
> -	 */
>   	cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
> +	cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
> +	cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
>   
> -	if (CPC_IN_PCC(desired_reg))
> +	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
>   		up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
>   	/*
>   	 * This is Phase-II where we transfer the ownership of PCC to Platform
> @@ -1583,7 +1583,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>   	 * case during a CMD_READ and if there are pending writes it delivers
>   	 * the write command before servicing the read command
>   	 */
> -	if (CPC_IN_PCC(desired_reg)) {
> +	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
>   		if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
>   			/* Update only if there are pending write commands */
>   			if (pcc_ss_data->pending_pcc_write_cmd)

Re: [PATCH v2 4/6] Documentation: amd_pstate: Move amd_pstate param to alphabetical order

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
> Move amd_pstate command line param description to correct alphabetical
> order.
> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>

> ---
>   .../admin-guide/kernel-parameters.txt         | 46 +++++++++----------
>   1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 0d8486325c9a..5f6a3a34251e 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -339,6 +339,29 @@
>   			             This mode requires kvm-amd.avic=1.
>   			             (Default when IOMMU HW support is present.)
>   
> +	amd_pstate=	[X86]
> +			disable
> +			  Do not enable amd_pstate as the default
> +			  scaling driver for the supported processors
> +			passive
> +			  Use amd_pstate with passive mode as a scaling driver.
> +			  In this mode autonomous selection is disabled.
> +			  Driver requests a desired performance level and platform
> +			  tires to match the same performance level (if it is
> +			  satisfied by guaranteed performance level).
> +			active
> +			  Use amd_pstate_epp driver instance as the scaling driver,
> +			  driver provides a hint to the hardware if software wants
> +			  to bias toward performance (0x0) or energy efficiency (0xff)
> +			  to the CPPC firmware. then CPPC power algorithm will
> +			  calculate the runtime workload and adjust the realtime cores
> +			  frequency.
> +			guided
> +			  Activate guided autonomous mode. Driver requests minimum and
> +			  maximum performance level and the platform autonomously
> +			  selects a performance level in this range and appropriate
> +			  to the current workload.
> +
>   	amijoy.map=	[HW,JOY] Amiga joystick support
>   			Map of devices attached to JOY0DAT and JOY1DAT
>   			Format: <a>,<b>
> @@ -7009,26 +7032,3 @@
>   				memory, and other data can't be written using
>   				xmon commands.
>   			off	xmon is disabled.
> -
> -	amd_pstate=	[X86]
> -			disable
> -			  Do not enable amd_pstate as the default
> -			  scaling driver for the supported processors
> -			passive
> -			  Use amd_pstate with passive mode as a scaling driver.
> -			  In this mode autonomous selection is disabled.
> -			  Driver requests a desired performance level and platform
> -			  tires to match the same performance level (if it is
> -			  satisfied by guaranteed performance level).
> -			active
> -			  Use amd_pstate_epp driver instance as the scaling driver,
> -			  driver provides a hint to the hardware if software wants
> -			  to bias toward performance (0x0) or energy efficiency (0xff)
> -			  to the CPPC firmware. then CPPC power algorithm will
> -			  calculate the runtime workload and adjust the realtime cores
> -			  frequency.
> -			guided
> -			  Activate guided autonomous mode. Driver requests minimum and
> -			  maximum performance level and the platform autonomously
> -			  selects a performance level in this range and appropriate
> -			  to the current workload.

Re: [PATCH v2 5/6] cpufreq: amd_pstate: Add guided mode control support via sysfs

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
> amd_pstate driver's `status` sysfs entry helps to control the driver's
> mode dynamically by user. After the addition of guided mode the
> combinations of mode transitions have been increased (16 combinations).
> Therefore optimise the amd_pstate_update_status function by implementing
> a state transition table.
> 
> There are 4 states amd_pstate supports, namely: 'disable', 'passive',
> 'active', and 'guided'.  The transition from any state to any other
> state is possible after this change. Only if the state requested matches
> with the current state then -EBUSY value is returned.
> 
> Sysfs interface:
> 
> To disable amd_pstate driver:
>   # echo disable > /sys/devices/system/cpu/amd_pstate/status
> 
> To enable passive mode:
>   # echo passive > /sys/devices/system/cpu/amd_pstate/status
> 
> To change mode to active:
>   # echo active > /sys/devices/system/cpu/amd_pstate/status
> 
> To change mode to guided:
>   # echo guided > /sys/devices/system/cpu/amd_pstate/status
> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
> ---
>   drivers/cpufreq/amd-pstate.c | 144 ++++++++++++++++++++++++++---------
>   1 file changed, 109 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 20d78dad712d..4a2b559fd712 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -65,6 +65,8 @@ static struct cpufreq_driver amd_pstate_epp_driver;
>   static int cppc_state = AMD_PSTATE_DISABLE;
>   struct kobject *amd_pstate_kobj;
>   
> +typedef int (*cppc_mode_transition_fn)(int);
> +
>   static inline int get_mode_idx_from_str(const char *str, size_t size)
>   {
>   	int i;
> @@ -806,55 +808,127 @@ static ssize_t amd_pstate_show_status(char *buf)
>   
>   static void amd_pstate_driver_cleanup(void)
>   {
> +	amd_pstate_enable(false);
> +	cppc_state = AMD_PSTATE_DISABLE;
>   	default_pstate_driver = NULL;
>   }
>   
> -static int amd_pstate_update_status(const char *buf, size_t size)
> +static int amd_pstate_register_driver(int mode)
>   {
>   	int ret;
> -	int mode_idx;
>   
> -	if (size > 7 || size < 3)
> +	if (mode == AMD_PSTATE_PASSIVE || mode == AMD_PSTATE_GUIDED)
> +		default_pstate_driver = &amd_pstate_driver;
> +	else if (mode == AMD_PSTATE_ACTIVE)
> +		default_pstate_driver = &amd_pstate_epp_driver;
> +	else
>   		return -EINVAL;
> -	mode_idx = get_mode_idx_from_str(buf, size);
>   
> -	switch(mode_idx) {
> -	case AMD_PSTATE_DISABLE:
> -		if (!default_pstate_driver)
> -			return -EINVAL;
> -		if (cppc_state == AMD_PSTATE_ACTIVE)
> -			return -EBUSY;
> -		ret = cpufreq_unregister_driver(default_pstate_driver);
> +	ret = cpufreq_register_driver(default_pstate_driver);
> +	if (ret) {
>   		amd_pstate_driver_cleanup();
> -		break;
> -	case AMD_PSTATE_PASSIVE:
> -		if (default_pstate_driver) {
> -			if (default_pstate_driver == &amd_pstate_driver)
> -				return 0;
> -			cpufreq_unregister_driver(default_pstate_driver);
> -			cppc_state = AMD_PSTATE_PASSIVE;
> -			default_pstate_driver = &amd_pstate_driver;
> -		}
> +		return ret;
> +	}
>   
> -		ret = cpufreq_register_driver(default_pstate_driver);
> -		break;
> -	case AMD_PSTATE_ACTIVE:
> -		if (default_pstate_driver) {
> -			if (default_pstate_driver == &amd_pstate_epp_driver)
> -				return 0;
> -			cpufreq_unregister_driver(default_pstate_driver);
> -			default_pstate_driver = &amd_pstate_epp_driver;
> -			cppc_state = AMD_PSTATE_ACTIVE;
> +	cppc_state = mode;
> +	return 0;
> +}
> +
> +static int amd_pstate_unregister_driver(int dummy)
> +{
> +	int ret;
> +
> +	ret = cpufreq_unregister_driver(default_pstate_driver);
> +
> +	if (ret)
> +		return ret;
> +
> +	amd_pstate_driver_cleanup();
> +	return 0;
> +}
> +
> +static void amd_pstate_change_mode_without_dvr_change(int mode)
> +{
> +	int cpu = 0;
> +
> +	cppc_state = mode;
> +	if (!boot_cpu_has(X86_FEATURE_CPPC)) {

You can save some indentation by inverting the check and calling "return".

> +		if (cppc_state == AMD_PSTATE_PASSIVE) {
> +			for_each_present_cpu(cpu) {
> +				cppc_set_auto_sel(cpu, 0);
> +			}
> +		} else if (cppc_state == AMD_PSTATE_GUIDED) {
> +				for_each_present_cpu(cpu) {
> +					cppc_set_auto_sel(cpu, 1);
> +				}
>   		}
> +	}
> +}
>   
> -		ret = cpufreq_register_driver(default_pstate_driver);
> -		break;
> -	default:
> -		break;
> -		ret = -EINVAL;
> +static int amd_pstate_change_driver_mode(int mode)
> +{
> +	int ret;
> +
> +	if ((mode == AMD_PSTATE_GUIDED && cppc_state == AMD_PSTATE_PASSIVE) ||
> +			(mode == AMD_PSTATE_PASSIVE && cppc_state == AMD_PSTATE_GUIDED)) {
> +		amd_pstate_change_mode_without_dvr_change(mode);
> +		return 0;

This feels like you're duplicating your logic of your mode transition 
table.  How about having the mode transition table call the function for 
changing modes without a driver change directly instead for those cases?

>   	}
>   
> -	return ret;
> +	ret = amd_pstate_unregister_driver(0);
> +	if (ret)
> +		return ret;
> +
> +	ret = amd_pstate_register_driver(mode);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/* Mode transition table */
> +cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = {
> +	[AMD_PSTATE_DISABLE]         = {
> +		[AMD_PSTATE_DISABLE]     = NULL,
> +		[AMD_PSTATE_PASSIVE]     = amd_pstate_register_driver,
> +		[AMD_PSTATE_ACTIVE]      = amd_pstate_register_driver,
> +		[AMD_PSTATE_GUIDED]      = amd_pstate_register_driver,
> +	},
> +	[AMD_PSTATE_PASSIVE]         = {
> +		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
> +		[AMD_PSTATE_PASSIVE]     = NULL,
> +		[AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
> +		[AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
> +	},
> +	[AMD_PSTATE_ACTIVE]          = {
> +		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
> +		[AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
> +		[AMD_PSTATE_ACTIVE]      = NULL,
> +		[AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
> +	},
> +	[AMD_PSTATE_GUIDED]          = {
> +		[AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
> +		[AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
> +		[AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
> +		[AMD_PSTATE_GUIDED]      = NULL,
> +	},
> +};
> +
> +static int amd_pstate_update_status(const char *buf, size_t size)
> +{
> +	int mode_idx;
> +
> +	if (size > 7 || size < 3)
> +		return -EINVAL;

The compiler typically inlines strlen.  Perhaps to make this more 
obvious what these boundaries are maybe do this:

size > strlen("passive") || size < strlen("off")

> +	mode_idx = get_mode_idx_from_str(buf, size);
> +
> +	if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX)
> +		return -EINVAL;
> +
> +	if (mode_state_machine[cppc_state][mode_idx])
> +		return mode_state_machine[cppc_state][mode_idx](mode_idx);
> +
> +	return -EBUSY;
>   }
>   
>   static ssize_t show_status(struct kobject *kobj,

Re: [PATCH v2 6/6] Documentation: amd_pstate: Update amd_pstate status sysfs for guided

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
> Update amd_pstate status sysfs for guided mode.
> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
> ---
>   Documentation/admin-guide/pm/amd-pstate.rst | 29 ++++++++++++++++-----
>   1 file changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
> index 55396981266a..92fa22e45a2b 100644
> --- a/Documentation/admin-guide/pm/amd-pstate.rst
> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> @@ -303,13 +303,16 @@ efficiency frequency management method on AMD processors.
>   AMD Pstate Driver Operation Modes
>   =================================
>   
> -``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and
> -CPPC non-autonomous(passive) mode.
> -active mode and passive mode can be chosen by different kernel parameters.
> -When in Autonomous mode, CPPC ignores requests done in the Desired Performance
> -Target register and takes into account only the values set to the Minimum requested
> -performance, Maximum requested performance, and Energy Performance Preference
> -registers. When Autonomous is disabled, it only considers the Desired Performance Target.
> +``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, guided
> +autonomous (guided) mode and non-autonomous (passive) mode.
> +Active/passive/guided mode can be chosen by different kernel parameters. In
> +autonomous mode, platform ignores the desired performance level request and
> +takes into account only the values set to the Minimum requested performance,
> +Maximum requested performance and Energy Performance Preference registers. In
> +non-autonomous mode, platform gets desired performance level from OS directly
> +through Desired Performance Register. In guided-autonomous mode, platform sets
> +operating performance level autonomously according to the current workload and
> +within the limits set by OS through min and max performance registers.

Your intro and explanation go in different orders.  Also this reads very 
dense.  Maybe it would make sense to put some whitespace between each mode?

>   
>   Active Mode
>   ------------
> @@ -338,6 +341,15 @@ to the Performance Reduction Tolerance register. Above the nominal performance l
>   processor must provide at least nominal performance requested and go higher if current
>   operating conditions allow.
>   
> +Guided Mode
> +-----------
> +
> +``amd_pstate=guided``
> +
> +If ``amd_pstate=guided`` is passed to kernel command line option then this mode
> +is activated.  In this mode, driver requests minimum and maximum performance
> +level and the platform autonomously selects a performance level in this range
> +and appropriate to the current workload.
>   
>   User Space Interface in ``sysfs``
>   =================================
> @@ -358,6 +370,9 @@ control its functionality at the system level.  They are located in the
>   	"passive"
>   		The driver is functional and in the ``passive mode``
>   
> +        "guided"
> +                The driver is functional and in the ``guided mode``
> +
>   	"disable"
>   		The driver is unregistered and not functional now.
>   

Re: [PATCH v2 2/6] acpi: cppc: Add auto select register read/write support

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
> For some shared memory based systems, the autonomous selection bit

For some "AMD" shared memory systems.

> needed to be set explicitly. Add autonomous selection register related
> APIs to acpi driver, which amd_pstate driver uses later.
> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>

> ---
>   drivers/acpi/cppc_acpi.c | 97 ++++++++++++++++++++++++++++++++++++++++
>   include/acpi/cppc_acpi.h | 11 +++++
>   2 files changed, 108 insertions(+)
> 
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index c936ff503965..e47b2cfe022e 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -1432,6 +1432,103 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
>   }
>   EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
>   
> +/*
> + * cppc_get_auto_sel_caps - Read autonomous selection register.
> + * @cpunum : CPU from which to read register.
> + * @perf_caps : struct where autonomous selection register value is updated.
> + */
> +int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> +	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> +	struct cpc_register_resource *auto_sel_reg;
> +	u64  auto_sel;
> +
> +	if (!cpc_desc) {
> +		pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
> +		return -ENODEV;
> +	}
> +
> +	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> +
> +	if (!CPC_SUPPORTED(auto_sel_reg))
> +		pr_warn_once("Autonomous mode is not unsupported!\n");
> +
> +	if (CPC_IN_PCC(auto_sel_reg)) {
> +		int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> +		struct cppc_pcc_data *pcc_ss_data = NULL;
> +		int ret = 0;
> +
> +		if (pcc_ss_id < 0)
> +			return -ENODEV;
> +
> +		pcc_ss_data = pcc_data[pcc_ss_id];
> +
> +		down_write(&pcc_ss_data->pcc_lock);
> +
> +		if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> +			cpc_read(cpunum, auto_sel_reg, &auto_sel);
> +			perf_caps->auto_sel = (bool)auto_sel;
> +		} else {
> +			ret = -EIO;
> +		}
> +
> +		up_write(&pcc_ss_data->pcc_lock);
> +
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
> +
> +/*
> + * cppc_set_auto_sel - Write autonomous selection register.
> + * @cpunum : CPU to which to write register.
> + * @enable : the desired value of autonomous selection resiter to be updated.
> + */
> +int cppc_set_auto_sel(int cpu, bool enable)
> +{
> +	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> +	struct cpc_register_resource *auto_sel_reg;
> +	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> +	struct cppc_pcc_data *pcc_ss_data = NULL;
> +	int ret = -EINVAL;
> +
> +	if (!cpc_desc) {
> +		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
> +		return -ENODEV;
> +	}
> +
> +	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> +
> +	if (CPC_IN_PCC(auto_sel_reg)) {
> +		if (pcc_ss_id < 0) {
> +			pr_debug("Invalid pcc_ss_id\n");
> +			return -ENODEV;
> +		}
> +
> +		if (CPC_SUPPORTED(auto_sel_reg)) {
> +			ret = cpc_write(cpu, auto_sel_reg, enable);
> +			if (ret)
> +				return ret;
> +		}
> +
> +		pcc_ss_data = pcc_data[pcc_ss_id];
> +
> +		down_write(&pcc_ss_data->pcc_lock);
> +		/* after writing CPC, transfer the ownership of PCC to platform */
> +		ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> +		up_write(&pcc_ss_data->pcc_lock);
> +	} else {
> +		ret = -ENOTSUPP;
> +		pr_debug("_CPC in PCC is not supported\n");
> +	}
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
> +
> +
>   /**
>    * cppc_set_enable - Set to enable CPPC on the processor by writing the
>    * Continuous Performance Control package EnableRegister field.
> diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> index 6b487a5bd638..6126c977ece0 100644
> --- a/include/acpi/cppc_acpi.h
> +++ b/include/acpi/cppc_acpi.h
> @@ -109,6 +109,7 @@ struct cppc_perf_caps {
>   	u32 lowest_freq;
>   	u32 nominal_freq;
>   	u32 energy_perf;
> +	bool auto_sel;
>   };
>   
>   struct cppc_perf_ctrls {
> @@ -153,6 +154,8 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
>   extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
>   extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf);
>   extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable);
> +extern int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> +extern int cppc_set_auto_sel(int cpu, bool enable);
>   #else /* !CONFIG_ACPI_CPPC_LIB */
>   static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
>   {
> @@ -214,6 +217,14 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
>   {
>   	return -ENOTSUPP;
>   }
> +static inline int cppc_set_auto_sel(int cpu, bool enable)
> +{
> +	return -ENOTSUPP;
> +}
> +static inline int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> +	return -ENOTSUPP;
> +}
>   #endif /* !CONFIG_ACPI_CPPC_LIB */
>   
>   #endif /* _CPPC_ACPI_H*/

Re: [PATCH v2 3/6] cpufreq: amd_pstate: Add guided autonomous mode

[Mario Limonciello]

On 1/12/23 23:21, Wyes Karny wrote:
>  From ACPI spec below 3 modes for CPPC can be defined:
> 1. Non autonomous: OS scaling governor specifies operating frequency/
>     performance level through `Desired Performance` register and platform
> follows that.
> 2. Guided autonomous: OS scaling governor specifies min and max
>     frequencies/ performance levels through `Minimum Performance` and
> `Maximum Performance` register, and platform can autonomously select an
> operating frequency in this range.
> 3. Fully autonomous: OS only hints (via EPP) to platform for the required
>     energy performance preference for the workload and platform autonomously
> scales the frequency.
> 
> Currently (1) is supported by amd_pstate as passive mode, and (3) is
> implemented by EPP support. This change is to support (2).
> 
> In guided autonomous mode the min_perf is based on the input from the
> scaling governor. For example, in case of schedutil this value depends
> on the current utilization. And max_perf is set to max capacity.
> 
> To activate guided auto mode ``amd_pstate=guided`` command line
> parameter has to be passed in the kernel.
> 
> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
> ---
>   .../admin-guide/kernel-parameters.txt         | 15 ++++++----
>   drivers/cpufreq/amd-pstate.c                  | 29 ++++++++++++++++---
>   include/linux/amd-pstate.h                    |  2 ++
>   3 files changed, 37 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index e3618dfdb36a..0d8486325c9a 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -7015,11 +7015,11 @@
>   			  Do not enable amd_pstate as the default
>   			  scaling driver for the supported processors
>   			passive
> -			  Use amd_pstate as a scaling driver, driver requests a
> -			  desired performance on this abstract scale and the power
> -			  management firmware translates the requests into actual
> -			  hardware states (core frequency, data fabric and memory
> -			  clocks etc.)
> +			  Use amd_pstate with passive mode as a scaling driver.
> +			  In this mode autonomous selection is disabled.
> +			  Driver requests a desired performance level and platform
> +			  tires to match the same performance level (if it is
> +			  satisfied by guaranteed performance level).
>   			active
>   			  Use amd_pstate_epp driver instance as the scaling driver,
>   			  driver provides a hint to the hardware if software wants
> @@ -7027,3 +7027,8 @@
>   			  to the CPPC firmware. then CPPC power algorithm will
>   			  calculate the runtime workload and adjust the realtime cores
>   			  frequency.
> +			guided
> +			  Activate guided autonomous mode. Driver requests minimum and
> +			  maximum performance level and the platform autonomously
> +			  selects a performance level in this range and appropriate
> +			  to the current workload.
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 87450413cf45..20d78dad712d 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -267,6 +267,20 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
>   		   cppc_perf.lowest_nonlinear_perf);
>   	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
>   
> +	ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf);
> +	if (ret) {
> +		pr_warn("failed to get auto_sel\n");

To make debugging easier in the future perhaps:

pr_warn("failed to get auto sel: %d\n", ret);

> +		return 0;
> +	}
> +
> +	if (cppc_state == AMD_PSTATE_PASSIVE)
> +		ret = cppc_set_auto_sel(cpudata->cpu, 0);
> +	else if (cppc_state == AMD_PSTATE_GUIDED)
> +		ret = cppc_set_auto_sel(cpudata->cpu, 1);
> +

as a simplification maybe:

ret = cppc_set_auto_sel(cpudata->cpu, cppc_state == AMD_PSTATE_PASSIVE ? 
0 : 1);

> +	if (ret)
> +		pr_warn("failed to set auto_sel\n");

Again, probably good to emit the error code in this message;
> +
>   	return 0;

As this could fail now shouldn't you be returning ret?

>   }
>   
> @@ -344,12 +358,18 @@ static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
>   }
>   
>   static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
> -			      u32 des_perf, u32 max_perf, bool fast_switch)
> +			      u32 des_perf, u32 max_perf, bool fast_switch, int guv_flags)
>   {
>   	u64 prev = READ_ONCE(cpudata->cppc_req_cached);
>   	u64 value = prev;
>   
>   	des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
> +
> +	if ((cppc_state == AMD_PSTATE_GUIDED) && (guv_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) {
> +		min_perf = des_perf;
> +		des_perf = 0;
> +	}
> +
>   	value &= ~AMD_CPPC_MIN_PERF(~0L);
>   	value |= AMD_CPPC_MIN_PERF(min_perf);
>   
> @@ -404,7 +424,7 @@ static int amd_pstate_target(struct cpufreq_policy *policy,
>   
>   	cpufreq_freq_transition_begin(policy, &freqs);
>   	amd_pstate_update(cpudata, min_perf, des_perf,
> -			  max_perf, false);
> +			  max_perf, false, policy->governor->flags);
>   	cpufreq_freq_transition_end(policy, &freqs, false);
>   
>   	return 0;
> @@ -438,7 +458,8 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
>   	if (max_perf < min_perf)
>   		max_perf = min_perf;
>   
> -	amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true);
> +	amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true,
> +			policy->governor->flags);
>   	cpufreq_cpu_put(policy);
>   }
>   
> @@ -1233,7 +1254,7 @@ static int __init amd_pstate_init(void)
>   	/* capability check */
>   	if (boot_cpu_has(X86_FEATURE_CPPC)) {
>   		pr_debug("AMD CPPC MSR based functionality is supported\n");
> -		if (cppc_state == AMD_PSTATE_PASSIVE)
> +		if (cppc_state != AMD_PSTATE_ACTIVE)
>   			default_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
>   	} else {
>   		pr_debug("AMD CPPC shared memory based functionality is supported\n");
> diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
> index 15761a581e82..e07cfbd63560 100644
> --- a/include/linux/amd-pstate.h
> +++ b/include/linux/amd-pstate.h
> @@ -92,6 +92,7 @@ enum amd_pstate_mode {
>   	AMD_PSTATE_DISABLE = 0,
>   	AMD_PSTATE_PASSIVE,
>   	AMD_PSTATE_ACTIVE,
> +	AMD_PSTATE_GUIDED,
>   	AMD_PSTATE_MAX,
>   };
>   
> @@ -99,6 +100,7 @@ static const char * const amd_pstate_mode_string[] = {
>   	[AMD_PSTATE_DISABLE]     = "disable",
>   	[AMD_PSTATE_PASSIVE]     = "passive",
>   	[AMD_PSTATE_ACTIVE]      = "active",
> +	[AMD_PSTATE_GUIDED]      = "guided",
>   	NULL,
>   };
>   

Re: [PATCH v2 1/6] acpi: cppc: Add min and max perf reg writing support

[Wyes Karny]

Hi Mario,

On 1/13/2023 11:07 AM, Mario Limonciello wrote:
> On 1/12/23 23:21, Wyes Karny wrote:
>> Currently writing of min and max perf register is deferred in
>> cppc_set_perf function. In CPPC guided mode, these registers needed to
>> be written to guide PMFW about min and max perf levels. Add this support
> 
> This is generic code, so  I think rather than PMFW you should just say "the platform".
> 
>> to make guided mode work properly on shared memory systems.
> 
> on AMD shared memory systems.
> 
>>
>> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
> 
> With the commit message cleaned up:
> 
> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>

Will do the cleanup part. Thanks for reviewing!

>> ---
>>   drivers/acpi/cppc_acpi.c | 16 ++++++++--------
>>   1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
>> index 02d83c807271..c936ff503965 100644
>> --- a/drivers/acpi/cppc_acpi.c
>> +++ b/drivers/acpi/cppc_acpi.c
>> @@ -1487,7 +1487,7 @@ EXPORT_SYMBOL_GPL(cppc_set_enable);
>>   int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>>   {
>>       struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
>> -    struct cpc_register_resource *desired_reg;
>> +    struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
>>       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
>>       struct cppc_pcc_data *pcc_ss_data = NULL;
>>       int ret = 0;
>> @@ -1498,6 +1498,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>>       }
>>         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
>> +    min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
>> +    max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
>>         /*
>>        * This is Phase-I where we want to write to CPC registers
>> @@ -1506,7 +1508,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>>        * Since read_lock can be acquired by multiple CPUs simultaneously we
>>        * achieve that goal here
>>        */
>> -    if (CPC_IN_PCC(desired_reg)) {
>> +    if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
>>           if (pcc_ss_id < 0) {
>>               pr_debug("Invalid pcc_ss_id\n");
>>               return -ENODEV;
>> @@ -1529,13 +1531,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>>           cpc_desc->write_cmd_status = 0;
>>       }
>>   -    /*
>> -     * Skip writing MIN/MAX until Linux knows how to come up with
>> -     * useful values.
>> -     */
>>       cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
>> +    cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
>> +    cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
>>   -    if (CPC_IN_PCC(desired_reg))
>> +    if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
>>           up_read(&pcc_ss_data->pcc_lock);    /* END Phase-I */
>>       /*
>>        * This is Phase-II where we transfer the ownership of PCC to Platform
>> @@ -1583,7 +1583,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
>>        * case during a CMD_READ and if there are pending writes it delivers
>>        * the write command before servicing the read command
>>        */
>> -    if (CPC_IN_PCC(desired_reg)) {
>> +    if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
>>           if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
>>               /* Update only if there are pending write commands */
>>               if (pcc_ss_data->pending_pcc_write_cmd)
> 

-- 
Thanks & Regards,
Wyes

Re: [PATCH v2 5/6] cpufreq: amd_pstate: Add guided mode control support via sysfs

[Wyes Karny]

On 1/13/2023 11:18 AM, Mario Limonciello wrote:
> On 1/12/23 23:21, Wyes Karny wrote:
>> amd_pstate driver's `status` sysfs entry helps to control the driver's
>> mode dynamically by user. After the addition of guided mode the
>> combinations of mode transitions have been increased (16 combinations).
>> Therefore optimise the amd_pstate_update_status function by implementing
>> a state transition table.
>>
>> There are 4 states amd_pstate supports, namely: 'disable', 'passive',
>> 'active', and 'guided'.  The transition from any state to any other
>> state is possible after this change. Only if the state requested matches
>> with the current state then -EBUSY value is returned.
>>
>> Sysfs interface:
>>
>> To disable amd_pstate driver:
>>   # echo disable > /sys/devices/system/cpu/amd_pstate/status
>>
>> To enable passive mode:
>>   # echo passive > /sys/devices/system/cpu/amd_pstate/status
>>
>> To change mode to active:
>>   # echo active > /sys/devices/system/cpu/amd_pstate/status
>>
>> To change mode to guided:
>>   # echo guided > /sys/devices/system/cpu/amd_pstate/status
>>
>> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
>> ---
>>   drivers/cpufreq/amd-pstate.c | 144 ++++++++++++++++++++++++++---------
>>   1 file changed, 109 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
>> index 20d78dad712d..4a2b559fd712 100644
>> --- a/drivers/cpufreq/amd-pstate.c
>> +++ b/drivers/cpufreq/amd-pstate.c
>> @@ -65,6 +65,8 @@ static struct cpufreq_driver amd_pstate_epp_driver;
>>   static int cppc_state = AMD_PSTATE_DISABLE;
>>   struct kobject *amd_pstate_kobj;
>>   +typedef int (*cppc_mode_transition_fn)(int);
>> +
>>   static inline int get_mode_idx_from_str(const char *str, size_t size)
>>   {
>>       int i;
>> @@ -806,55 +808,127 @@ static ssize_t amd_pstate_show_status(char *buf)
>>     static void amd_pstate_driver_cleanup(void)
>>   {
>> +    amd_pstate_enable(false);
>> +    cppc_state = AMD_PSTATE_DISABLE;
>>       default_pstate_driver = NULL;
>>   }
>>   -static int amd_pstate_update_status(const char *buf, size_t size)
>> +static int amd_pstate_register_driver(int mode)
>>   {
>>       int ret;
>> -    int mode_idx;
>>   -    if (size > 7 || size < 3)
>> +    if (mode == AMD_PSTATE_PASSIVE || mode == AMD_PSTATE_GUIDED)
>> +        default_pstate_driver = &amd_pstate_driver;
>> +    else if (mode == AMD_PSTATE_ACTIVE)
>> +        default_pstate_driver = &amd_pstate_epp_driver;
>> +    else
>>           return -EINVAL;
>> -    mode_idx = get_mode_idx_from_str(buf, size);
>>   -    switch(mode_idx) {
>> -    case AMD_PSTATE_DISABLE:
>> -        if (!default_pstate_driver)
>> -            return -EINVAL;
>> -        if (cppc_state == AMD_PSTATE_ACTIVE)
>> -            return -EBUSY;
>> -        ret = cpufreq_unregister_driver(default_pstate_driver);
>> +    ret = cpufreq_register_driver(default_pstate_driver);
>> +    if (ret) {
>>           amd_pstate_driver_cleanup();
>> -        break;
>> -    case AMD_PSTATE_PASSIVE:
>> -        if (default_pstate_driver) {
>> -            if (default_pstate_driver == &amd_pstate_driver)
>> -                return 0;
>> -            cpufreq_unregister_driver(default_pstate_driver);
>> -            cppc_state = AMD_PSTATE_PASSIVE;
>> -            default_pstate_driver = &amd_pstate_driver;
>> -        }
>> +        return ret;
>> +    }
>>   -        ret = cpufreq_register_driver(default_pstate_driver);
>> -        break;
>> -    case AMD_PSTATE_ACTIVE:
>> -        if (default_pstate_driver) {
>> -            if (default_pstate_driver == &amd_pstate_epp_driver)
>> -                return 0;
>> -            cpufreq_unregister_driver(default_pstate_driver);
>> -            default_pstate_driver = &amd_pstate_epp_driver;
>> -            cppc_state = AMD_PSTATE_ACTIVE;
>> +    cppc_state = mode;
>> +    return 0;
>> +}
>> +
>> +static int amd_pstate_unregister_driver(int dummy)
>> +{
>> +    int ret;
>> +
>> +    ret = cpufreq_unregister_driver(default_pstate_driver);
>> +
>> +    if (ret)
>> +        return ret;
>> +
>> +    amd_pstate_driver_cleanup();
>> +    return 0;
>> +}
>> +
>> +static void amd_pstate_change_mode_without_dvr_change(int mode)
>> +{
>> +    int cpu = 0;
>> +
>> +    cppc_state = mode;
>> +    if (!boot_cpu_has(X86_FEATURE_CPPC)) {
> 
> You can save some indentation by inverting the check and calling "return

Makes sense. Thanks!
> 
>> +        if (cppc_state == AMD_PSTATE_PASSIVE) {
>> +            for_each_present_cpu(cpu) {
>> +                cppc_set_auto_sel(cpu, 0);
>> +            }
>> +        } else if (cppc_state == AMD_PSTATE_GUIDED) {
>> +                for_each_present_cpu(cpu) {
>> +                    cppc_set_auto_sel(cpu, 1);
>> +                }
>>           }
>> +    }
>> +}
>>   -        ret = cpufreq_register_driver(default_pstate_driver);
>> -        break;
>> -    default:
>> -        break;
>> -        ret = -EINVAL;
>> +static int amd_pstate_change_driver_mode(int mode)
>> +{
>> +    int ret;
>> +
>> +    if ((mode == AMD_PSTATE_GUIDED && cppc_state == AMD_PSTATE_PASSIVE) ||
>> +            (mode == AMD_PSTATE_PASSIVE && cppc_state == AMD_PSTATE_GUIDED)) {
>> +        amd_pstate_change_mode_without_dvr_change(mode);
>> +        return 0;
> 
> This feels like you're duplicating your logic of your mode transition table.  How about having the mode transition table call the function for changing modes without a driver change directly instead for those cases?

Makes sense. Will add this in the table.
> 
>>       }
>>   -    return ret;
>> +    ret = amd_pstate_unregister_driver(0);
>> +    if (ret)
>> +        return ret;
>> +
>> +    ret = amd_pstate_register_driver(mode);
>> +    if (ret)
>> +        return ret;
>> +
>> +    return 0;
>> +}
>> +
>> +/* Mode transition table */
>> +cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = {
>> +    [AMD_PSTATE_DISABLE]         = {
>> +        [AMD_PSTATE_DISABLE]     = NULL,
>> +        [AMD_PSTATE_PASSIVE]     = amd_pstate_register_driver,
>> +        [AMD_PSTATE_ACTIVE]      = amd_pstate_register_driver,
>> +        [AMD_PSTATE_GUIDED]      = amd_pstate_register_driver,
>> +    },
>> +    [AMD_PSTATE_PASSIVE]         = {
>> +        [AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
>> +        [AMD_PSTATE_PASSIVE]     = NULL,
>> +        [AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
>> +        [AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
>> +    },
>> +    [AMD_PSTATE_ACTIVE]          = {
>> +        [AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
>> +        [AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
>> +        [AMD_PSTATE_ACTIVE]      = NULL,
>> +        [AMD_PSTATE_GUIDED]      = amd_pstate_change_driver_mode,
>> +    },
>> +    [AMD_PSTATE_GUIDED]          = {
>> +        [AMD_PSTATE_DISABLE]     = amd_pstate_unregister_driver,
>> +        [AMD_PSTATE_PASSIVE]     = amd_pstate_change_driver_mode,
>> +        [AMD_PSTATE_ACTIVE]      = amd_pstate_change_driver_mode,
>> +        [AMD_PSTATE_GUIDED]      = NULL,
>> +    },
>> +};
>> +
>> +static int amd_pstate_update_status(const char *buf, size_t size)
>> +{
>> +    int mode_idx;
>> +
>> +    if (size > 7 || size < 3)
>> +        return -EINVAL;
> 
> The compiler typically inlines strlen.  Perhaps to make this more obvious what these boundaries are maybe do this:
> 
> size > strlen("passive") || size < strlen("off")
> 
>> +    mode_idx = get_mode_idx_from_str(buf, size);
>> +
>> +    if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX)
>> +        return -EINVAL;
>> +
>> +    if (mode_state_machine[cppc_state][mode_idx])
>> +        return mode_state_machine[cppc_state][mode_idx](mode_idx);
>> +
>> +    return -EBUSY;
>>   }
>>     static ssize_t show_status(struct kobject *kobj,
> 

-- 
Thanks & Regards,
Wyes

Re: [PATCH v2 6/6] Documentation: amd_pstate: Update amd_pstate status sysfs for guided

[Wyes Karny]

On 1/13/2023 11:20 AM, Mario Limonciello wrote:
> On 1/12/23 23:21, Wyes Karny wrote:
>> Update amd_pstate status sysfs for guided mode.
>>
>> Signed-off-by: Wyes Karny <wyes.karny@amd.com>
>> ---
>>   Documentation/admin-guide/pm/amd-pstate.rst | 29 ++++++++++++++++-----
>>   1 file changed, 22 insertions(+), 7 deletions(-)
>>
>> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
>> index 55396981266a..92fa22e45a2b 100644
>> --- a/Documentation/admin-guide/pm/amd-pstate.rst
>> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
>> @@ -303,13 +303,16 @@ efficiency frequency management method on AMD processors.
>>   AMD Pstate Driver Operation Modes
>>   =================================
>>   -``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and
>> -CPPC non-autonomous(passive) mode.
>> -active mode and passive mode can be chosen by different kernel parameters.
>> -When in Autonomous mode, CPPC ignores requests done in the Desired Performance
>> -Target register and takes into account only the values set to the Minimum requested
>> -performance, Maximum requested performance, and Energy Performance Preference
>> -registers. When Autonomous is disabled, it only considers the Desired Performance Target.
>> +``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, guided
>> +autonomous (guided) mode and non-autonomous (passive) mode.
>> +Active/passive/guided mode can be chosen by different kernel parameters. In
>> +autonomous mode, platform ignores the desired performance level request and
>> +takes into account only the values set to the Minimum requested performance,
>> +Maximum requested performance and Energy Performance Preference registers. In
>> +non-autonomous mode, platform gets desired performance level from OS directly
>> +through Desired Performance Register. In guided-autonomous mode, platform sets
>> +operating performance level autonomously according to the current workload and
>> +within the limits set by OS through min and max performance registers.
> 
> Your intro and explanation go in different orders.  Also this reads very dense.  Maybe it would make sense to put some whitespace between each mode?

Yes, will try to make this easy to read.

> 
>>     Active Mode
>>   ------------
>> @@ -338,6 +341,15 @@ to the Performance Reduction Tolerance register. Above the nominal performance l
>>   processor must provide at least nominal performance requested and go higher if current
>>   operating conditions allow.
>>   +Guided Mode
>> +-----------
>> +
>> +``amd_pstate=guided``
>> +
>> +If ``amd_pstate=guided`` is passed to kernel command line option then this mode
>> +is activated.  In this mode, driver requests minimum and maximum performance
>> +level and the platform autonomously selects a performance level in this range
>> +and appropriate to the current workload.
>>     User Space Interface in ``sysfs``
>>   =================================
>> @@ -358,6 +370,9 @@ control its functionality at the system level.  They are located in the
>>       "passive"
>>           The driver is functional and in the ``passive mode``
>>   +        "guided"
>> +                The driver is functional and in the ``guided mode``
>> +
>>       "disable"
>>           The driver is unregistered and not functional now.
>>   
> 

-- 
Thanks & Regards,
Wyes