[PATCH v1 0/3] clk: tegra: add DFLL support for Tegra 4

[PATCH v1 0/3] clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on
a ring oscillator and translates voltage changes into frequency
compensation changes needed to prevent the CPU from failing and is
essential for correct CPU frequency scaling.

Svyatoslav Ryhel (3):
  drivers: cpufreq: add Tegra 4 support
  drivers: clk: tegra: add DFLL support for Tegra 4
  ARM: tegra: Add DFLL clock support on Tegra 4

 arch/arm/boot/dts/nvidia/tegra114.dtsi     |  34 +++++++
 drivers/clk/tegra/Kconfig                  |   2 +-
 drivers/clk/tegra/clk-tegra114.c           |  30 +++++-
 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++
 drivers/clk/tegra/clk.h                    |   2 -
 drivers/cpufreq/cpufreq-dt-platdev.c       |   1 +
 drivers/cpufreq/tegra124-cpufreq.c         |   5 +-
 include/dt-bindings/reset/tegra114-car.h   |  13 +++
 8 files changed, 182 insertions(+), 9 deletions(-)
 create mode 100644 include/dt-bindings/reset/tegra114-car.h

-- 
2.43.0

[PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Svyatoslav Ryhel]

Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 drivers/cpufreq/tegra124-cpufreq.c   | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 18942bfe9c95..7d15a1224d37 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -140,6 +140,7 @@ static const struct of_device_id blocklist[] __initconst = {
 
 	{ .compatible = "nvidia,tegra20", },
 	{ .compatible = "nvidia,tegra30", },
+	{ .compatible = "nvidia,tegra114", },
 	{ .compatible = "nvidia,tegra124", },
 	{ .compatible = "nvidia,tegra210", },
 	{ .compatible = "nvidia,tegra234", },
diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
index 514146d98bca..6ff2ccc08e5e 100644
--- a/drivers/cpufreq/tegra124-cpufreq.c
+++ b/drivers/cpufreq/tegra124-cpufreq.c
@@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void)
 	int ret;
 	struct platform_device *pdev;
 
-	if (!(of_machine_is_compatible("nvidia,tegra124") ||
-		of_machine_is_compatible("nvidia,tegra210")))
+	if (!(of_machine_is_compatible("nvidia,tegra114") ||
+	      of_machine_is_compatible("nvidia,tegra124") ||
+	      of_machine_is_compatible("nvidia,tegra210")))
 		return -ENODEV;
 
 	/*
-- 
2.43.0

Re: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Thierry Reding]

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On Fri, Mar 21, 2025 at 11:55:54AM +0200, Svyatoslav Ryhel wrote:
> Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.

It might be confusing to refer to this as both Tegra 4 and Tegra114. I
think it'd be better to stick with just Tegra114. Otherwise:

Reviewed-by: Thierry Reding <treding@nvidia.com>

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Re: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Svyatoslav Ryhel]

вт, 10 черв. 2025 р. о 14:09 Thierry Reding <thierry.reding@gmail.com> пише:
>
> On Fri, Mar 21, 2025 at 11:55:54AM +0200, Svyatoslav Ryhel wrote:
> > Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.
>
> It might be confusing to refer to this as both Tegra 4 and Tegra114. I
> think it'd be better to stick with just Tegra114. Otherwise:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>

Your review applies only to this patch to to entire series?

Re: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Mikko Perttunen]

On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  drivers/cpufreq/tegra124-cpufreq.c   | 5 +++--
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> b/drivers/cpufreq/cpufreq-dt-platdev.c index 18942bfe9c95..7d15a1224d37
> 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -140,6 +140,7 @@ static const struct of_device_id blocklist[] __initconst
> = {
> 
>  	{ .compatible = "nvidia,tegra20", },
>  	{ .compatible = "nvidia,tegra30", },
> +	{ .compatible = "nvidia,tegra114", },
>  	{ .compatible = "nvidia,tegra124", },
>  	{ .compatible = "nvidia,tegra210", },
>  	{ .compatible = "nvidia,tegra234", },
> diff --git a/drivers/cpufreq/tegra124-cpufreq.c
> b/drivers/cpufreq/tegra124-cpufreq.c index 514146d98bca..6ff2ccc08e5e
> 100644
> --- a/drivers/cpufreq/tegra124-cpufreq.c
> +++ b/drivers/cpufreq/tegra124-cpufreq.c
> @@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void)
>  	int ret;
>  	struct platform_device *pdev;
> 
> -	if (!(of_machine_is_compatible("nvidia,tegra124") ||
> -		of_machine_is_compatible("nvidia,tegra210")))
> +	if (!(of_machine_is_compatible("nvidia,tegra114") ||
> +	      of_machine_is_compatible("nvidia,tegra124") ||
> +	      of_machine_is_compatible("nvidia,tegra210")))
>  		return -ENODEV;
> 
>  	/*

I also prefer using Tegra114 and Tegra124 in the commit message, perhaps with 
the marketing names in parentheses, as the chip IDs are more consistent and 
(IMO) easier to decipher than the product names.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Svyatoslav Ryhel]

пт, 22 серп. 2025 р. о 05:58 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> > Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> >  drivers/cpufreq/tegra124-cpufreq.c   | 5 +++--
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> > b/drivers/cpufreq/cpufreq-dt-platdev.c index 18942bfe9c95..7d15a1224d37
> > 100644
> > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > @@ -140,6 +140,7 @@ static const struct of_device_id blocklist[] __initconst
> > = {
> >
> >       { .compatible = "nvidia,tegra20", },
> >       { .compatible = "nvidia,tegra30", },
> > +     { .compatible = "nvidia,tegra114", },
> >       { .compatible = "nvidia,tegra124", },
> >       { .compatible = "nvidia,tegra210", },
> >       { .compatible = "nvidia,tegra234", },
> > diff --git a/drivers/cpufreq/tegra124-cpufreq.c
> > b/drivers/cpufreq/tegra124-cpufreq.c index 514146d98bca..6ff2ccc08e5e
> > 100644
> > --- a/drivers/cpufreq/tegra124-cpufreq.c
> > +++ b/drivers/cpufreq/tegra124-cpufreq.c
> > @@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void)
> >       int ret;
> >       struct platform_device *pdev;
> >
> > -     if (!(of_machine_is_compatible("nvidia,tegra124") ||
> > -             of_machine_is_compatible("nvidia,tegra210")))
> > +     if (!(of_machine_is_compatible("nvidia,tegra114") ||
> > +           of_machine_is_compatible("nvidia,tegra124") ||
> > +           of_machine_is_compatible("nvidia,tegra210")))
> >               return -ENODEV;
> >
> >       /*
>
> I also prefer using Tegra114 and Tegra124 in the commit message, perhaps with
> the marketing names in parentheses, as the chip IDs are more consistent and
> (IMO) easier to decipher than the product names.
>
> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
>

Yes, this was applied in v2 already and all other my Tegra patches,
this exact commit was already picked from v2.

Re: [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support

[Mikko Perttunen]

On Friday, August 22, 2025 2:21 PM Svyatoslav Ryhel wrote:
> пт, 22 серп. 2025 р. о 05:58 Mikko Perttunen <mperttunen@nvidia.com> пише:
> > On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> > > Tegra 4 is fully compatible with existing Tegra K1 cpufreq driver.
> > > 
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > > 
> > >  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> > >  drivers/cpufreq/tegra124-cpufreq.c   | 5 +++--
> > >  2 files changed, 4 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> > > b/drivers/cpufreq/cpufreq-dt-platdev.c index 18942bfe9c95..7d15a1224d37
> > > 100644
> > > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > > @@ -140,6 +140,7 @@ static const struct of_device_id blocklist[]
> > > __initconst = {
> > > 
> > >       { .compatible = "nvidia,tegra20", },
> > >       { .compatible = "nvidia,tegra30", },
> > > 
> > > +     { .compatible = "nvidia,tegra114", },
> > > 
> > >       { .compatible = "nvidia,tegra124", },
> > >       { .compatible = "nvidia,tegra210", },
> > >       { .compatible = "nvidia,tegra234", },
> > > 
> > > diff --git a/drivers/cpufreq/tegra124-cpufreq.c
> > > b/drivers/cpufreq/tegra124-cpufreq.c index 514146d98bca..6ff2ccc08e5e
> > > 100644
> > > --- a/drivers/cpufreq/tegra124-cpufreq.c
> > > +++ b/drivers/cpufreq/tegra124-cpufreq.c
> > > @@ -189,8 +189,9 @@ static int __init tegra_cpufreq_init(void)
> > > 
> > >       int ret;
> > >       struct platform_device *pdev;
> > > 
> > > -     if (!(of_machine_is_compatible("nvidia,tegra124") ||
> > > -             of_machine_is_compatible("nvidia,tegra210")))
> > > +     if (!(of_machine_is_compatible("nvidia,tegra114") ||
> > > +           of_machine_is_compatible("nvidia,tegra124") ||
> > > +           of_machine_is_compatible("nvidia,tegra210")))
> > > 
> > >               return -ENODEV;
> > >       
> > >       /*
> > 
> > I also prefer using Tegra114 and Tegra124 in the commit message, perhaps
> > with the marketing names in parentheses, as the chip IDs are more
> > consistent and (IMO) easier to decipher than the product names.
> > 
> > Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
> 
> Yes, this was applied in v2 already and all other my Tegra patches,
> this exact commit was already picked from v2.

Ah, sorry. Not sure how I missed that.

Mikko

[PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

Extend the Tegra124 driver to include DFLL configuration settings required
for Tegra114 compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/clk/tegra/Kconfig                  |   2 +-
 drivers/clk/tegra/clk-tegra114.c           |  30 +++++-
 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++
 drivers/clk/tegra/clk.h                    |   2 -
 include/dt-bindings/reset/tegra114-car.h   |  13 +++
 5 files changed, 144 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/reset/tegra114-car.h

diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
index 90df619dc087..62147a069606 100644
--- a/drivers/clk/tegra/Kconfig
+++ b/drivers/clk/tegra/Kconfig
@@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP
 	depends on TEGRA_BPMP
 
 config TEGRA_CLK_DFLL
-	depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
+	depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
 	select PM_OPP
 	def_bool y
 
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b19dd4e6e17c..9b6794b951a2 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -11,6 +11,7 @@
 #include <linux/export.h>
 #include <linux/clk/tegra.h>
 #include <dt-bindings/clock/tegra114-car.h>
+#include <dt-bindings/reset/tegra114-car.h>
 
 #include "clk.h"
 #include "clk-id.h"
@@ -1260,7 +1261,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
  *
  * Assert the reset line of the DFLL's DVCO.  No return value.
  */
-void tegra114_clock_assert_dfll_dvco_reset(void)
+static void tegra114_clock_assert_dfll_dvco_reset(void)
 {
 	u32 v;
 
@@ -1269,7 +1270,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void)
 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
 	tegra114_car_barrier();
 }
-EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
 
 /**
  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
@@ -1277,7 +1277,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
  * operate.  No return value.
  */
-void tegra114_clock_deassert_dfll_dvco_reset(void)
+static void tegra114_clock_deassert_dfll_dvco_reset(void)
 {
 	u32 v;
 
@@ -1286,7 +1286,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void)
 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
 	tegra114_car_barrier();
 }
-EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
+
+static int tegra114_reset_assert(unsigned long id)
+{
+	if (id == TEGRA114_RST_DFLL_DVCO)
+		tegra114_clock_assert_dfll_dvco_reset();
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+static int tegra114_reset_deassert(unsigned long id)
+{
+	if (id == TEGRA114_RST_DFLL_DVCO)
+		tegra114_clock_deassert_dfll_dvco_reset();
+	else
+		return -EINVAL;
+
+	return 0;
+}
 
 #ifdef CONFIG_TEGRA124_CLK_EMC
 static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec,
@@ -1357,6 +1376,9 @@ static void __init tegra114_clock_init(struct device_node *np)
 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
 					&pll_x_params);
 
+	tegra_init_special_resets(1, tegra114_reset_assert,
+				  tegra114_reset_deassert);
+
 #ifdef CONFIG_TEGRA124_CLK_EMC
 	tegra_add_of_provider(np, tegra114_clk_src_onecell_get);
 	clks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 0251618b82c8..7a43380ce519 100644
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -28,6 +28,99 @@ struct dfll_fcpu_data {
 	unsigned int cpu_cvb_tables_size;
 };
 
+/* Maximum CPU frequency, indexed by CPU speedo id */
+static const unsigned long tegra114_cpu_max_freq_table[] = {
+	[0] = 2040000000UL,
+	[1] = 1810500000UL,
+	[2] = 1912500000UL,
+	[3] = 1810500000UL,
+};
+
+#define T114_CPU_CVB_TABLE \
+	.min_millivolts = 1000, \
+	.max_millivolts = 1320, \
+	.speedo_scale = 100,    \
+	.voltage_scale = 1000,  \
+	.entries = {            \
+		{  306000000UL, { 2190643, -141851, 3576 } }, \
+		{  408000000UL, { 2250968, -144331, 3576 } }, \
+		{  510000000UL, { 2313333, -146811, 3576 } }, \
+		{  612000000UL, { 2377738, -149291, 3576 } }, \
+		{  714000000UL, { 2444183, -151771, 3576 } }, \
+		{  816000000UL, { 2512669, -154251, 3576 } }, \
+		{  918000000UL, { 2583194, -156731, 3576 } }, \
+		{ 1020000000UL, { 2655759, -159211, 3576 } }, \
+		{ 1122000000UL, { 2730365, -161691, 3576 } }, \
+		{ 1224000000UL, { 2807010, -164171, 3576 } }, \
+		{ 1326000000UL, { 2885696, -166651, 3576 } }, \
+		{ 1428000000UL, { 2966422, -169131, 3576 } }, \
+		{ 1530000000UL, { 3049183, -171601, 3576 } }, \
+		{ 1606500000UL, { 3112179, -173451, 3576 } }, \
+		{ 1708500000UL, { 3198504, -175931, 3576 } }, \
+		{ 1810500000UL, { 3304747, -179126, 3576 } }, \
+		{ 1912500000UL, { 3395401, -181606, 3576 } }, \
+		{          0UL, {       0,       0,    0 } }, \
+	}, \
+	.cpu_dfll_data = {      \
+		.tune0_low = 0x00b0039d,          \
+		.tune0_high = 0x00b0009d,         \
+		.tune1 = 0x0000001f,              \
+		.tune_high_min_millivolts = 1050, \
+	}
+
+static const struct cvb_table tegra114_cpu_cvb_tables[] = {
+	{
+		.speedo_id = 0,
+		.process_id = -1,
+		.min_millivolts = 1000,
+		.max_millivolts = 1250,
+		.speedo_scale = 100,
+		.voltage_scale = 100,
+		.entries = {
+			{  306000000UL, { 107330, -1569,   0 } },
+			{  408000000UL, { 111250, -1666,   0 } },
+			{  510000000UL, { 110000, -1460,   0 } },
+			{  612000000UL, { 117290, -1745,   0 } },
+			{  714000000UL, { 122700, -1910,   0 } },
+			{  816000000UL, { 125620, -1945,   0 } },
+			{  918000000UL, { 130560, -2076,   0 } },
+			{ 1020000000UL, { 137280, -2303,   0 } },
+			{ 1122000000UL, { 146440, -2660,   0 } },
+			{ 1224000000UL, { 152190, -2825,   0 } },
+			{ 1326000000UL, { 157520, -2953,   0 } },
+			{ 1428000000UL, { 166100, -3261,   0 } },
+			{ 1530000000UL, { 176410, -3647,   0 } },
+			{ 1632000000UL, { 189620, -4186,   0 } },
+			{ 1734000000UL, { 203190, -4725,   0 } },
+			{ 1836000000UL, { 222670, -5573,   0 } },
+			{ 1938000000UL, { 256210, -7165,   0 } },
+			{ 2040000000UL, { 250050, -6544,   0 } },
+			{          0UL, {      0,     0,   0 } },
+		},
+		.cpu_dfll_data = {
+			.tune0_low = 0x00b0019d,
+			.tune0_high = 0x00b0019d,
+			.tune1 = 0x0000001f,
+			.tune_high_min_millivolts = 1000,
+		}
+	},
+	{
+		.speedo_id = 1,
+		.process_id = -1,
+		T114_CPU_CVB_TABLE
+	},
+	{
+		.speedo_id = 2,
+		.process_id = -1,
+		T114_CPU_CVB_TABLE
+	},
+	{
+		.speedo_id = 3,
+		.process_id = -1,
+		T114_CPU_CVB_TABLE
+	},
+};
+
 /* Maximum CPU frequency, indexed by CPU speedo id */
 static const unsigned long tegra124_cpu_max_freq_table[] = {
 	[0] = 2014500000UL,
@@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
 	},
 };
 
+static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = {
+	.cpu_max_freq_table = tegra114_cpu_max_freq_table,
+	.cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table),
+	.cpu_cvb_tables = tegra114_cpu_cvb_tables,
+	.cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables)
+};
+
 static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
 	.cpu_max_freq_table = tegra124_cpu_max_freq_table,
 	.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
 };
 
 static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
+	{
+		.compatible = "nvidia,tegra114-dfll",
+		.data = &tegra114_dfll_fcpu_data,
+	},
 	{
 		.compatible = "nvidia,tegra124-dfll",
 		.data = &tegra124_dfll_fcpu_data,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 5d80d8b79b8e..58e860b18e5e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -898,8 +898,6 @@ static inline bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw)
 void tegra114_clock_tune_cpu_trimmers_high(void);
 void tegra114_clock_tune_cpu_trimmers_low(void);
 void tegra114_clock_tune_cpu_trimmers_init(void);
-void tegra114_clock_assert_dfll_dvco_reset(void);
-void tegra114_clock_deassert_dfll_dvco_reset(void);
 
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
diff --git a/include/dt-bindings/reset/tegra114-car.h b/include/dt-bindings/reset/tegra114-car.h
new file mode 100644
index 000000000000..d7908d810ddf
--- /dev/null
+++ b/include/dt-bindings/reset/tegra114-car.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * This header provides Tegra114-specific constants for binding
+ * nvidia,tegra114-car.
+ */
+
+#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
+#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
+
+#define TEGRA114_RESET(x)		(5 * 32 + (x))
+#define TEGRA114_RST_DFLL_DVCO		TEGRA114_RESET(0)
+
+#endif	/* _DT_BINDINGS_RESET_TEGRA114_CAR_H */
-- 
2.43.0

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Krzysztof Kozlowski]

On 21/03/2025 10:55, Svyatoslav Ryhel wrote:
> Extend the Tegra124 driver to include DFLL configuration settings required
> for Tegra114 compatibility.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument, so you will
not CC people just because they made one commit years ago). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.
</form letter>



> +++ b/include/dt-bindings/reset/tegra114-car.h

Filename based on compatible.

> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * This header provides Tegra114-specific constants for binding
> + * nvidia,tegra114-car.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +
> +#define TEGRA114_RESET(x)		(5 * 32 + (x))


Does not look like a binding, but some sort of register. Binding IDs
start from 0 (or 1) and are incremented by 1.

Best regards,
Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

пт, 21 бер. 2025 р. о 22:50 Krzysztof Kozlowski <krzk@kernel.org> пише:
>
> On 21/03/2025 10:55, Svyatoslav Ryhel wrote:
> > Extend the Tegra124 driver to include DFLL configuration settings required
> > for Tegra114 compatibility.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
>
> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
> not CC people just because they made one commit years ago). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
>
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
> </form letter>
>
>
>
> > +++ b/include/dt-bindings/reset/tegra114-car.h
>
> Filename based on compatible.
>
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> > +/*
> > + * This header provides Tegra114-specific constants for binding
> > + * nvidia,tegra114-car.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> > +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> > +
> > +#define TEGRA114_RESET(x)            (5 * 32 + (x))
>
>
> Does not look like a binding, but some sort of register. Binding IDs
> start from 0 (or 1) and are incremented by 1.
>

Hello there!
This file add same logic for Tegra114 as Tegra124 currently
implements, check here
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5

I did not re-use Tegra124 value, though it is same, to avoid confusion
in main Tegra114 device tree.

> Best regards,
> Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Krzysztof Kozlowski]

On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>>> +/*
>>> + * This header provides Tegra114-specific constants for binding
>>> + * nvidia,tegra114-car.
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>> +
>>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
>>
>>
>> Does not look like a binding, but some sort of register. Binding IDs
>> start from 0 (or 1) and are incremented by 1.
>>
> 
> Hello there!
> This file add same logic for Tegra114 as Tegra124 currently
> implements, check here
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
> 
> I did not re-use Tegra124 value, though it is same, to avoid confusion
> in main Tegra114 device tree.

What confusion? Why would anyone be interested in comparing numbers thus
getting confused by different number? These are abstract IDs.

Best regards,
Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

нд, 4 трав. 2025 р. о 19:23 Krzysztof Kozlowski <krzk@kernel.org> пише:
>
> On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
> >>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> >>> +/*
> >>> + * This header provides Tegra114-specific constants for binding
> >>> + * nvidia,tegra114-car.
> >>> + */
> >>> +
> >>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>> +
> >>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
> >>
> >>
> >> Does not look like a binding, but some sort of register. Binding IDs
> >> start from 0 (or 1) and are incremented by 1.
> >>
> >
> > Hello there!
> > This file add same logic for Tegra114 as Tegra124 currently
> > implements, check here
> > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
> >
> > I did not re-use Tegra124 value, though it is same, to avoid confusion
> > in main Tegra114 device tree.
>
> What confusion? Why would anyone be interested in comparing numbers thus
> getting confused by different number? These are abstract IDs.
>

By using TEGRA124_RESET in Tegra114 device tree

> Best regards,
> Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Krzysztof Kozlowski]

On 04/05/2025 18:25, Svyatoslav Ryhel wrote:
> нд, 4 трав. 2025 р. о 19:23 Krzysztof Kozlowski <krzk@kernel.org> пише:
>>
>> On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
>>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>>>>> +/*
>>>>> + * This header provides Tegra114-specific constants for binding
>>>>> + * nvidia,tegra114-car.
>>>>> + */
>>>>> +
>>>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>> +
>>>>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
>>>>
>>>>
>>>> Does not look like a binding, but some sort of register. Binding IDs
>>>> start from 0 (or 1) and are incremented by 1.
>>>>
>>>
>>> Hello there!
>>> This file add same logic for Tegra114 as Tegra124 currently
>>> implements, check here
>>> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
>>>
>>> I did not re-use Tegra124 value, though it is same, to avoid confusion
>>> in main Tegra114 device tree.
>>
>> What confusion? Why would anyone be interested in comparing numbers thus
>> getting confused by different number? These are abstract IDs.
>>
> 
> By using TEGRA124_RESET in Tegra114 device tree

Why would you use define from other SoC... and how is it related to my
comment in the first place?


Best regards,
Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

нд, 4 трав. 2025 р. о 20:11 Krzysztof Kozlowski <krzk@kernel.org> пише:
>
> On 04/05/2025 18:25, Svyatoslav Ryhel wrote:
> > нд, 4 трав. 2025 р. о 19:23 Krzysztof Kozlowski <krzk@kernel.org> пише:
> >>
> >> On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
> >>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> >>>>> +/*
> >>>>> + * This header provides Tegra114-specific constants for binding
> >>>>> + * nvidia,tegra114-car.
> >>>>> + */
> >>>>> +
> >>>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>>>> +
> >>>>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
> >>>>
> >>>>
> >>>> Does not look like a binding, but some sort of register. Binding IDs
> >>>> start from 0 (or 1) and are incremented by 1.
> >>>>
> >>>
> >>> Hello there!
> >>> This file add same logic for Tegra114 as Tegra124 currently
> >>> implements, check here
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
> >>>
> >>> I did not re-use Tegra124 value, though it is same, to avoid confusion
> >>> in main Tegra114 device tree.
> >>
> >> What confusion? Why would anyone be interested in comparing numbers thus
> >> getting confused by different number? These are abstract IDs.
> >>
> >
> > By using TEGRA124_RESET in Tegra114 device tree
>
> Why would you use define from other SoC... and how is it related to my
> comment in the first place?
>

You did not even bother to check link that I have provided, did you?

You cut the actual device tree compatible definition,
TEGRA114_RESET(x) is a macro used further to define device tree
compatibles.

Like this:

#define TEGRA114_RST_DFLL_DVCO         TEGRA114_RESET(0)

>
> Best regards,
> Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Krzysztof Kozlowski]

On 04/05/2025 19:30, Svyatoslav Ryhel wrote:
> нд, 4 трав. 2025 р. о 20:11 Krzysztof Kozlowski <krzk@kernel.org> пише:
>>
>> On 04/05/2025 18:25, Svyatoslav Ryhel wrote:
>>> нд, 4 трав. 2025 р. о 19:23 Krzysztof Kozlowski <krzk@kernel.org> пише:
>>>>
>>>> On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
>>>>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>>>>>>> +/*
>>>>>>> + * This header provides Tegra114-specific constants for binding
>>>>>>> + * nvidia,tegra114-car.
>>>>>>> + */
>>>>>>> +
>>>>>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>>>> +
>>>>>>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
>>>>>>
>>>>>>
>>>>>> Does not look like a binding, but some sort of register. Binding IDs
>>>>>> start from 0 (or 1) and are incremented by 1.
>>>>>>
>>>>>
>>>>> Hello there!
>>>>> This file add same logic for Tegra114 as Tegra124 currently
>>>>> implements, check here
>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
>>>>>
>>>>> I did not re-use Tegra124 value, though it is same, to avoid confusion
>>>>> in main Tegra114 device tree.
>>>>
>>>> What confusion? Why would anyone be interested in comparing numbers thus
>>>> getting confused by different number? These are abstract IDs.
>>>>
>>>
>>> By using TEGRA124_RESET in Tegra114 device tree
>>
>> Why would you use define from other SoC... and how is it related to my
>> comment in the first place?
>>
> 
> You did not even bother to check link that I have provided, did you?

I did. I clicked it, looked the same as here. Does not help.

> 
> You cut the actual device tree compatible definition,
> TEGRA114_RESET(x) is a macro used further to define device tree
> compatibles.

There are no further users...

> 
> Like this:
> 
> #define TEGRA114_RST_DFLL_DVCO         TEGRA114_RESET(0)

and still my comment stands. Bindings start from 0 or 1.


Best regards,
Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Thierry Reding]

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On Fri, Mar 21, 2025 at 09:50:09PM +0100, Krzysztof Kozlowski wrote:
> On 21/03/2025 10:55, Svyatoslav Ryhel wrote:
> > Extend the Tegra124 driver to include DFLL configuration settings required
> > for Tegra114 compatibility.
> > 
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> 
> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
> not CC people just because they made one commit years ago). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
> 
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
> </form letter>
> 
> 
> 
> > +++ b/include/dt-bindings/reset/tegra114-car.h
> 
> Filename based on compatible.
> 
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> > +/*
> > + * This header provides Tegra114-specific constants for binding
> > + * nvidia,tegra114-car.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> > +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> > +
> > +#define TEGRA114_RESET(x)		(5 * 32 + (x))
> 
> 
> Does not look like a binding, but some sort of register. Binding IDs
> start from 0 (or 1) and are incremented by 1.

I'll try and clear up some of the confusion around this. The way that
resets are handled on these Tegra devices is that there is a set of
peripheral clocks & resets which are paired up. This is because they
are laid out in banks within the CAR (clock and reset) controller. In
most cases we're referring to those resets, so you'll often see a clock
ID used in conjection with the same reset ID for a given IP block.

In addition to those peripheral resets, there are a number of extra
resets that don't have a corresponding clock and which are exposed in
registers outside of the peripheral banks, but still part of the CAR.
To support those "special" registers, the TEGRA*_RESET() is used to
denote resets outside of the regular peripheral resets. Essentially it
defines the offset within the CAR at which special resets start. In the
above case, Tegra114 has 5 banks with 32 peripheral resets each. The
first special reset, TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0.

So to summarize: We cannot start enumerating these at 0 because that
would fall into the range of peripheral reset IDs.

Thierry

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Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Krzysztof Kozlowski]

On 10/06/2025 13:07, Thierry Reding wrote:
>>
>>> @@ -0,0 +1,13 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>>> +/*
>>> + * This header provides Tegra114-specific constants for binding
>>> + * nvidia,tegra114-car.
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>> +
>>> +#define TEGRA114_RESET(x)		(5 * 32 + (x))
>>
>>
>> Does not look like a binding, but some sort of register. Binding IDs
>> start from 0 (or 1) and are incremented by 1.
> 
> I'll try and clear up some of the confusion around this. The way that
> resets are handled on these Tegra devices is that there is a set of
> peripheral clocks & resets which are paired up. This is because they
> are laid out in banks within the CAR (clock and reset) controller. In
> most cases we're referring to those resets, so you'll often see a clock
> ID used in conjection with the same reset ID for a given IP block.
> 
> In addition to those peripheral resets, there are a number of extra
> resets that don't have a corresponding clock and which are exposed in
> registers outside of the peripheral banks, but still part of the CAR.
> To support those "special" registers, the TEGRA*_RESET() is used to
> denote resets outside of the regular peripheral resets. Essentially it
> defines the offset within the CAR at which special resets start. In the
> above case, Tegra114 has 5 banks with 32 peripheral resets each. The
> first special reset, TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0.
> 
> So to summarize: We cannot start enumerating these at 0 because that
> would fall into the range of peripheral reset IDs.

So these are hardware values, not bindings. Drop the header or move it
outside of bindings like other headers for hardware constants.

Best regards,
Krzysztof

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2564 bytes --]

On Wed, Jun 18, 2025 at 11:13:37AM +0200, Krzysztof Kozlowski wrote:
> On 10/06/2025 13:07, Thierry Reding wrote:
> >>
> >>> @@ -0,0 +1,13 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> >>> +/*
> >>> + * This header provides Tegra114-specific constants for binding
> >>> + * nvidia,tegra114-car.
> >>> + */
> >>> +
> >>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> >>> +
> >>> +#define TEGRA114_RESET(x)		(5 * 32 + (x))
> >>
> >>
> >> Does not look like a binding, but some sort of register. Binding IDs
> >> start from 0 (or 1) and are incremented by 1.
> > 
> > I'll try and clear up some of the confusion around this. The way that
> > resets are handled on these Tegra devices is that there is a set of
> > peripheral clocks & resets which are paired up. This is because they
> > are laid out in banks within the CAR (clock and reset) controller. In
> > most cases we're referring to those resets, so you'll often see a clock
> > ID used in conjection with the same reset ID for a given IP block.
> > 
> > In addition to those peripheral resets, there are a number of extra
> > resets that don't have a corresponding clock and which are exposed in
> > registers outside of the peripheral banks, but still part of the CAR.
> > To support those "special" registers, the TEGRA*_RESET() is used to
> > denote resets outside of the regular peripheral resets. Essentially it
> > defines the offset within the CAR at which special resets start. In the
> > above case, Tegra114 has 5 banks with 32 peripheral resets each. The
> > first special reset, TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0.
> > 
> > So to summarize: We cannot start enumerating these at 0 because that
> > would fall into the range of peripheral reset IDs.
> 
> So these are hardware values, not bindings. Drop the header or move it
> outside of bindings like other headers for hardware constants.

5 banks and 32 peripheral resets per bank are properties of the
hardware, yes. However, the notion of starting the enumeration of the
extra resets after those 160 resets is a binding. There's no concept
in the chip that would tie the DFLL reset to index 160.

Dropping the header altogether would mean that we need to hardcode
the value, which makes its meaning completely opaque. Besides, there are
a bunch of header files in include/dt-bindings that define symbolic
names for hardware values, and I'm not sure why you think these here
would be different.

Thierry

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Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Stephen Boyd]

Quoting Svyatoslav Ryhel (2025-03-21 02:55:55)
> Extend the Tegra124 driver to include DFLL configuration settings required
> for Tegra114 compatibility.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---

Drive by nitpick. The subject should drop "drivers: " because it's
implicit from "clk:".

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Svyatoslav Ryhel]

вт, 25 бер. 2025 р. о 20:56 Stephen Boyd <sboyd@kernel.org> пише:
>
> Quoting Svyatoslav Ryhel (2025-03-21 02:55:55)
> > Extend the Tegra124 driver to include DFLL configuration settings required
> > for Tegra114 compatibility.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
>
> Drive by nitpick. The subject should drop "drivers: " because it's
> implicit from "clk:".

If this is the only remark you have to this commit, I am happy to fix it ;)

Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4

[Mikko Perttunen]

On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> Extend the Tegra124 driver to include DFLL configuration settings required
> for Tegra114 compatibility.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/Kconfig                  |   2 +-
>  drivers/clk/tegra/clk-tegra114.c           |  30 +++++-
>  drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++
>  drivers/clk/tegra/clk.h                    |   2 -
>  include/dt-bindings/reset/tegra114-car.h   |  13 +++
>  5 files changed, 144 insertions(+), 7 deletions(-)
>  create mode 100644 include/dt-bindings/reset/tegra114-car.h
> 
> diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
> index 90df619dc087..62147a069606 100644
> --- a/drivers/clk/tegra/Kconfig
> +++ b/drivers/clk/tegra/Kconfig
> @@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP
>  	depends on TEGRA_BPMP
> 
>  config TEGRA_CLK_DFLL
> -	depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
> +	depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || 
ARCH_TEGRA_210_SOC
>  	select PM_OPP
>  	def_bool y
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c
> b/drivers/clk/tegra/clk-tegra114.c index b19dd4e6e17c..9b6794b951a2 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -11,6 +11,7 @@
>  #include <linux/export.h>
>  #include <linux/clk/tegra.h>
>  #include <dt-bindings/clock/tegra114-car.h>
> +#include <dt-bindings/reset/tegra114-car.h>
> 
>  #include "clk.h"
>  #include "clk-id.h"
> @@ -1260,7 +1261,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
>   *
>   * Assert the reset line of the DFLL's DVCO.  No return value.
>   */
> -void tegra114_clock_assert_dfll_dvco_reset(void)
> +static void tegra114_clock_assert_dfll_dvco_reset(void)
>  {
>  	u32 v;
> 
> @@ -1269,7 +1270,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void)
>  	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
>  	tegra114_car_barrier();
>  }
> -EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
> 
>  /**
>   * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
> @@ -1277,7 +1277,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
> * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to *
> operate.  No return value.
>   */
> -void tegra114_clock_deassert_dfll_dvco_reset(void)
> +static void tegra114_clock_deassert_dfll_dvco_reset(void)
>  {
>  	u32 v;
> 
> @@ -1286,7 +1286,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void)
>  	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
>  	tegra114_car_barrier();
>  }
> -EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
> +
> +static int tegra114_reset_assert(unsigned long id)
> +{
> +	if (id == TEGRA114_RST_DFLL_DVCO)
> +		tegra114_clock_assert_dfll_dvco_reset();
> +	else
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int tegra114_reset_deassert(unsigned long id)
> +{
> +	if (id == TEGRA114_RST_DFLL_DVCO)
> +		tegra114_clock_deassert_dfll_dvco_reset();
> +	else
> +		return -EINVAL;
> +
> +	return 0;
> +}
> 
>  #ifdef CONFIG_TEGRA124_CLK_EMC
>  static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args
> *clkspec, @@ -1357,6 +1376,9 @@ static void __init
> tegra114_clock_init(struct device_node *np)
> tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
>  					&pll_x_params);
> 
> +	tegra_init_special_resets(1, tegra114_reset_assert,
> +				  tegra114_reset_deassert);
> +
>  #ifdef CONFIG_TEGRA124_CLK_EMC
>  	tegra_add_of_provider(np, tegra114_clk_src_onecell_get);
>  	clks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,

Could you split this up into separate patches for the reset portion and the 
DFLL portion.

> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index
> 0251618b82c8..7a43380ce519 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -28,6 +28,99 @@ struct dfll_fcpu_data {
>  	unsigned int cpu_cvb_tables_size;
>  };
> 
> +/* Maximum CPU frequency, indexed by CPU speedo id */
> +static const unsigned long tegra114_cpu_max_freq_table[] = {
> +	[0] = 2040000000UL,
> +	[1] = 1810500000UL,
> +	[2] = 1912500000UL,
> +	[3] = 1810500000UL,
> +};
> +
> +#define T114_CPU_CVB_TABLE \
> +	.min_millivolts = 1000, \
> +	.max_millivolts = 1320, \
> +	.speedo_scale = 100,    \
> +	.voltage_scale = 1000,  \
> +	.entries = {            \
> +		{  306000000UL, { 2190643, -141851, 3576 } }, \
> +		{  408000000UL, { 2250968, -144331, 3576 } }, \
> +		{  510000000UL, { 2313333, -146811, 3576 } }, \
> +		{  612000000UL, { 2377738, -149291, 3576 } }, \
> +		{  714000000UL, { 2444183, -151771, 3576 } }, \
> +		{  816000000UL, { 2512669, -154251, 3576 } }, \
> +		{  918000000UL, { 2583194, -156731, 3576 } }, \
> +		{ 1020000000UL, { 2655759, -159211, 3576 } }, \
> +		{ 1122000000UL, { 2730365, -161691, 3576 } }, \
> +		{ 1224000000UL, { 2807010, -164171, 3576 } }, \
> +		{ 1326000000UL, { 2885696, -166651, 3576 } }, \
> +		{ 1428000000UL, { 2966422, -169131, 3576 } }, \
> +		{ 1530000000UL, { 3049183, -171601, 3576 } }, \
> +		{ 1606500000UL, { 3112179, -173451, 3576 } }, \
> +		{ 1708500000UL, { 3198504, -175931, 3576 } }, \
> +		{ 1810500000UL, { 3304747, -179126, 3576 } }, \
> +		{ 1912500000UL, { 3395401, -181606, 3576 } }, \
> +		{          0UL, {       0,       0,    0 } }, \
> +	}, \
> +	.cpu_dfll_data = {      \
> +		.tune0_low = 0x00b0039d,          \
> +		.tune0_high = 0x00b0009d,         \
> +		.tune1 = 0x0000001f,              \
> +		.tune_high_min_millivolts = 1050, \
> +	}
> +

Looks good -- could you add a T210_ prefix into the existing CVB table macro 
names to avoid any confusion later.

> +static const struct cvb_table tegra114_cpu_cvb_tables[] = {
> +	{
> +		.speedo_id = 0,
> +		.process_id = -1,
> +		.min_millivolts = 1000,
> +		.max_millivolts = 1250,
> +		.speedo_scale = 100,
> +		.voltage_scale = 100,
> +		.entries = {
> +			{  306000000UL, { 107330, -1569,   0 } },
> +			{  408000000UL, { 111250, -1666,   0 } },
> +			{  510000000UL, { 110000, -1460,   0 } },
> +			{  612000000UL, { 117290, -1745,   0 } },
> +			{  714000000UL, { 122700, -1910,   0 } },
> +			{  816000000UL, { 125620, -1945,   0 } },
> +			{  918000000UL, { 130560, -2076,   0 } },
> +			{ 1020000000UL, { 137280, -2303,   0 } },
> +			{ 1122000000UL, { 146440, -2660,   0 } },
> +			{ 1224000000UL, { 152190, -2825,   0 } },
> +			{ 1326000000UL, { 157520, -2953,   0 } },
> +			{ 1428000000UL, { 166100, -3261,   0 } },
> +			{ 1530000000UL, { 176410, -3647,   0 } },
> +			{ 1632000000UL, { 189620, -4186,   0 } },
> +			{ 1734000000UL, { 203190, -4725,   0 } },
> +			{ 1836000000UL, { 222670, -5573,   0 } },
> +			{ 1938000000UL, { 256210, -7165,   0 } },
> +			{ 2040000000UL, { 250050, -6544,   0 } },
> +			{          0UL, {      0,     0,   0 } },
> +		},
> +		.cpu_dfll_data = {
> +			.tune0_low = 0x00b0019d,
> +			.tune0_high = 0x00b0019d,
> +			.tune1 = 0x0000001f,
> +			.tune_high_min_millivolts = 1000,
> +		}
> +	},
> +	{
> +		.speedo_id = 1,
> +		.process_id = -1,
> +		T114_CPU_CVB_TABLE
> +	},
> +	{
> +		.speedo_id = 2,
> +		.process_id = -1,
> +		T114_CPU_CVB_TABLE
> +	},
> +	{
> +		.speedo_id = 3,
> +		.process_id = -1,
> +		T114_CPU_CVB_TABLE
> +	},
> +};
> +
>  /* Maximum CPU frequency, indexed by CPU speedo id */
>  static const unsigned long tegra124_cpu_max_freq_table[] = {
>  	[0] = 2014500000UL,
> @@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
>  	},
>  };
> 
> +static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = {
> +	.cpu_max_freq_table = tegra114_cpu_max_freq_table,
> +	.cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table),
> +	.cpu_cvb_tables = tegra114_cpu_cvb_tables,
> +	.cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables)
> +};
> +
>  static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
>  	.cpu_max_freq_table = tegra124_cpu_max_freq_table,
>  	.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
> @@ -509,6 +609,10 @@ static const struct dfll_fcpu_data
> tegra210_dfll_fcpu_data = { };
> 
>  static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> +	{
> +		.compatible = "nvidia,tegra114-dfll",
> +		.data = &tegra114_dfll_fcpu_data,
> +	},
>  	{
>  		.compatible = "nvidia,tegra124-dfll",
>  		.data = &tegra124_dfll_fcpu_data,
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 5d80d8b79b8e..58e860b18e5e 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -898,8 +898,6 @@ static inline bool
> tegra124_clk_emc_driver_available(struct clk_hw *emc_hw) void
> tegra114_clock_tune_cpu_trimmers_high(void);
>  void tegra114_clock_tune_cpu_trimmers_low(void);
>  void tegra114_clock_tune_cpu_trimmers_init(void);
> -void tegra114_clock_assert_dfll_dvco_reset(void);
> -void tegra114_clock_deassert_dfll_dvco_reset(void);
> 
>  typedef void (*tegra_clk_apply_init_table_func)(void);
>  extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
> diff --git a/include/dt-bindings/reset/tegra114-car.h
> b/include/dt-bindings/reset/tegra114-car.h new file mode 100644
> index 000000000000..d7908d810ddf
> --- /dev/null
> +++ b/include/dt-bindings/reset/tegra114-car.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * This header provides Tegra114-specific constants for binding
> + * nvidia,tegra114-car.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +
> +#define TEGRA114_RESET(x)		(5 * 32 + (x))
> +#define TEGRA114_RST_DFLL_DVCO		TEGRA114_RESET(0)
> +
> +#endif	/* _DT_BINDINGS_RESET_TEGRA114_CAR_H */

Bindings look fine to me, they follow existing pattern used on other chips for 
DFLL. Perhaps add a note to the commit message along the lines of 'Binding 
values for special resets are placed starting from software-defined index 160 
in line with other chips.', for extra clarity.

Thanks,
Mikko

[PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Svyatoslav Ryhel]

Add DFLL clock node to common Tegra114 device tree along with clocks
property to cpu node.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 341ec0962460..25d063a47ca5 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra114-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/tegra114-car.h>
 #include <dt-bindings/soc/tegra-pmc.h>
 
 #include "tegra114-peripherals-opp.dtsi"
@@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
 		#nvidia,mipi-calibrate-cells = <1>;
 	};
 
+	dfll: clock@70110000 {
+		compatible = "nvidia,tegra114-dfll";
+		reg = <0x70110000 0x100>, /* DFLL control */
+		      <0x70110000 0x100>, /* I2C output control */
+		      <0x70110100 0x100>, /* Integrated I2C controller */
+		      <0x70110200 0x100>; /* Look-up table RAM */
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
+			 <&tegra_car TEGRA114_CLK_DFLL_REF>,
+			 <&tegra_car TEGRA114_CLK_I2C5>;
+		clock-names = "soc", "ref", "i2c";
+		resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
+		reset-names = "dvco";
+		#clock-cells = <0>;
+		clock-output-names = "dfllCPU_out";
+		nvidia,sample-rate = <11500>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,cf = <10>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+		status = "disabled";
+	};
+
 	mmc@78000000 {
 		compatible = "nvidia,tegra114-sdhci";
 		reg = <0x78000000 0x200>;
@@ -841,6 +866,15 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
+
+			clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
+				 <&tegra_car TEGRA114_CLK_CCLK_LP>,
+				 <&tegra_car TEGRA114_CLK_PLL_X>,
+				 <&tegra_car TEGRA114_CLK_PLL_P>,
+				 <&dfll>;
+			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+			/* FIXME: what's the actual transition time? */
+			clock-latency = <300000>;
 		};
 
 		cpu@1 {
-- 
2.43.0

Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Mikko Perttunen]

On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> Add DFLL clock node to common Tegra114 device tree along with clocks
> property to cpu node.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 341ec0962460..25d063a47ca5
> 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/memory/tegra114-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/reset/tegra114-car.h>
>  #include <dt-bindings/soc/tegra-pmc.h>
> 
>  #include "tegra114-peripherals-opp.dtsi"
> @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
>  		#nvidia,mipi-calibrate-cells = <1>;
>  	};
> 
> +	dfll: clock@70110000 {
> +		compatible = "nvidia,tegra114-dfll";
> +		reg = <0x70110000 0x100>, /* DFLL control */
> +		      <0x70110000 0x100>, /* I2C output control */
> +		      <0x70110100 0x100>, /* Integrated I2C controller */
> +		      <0x70110200 0x100>; /* Look-up table RAM */
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> +			 <&tegra_car TEGRA114_CLK_DFLL_REF>,
> +			 <&tegra_car TEGRA114_CLK_I2C5>;
> +		clock-names = "soc", "ref", "i2c";
> +		resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> +		reset-names = "dvco";
> +		#clock-cells = <0>;
> +		clock-output-names = "dfllCPU_out";
> +		nvidia,sample-rate = <11500>;

Should this be 12500? That would match Tegra124 and a downstream kernel for 
Tegra114 I have.

> +		nvidia,droop-ctrl = <0x00000f00>;
> +		nvidia,force-mode = <1>;
> +		nvidia,cf = <10>;
> +		nvidia,ci = <0>;
> +		nvidia,cg = <2>;
> +		status = "disabled";
> +	};
> +
>  	mmc@78000000 {
>  		compatible = "nvidia,tegra114-sdhci";
>  		reg = <0x78000000 0x200>;
> @@ -841,6 +866,15 @@ cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0>;
> +
> +			clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> +				 <&tegra_car TEGRA114_CLK_CCLK_LP>,
> +				 <&tegra_car TEGRA114_CLK_PLL_X>,
> +				 <&tegra_car TEGRA114_CLK_PLL_P>,
> +				 <&dfll>;
> +			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", 
"dfll";
> +			/* FIXME: what's the actual transition time? */
> +			clock-latency = <300000>;
>  		};
> 
>  		cpu@1 {

Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Svyatoslav Ryhel]

пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> > Add DFLL clock node to common Tegra114 device tree along with clocks
> > property to cpu node.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 341ec0962460..25d063a47ca5
> > 100644
> > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > @@ -4,6 +4,7 @@
> >  #include <dt-bindings/memory/tegra114-mc.h>
> >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/reset/tegra114-car.h>
> >  #include <dt-bindings/soc/tegra-pmc.h>
> >
> >  #include "tegra114-peripherals-opp.dtsi"
> > @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
> >               #nvidia,mipi-calibrate-cells = <1>;
> >       };
> >
> > +     dfll: clock@70110000 {
> > +             compatible = "nvidia,tegra114-dfll";
> > +             reg = <0x70110000 0x100>, /* DFLL control */
> > +                   <0x70110000 0x100>, /* I2C output control */
> > +                   <0x70110100 0x100>, /* Integrated I2C controller */
> > +                   <0x70110200 0x100>; /* Look-up table RAM */
> > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
> > +                      <&tegra_car TEGRA114_CLK_I2C5>;
> > +             clock-names = "soc", "ref", "i2c";
> > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> > +             reset-names = "dvco";
> > +             #clock-cells = <0>;
> > +             clock-output-names = "dfllCPU_out";
> > +             nvidia,sample-rate = <11500>;
>
> Should this be 12500? That would match Tegra124 and a downstream kernel for
> Tegra114 I have.
>

I referred to tegratab and macallan boards in 3.4 kernel which give
11500, maybe sample-rate was changed to 12500 later with tegra124
addition?

> > +             nvidia,droop-ctrl = <0x00000f00>;
> > +             nvidia,force-mode = <1>;
> > +             nvidia,cf = <10>;
> > +             nvidia,ci = <0>;
> > +             nvidia,cg = <2>;
> > +             status = "disabled";
> > +     };
> > +
> >       mmc@78000000 {
> >               compatible = "nvidia,tegra114-sdhci";
> >               reg = <0x78000000 0x200>;
> > @@ -841,6 +866,15 @@ cpu@0 {
> >                       device_type = "cpu";
> >                       compatible = "arm,cortex-a15";
> >                       reg = <0>;
> > +
> > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
> > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
> > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
> > +                              <&dfll>;
> > +                     clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
> "dfll";
> > +                     /* FIXME: what's the actual transition time? */
> > +                     clock-latency = <300000>;
> >               };
> >
> >               cpu@1 {
>
>
>
>

Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Mikko Perttunen]

On Friday, August 22, 2025 2:19 PM Svyatoslav Ryhel wrote:
> пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@nvidia.com> пише:
> > On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> > > Add DFLL clock node to common Tegra114 device tree along with clocks
> > > property to cpu node.
> > > 
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > > 
> > >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index
> > > 341ec0962460..25d063a47ca5
> > > 100644
> > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > @@ -4,6 +4,7 @@
> > > 
> > >  #include <dt-bindings/memory/tegra114-mc.h>
> > >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > 
> > > +#include <dt-bindings/reset/tegra114-car.h>
> > > 
> > >  #include <dt-bindings/soc/tegra-pmc.h>
> > >  
> > >  #include "tegra114-peripherals-opp.dtsi"
> > > 
> > > @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
> > > 
> > >               #nvidia,mipi-calibrate-cells = <1>;
> > >       
> > >       };
> > > 
> > > +     dfll: clock@70110000 {
> > > +             compatible = "nvidia,tegra114-dfll";
> > > +             reg = <0x70110000 0x100>, /* DFLL control */
> > > +                   <0x70110000 0x100>, /* I2C output control */
> > > +                   <0x70110100 0x100>, /* Integrated I2C controller */
> > > +                   <0x70110200 0x100>; /* Look-up table RAM */
> > > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> > > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> > > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
> > > +                      <&tegra_car TEGRA114_CLK_I2C5>;
> > > +             clock-names = "soc", "ref", "i2c";
> > > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> > > +             reset-names = "dvco";
> > > +             #clock-cells = <0>;
> > > +             clock-output-names = "dfllCPU_out";
> > > +             nvidia,sample-rate = <11500>;
> > 
> > Should this be 12500? That would match Tegra124 and a downstream kernel
> > for
> > Tegra114 I have.
> 
> I referred to tegratab and macallan boards in 3.4 kernel which give
> 11500, maybe sample-rate was changed to 12500 later with tegra124
> addition?

That's interesting. I was looking at the public roth (Shield Portable) kernel, 
which does not support Tegra124. I checked the L4T r17 release now, and it 
seems it's a newer version, where the sample rate has been changed to 11500 on 
some boards due to a voltage undershoot issue with vdd_cpu on macallan/
tegratab [1].

So on macallan/tegratab, the vdd_cpu (smps123) ramp rate should be set to 
2.5mV/us and sample-rate to 11500, while on other boards it can be 5mV/us with 
12500 for faster ramping.

[1] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-2.6/+/
b92cab2d4cb6379aeded80adc4c5d0708c3f038e%5E%21/#F0

Cheers,
Mikko

> 
> > > +             nvidia,droop-ctrl = <0x00000f00>;
> > > +             nvidia,force-mode = <1>;
> > > +             nvidia,cf = <10>;
> > > +             nvidia,ci = <0>;
> > > +             nvidia,cg = <2>;
> > > +             status = "disabled";
> > > +     };
> > > +
> > > 
> > >       mmc@78000000 {
> > >       
> > >               compatible = "nvidia,tegra114-sdhci";
> > >               reg = <0x78000000 0x200>;
> > > 
> > > @@ -841,6 +866,15 @@ cpu@0 {
> > > 
> > >                       device_type = "cpu";
> > >                       compatible = "arm,cortex-a15";
> > >                       reg = <0>;
> > > 
> > > +
> > > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> > > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
> > > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
> > > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
> > > +                              <&dfll>;
> > > +                     clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
> > 
> > "dfll";
> > 
> > > +                     /* FIXME: what's the actual transition time? */
> > > +                     clock-latency = <300000>;
> > > 
> > >               };
> > >               
> > >               cpu@1 {

Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Svyatoslav]

25 серпня 2025 р. 07:20:10 GMT+03:00, Mikko Perttunen <mperttunen@nvidia.com> пише:
>On Friday, August 22, 2025 2:19 PM Svyatoslav Ryhel wrote:
>> пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@nvidia.com> пише:
>> > On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
>> > > Add DFLL clock node to common Tegra114 device tree along with clocks
>> > > property to cpu node.
>> > > 
>> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
>> > > ---
>> > > 
>> > >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
>> > >  1 file changed, 34 insertions(+)
>> > > 
>> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index
>> > > 341ec0962460..25d063a47ca5
>> > > 100644
>> > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > @@ -4,6 +4,7 @@
>> > > 
>> > >  #include <dt-bindings/memory/tegra114-mc.h>
>> > >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>> > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> > > 
>> > > +#include <dt-bindings/reset/tegra114-car.h>
>> > > 
>> > >  #include <dt-bindings/soc/tegra-pmc.h>
>> > >  
>> > >  #include "tegra114-peripherals-opp.dtsi"
>> > > 
>> > > @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
>> > > 
>> > >               #nvidia,mipi-calibrate-cells = <1>;
>> > >       
>> > >       };
>> > > 
>> > > +     dfll: clock@70110000 {
>> > > +             compatible = "nvidia,tegra114-dfll";
>> > > +             reg = <0x70110000 0x100>, /* DFLL control */
>> > > +                   <0x70110000 0x100>, /* I2C output control */
>> > > +                   <0x70110100 0x100>, /* Integrated I2C controller */
>> > > +                   <0x70110200 0x100>; /* Look-up table RAM */
>> > > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> > > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
>> > > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
>> > > +                      <&tegra_car TEGRA114_CLK_I2C5>;
>> > > +             clock-names = "soc", "ref", "i2c";
>> > > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
>> > > +             reset-names = "dvco";
>> > > +             #clock-cells = <0>;
>> > > +             clock-output-names = "dfllCPU_out";
>> > > +             nvidia,sample-rate = <11500>;
>> > 
>> > Should this be 12500? That would match Tegra124 and a downstream kernel
>> > for
>> > Tegra114 I have.
>> 
>> I referred to tegratab and macallan boards in 3.4 kernel which give
>> 11500, maybe sample-rate was changed to 12500 later with tegra124
>> addition?
>
>That's interesting. I was looking at the public roth (Shield Portable) kernel, 
>which does not support Tegra124. I checked the L4T r17 release now, and it 
>seems it's a newer version, where the sample rate has been changed to 11500 on 
>some boards due to a voltage undershoot issue with vdd_cpu on macallan/
>tegratab [1].
>
>So on macallan/tegratab, the vdd_cpu (smps123) ramp rate should be set to 
>2.5mV/us and sample-rate to 11500, while on other boards it can be 5mV/us with 
>12500 for faster ramping.
>
>[1] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-2.6/+/
>b92cab2d4cb6379aeded80adc4c5d0708c3f038e%5E%21/#F0
>
>Cheers,
>Mikko
>

So should I stick with 11500 as a safer, acceptable for every t114 option?

>> 
>> > > +             nvidia,droop-ctrl = <0x00000f00>;
>> > > +             nvidia,force-mode = <1>;
>> > > +             nvidia,cf = <10>;
>> > > +             nvidia,ci = <0>;
>> > > +             nvidia,cg = <2>;
>> > > +             status = "disabled";
>> > > +     };
>> > > +
>> > > 
>> > >       mmc@78000000 {
>> > >       
>> > >               compatible = "nvidia,tegra114-sdhci";
>> > >               reg = <0x78000000 0x200>;
>> > > 
>> > > @@ -841,6 +866,15 @@ cpu@0 {
>> > > 
>> > >                       device_type = "cpu";
>> > >                       compatible = "arm,cortex-a15";
>> > >                       reg = <0>;
>> > > 
>> > > +
>> > > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
>> > > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
>> > > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
>> > > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
>> > > +                              <&dfll>;
>> > > +                     clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
>> > 
>> > "dfll";
>> > 
>> > > +                     /* FIXME: what's the actual transition time? */
>> > > +                     clock-latency = <300000>;
>> > > 
>> > >               };
>> > >               
>> > >               cpu@1 {
>
>
>
>

Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

[Mikko Perttunen]

On Monday, August 25, 2025 1:26 PM Svyatoslav wrote:
> 25 серпня 2025 р. 07:20:10 GMT+03:00, Mikko Perttunen 
<mperttunen@nvidia.com> пише:
> >On Friday, August 22, 2025 2:19 PM Svyatoslav Ryhel wrote:
> >> пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@nvidia.com> 
пише:
> >> > On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> >> > > Add DFLL clock node to common Tegra114 device tree along with clocks
> >> > > property to cpu node.
> >> > > 
> >> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> >> > > ---
> >> > > 
> >> > >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34
> >> > >  ++++++++++++++++++++++++++
> >> > >  1 file changed, 34 insertions(+)
> >> > > 
> >> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> >> > > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index
> >> > > 341ec0962460..25d063a47ca5
> >> > > 100644
> >> > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> >> > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> >> > > @@ -4,6 +4,7 @@
> >> > > 
> >> > >  #include <dt-bindings/memory/tegra114-mc.h>
> >> > >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> >> > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> > > 
> >> > > +#include <dt-bindings/reset/tegra114-car.h>
> >> > > 
> >> > >  #include <dt-bindings/soc/tegra-pmc.h>
> >> > >  
> >> > >  #include "tegra114-peripherals-opp.dtsi"
> >> > > 
> >> > > @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
> >> > > 
> >> > >               #nvidia,mipi-calibrate-cells = <1>;
> >> > >       
> >> > >       };
> >> > > 
> >> > > +     dfll: clock@70110000 {
> >> > > +             compatible = "nvidia,tegra114-dfll";
> >> > > +             reg = <0x70110000 0x100>, /* DFLL control */
> >> > > +                   <0x70110000 0x100>, /* I2C output control */
> >> > > +                   <0x70110100 0x100>, /* Integrated I2C controller
> >> > > */
> >> > > +                   <0x70110200 0x100>; /* Look-up table RAM */
> >> > > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> >> > > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> >> > > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
> >> > > +                      <&tegra_car TEGRA114_CLK_I2C5>;
> >> > > +             clock-names = "soc", "ref", "i2c";
> >> > > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> >> > > +             reset-names = "dvco";
> >> > > +             #clock-cells = <0>;
> >> > > +             clock-output-names = "dfllCPU_out";
> >> > > +             nvidia,sample-rate = <11500>;
> >> > 
> >> > Should this be 12500? That would match Tegra124 and a downstream kernel
> >> > for
> >> > Tegra114 I have.
> >> 
> >> I referred to tegratab and macallan boards in 3.4 kernel which give
> >> 11500, maybe sample-rate was changed to 12500 later with tegra124
> >> addition?
> >
> >That's interesting. I was looking at the public roth (Shield Portable)
> >kernel, which does not support Tegra124. I checked the L4T r17 release
> >now, and it seems it's a newer version, where the sample rate has been
> >changed to 11500 on some boards due to a voltage undershoot issue with
> >vdd_cpu on macallan/ tegratab [1].
> >
> >So on macallan/tegratab, the vdd_cpu (smps123) ramp rate should be set to
> >2.5mV/us and sample-rate to 11500, while on other boards it can be 5mV/us
> >with 12500 for faster ramping.
> >
> >[1] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-2.6/+/
> >b92cab2d4cb6379aeded80adc4c5d0708c3f038e%5E%21/#F0
> >
> >Cheers,
> >Mikko
> 
> So should I stick with 11500 as a safer, acceptable for every t114 option?

I think it'd make sense to just put it in each board file separately. T124 DTs 
already seem to be doing that in addition to the main file.

> 
> >> > > +             nvidia,droop-ctrl = <0x00000f00>;
> >> > > +             nvidia,force-mode = <1>;
> >> > > +             nvidia,cf = <10>;
> >> > > +             nvidia,ci = <0>;
> >> > > +             nvidia,cg = <2>;
> >> > > +             status = "disabled";
> >> > > +     };
> >> > > +
> >> > > 
> >> > >       mmc@78000000 {
> >> > >       
> >> > >               compatible = "nvidia,tegra114-sdhci";
> >> > >               reg = <0x78000000 0x200>;
> >> > > 
> >> > > @@ -841,6 +866,15 @@ cpu@0 {
> >> > > 
> >> > >                       device_type = "cpu";
> >> > >                       compatible = "arm,cortex-a15";
> >> > >                       reg = <0>;
> >> > > 
> >> > > +
> >> > > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> >> > > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
> >> > > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
> >> > > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
> >> > > +                              <&dfll>;
> >> > > +                     clock-names = "cpu_g", "cpu_lp", "pll_x",
> >> > > "pll_p",
> >> > 
> >> > "dfll";
> >> > 
> >> > > +                     /* FIXME: what's the actual transition time? */
> >> > > +                     clock-latency = <300000>;
> >> > > 
> >> > >               };
> >> > >               
> >> > >               cpu@1 {