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Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261007144150.15113-1-ggherdovich@suse.cz> <27b226c7-f30b-4863-96e6-6798232863c5@amd.com> <93531c5c-5638-4a20-919a-8471a7222218@suse.cz> Content-Language: en-US From: Giovanni Gherdovich In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Flag: NO X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.49 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.cz:s=susede2_rsa,suse.cz:s=susede2_ed25519]; NEURAL_HAM_SHORT(-0.19)[-0.964]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; XM_UA_NO_VERSION(0.01)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_SEVEN(0.00)[8]; RCVD_TLS_ALL(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.cz:dkim]; DNSWL_BLOCKED(0.00)[2a07:de40:b281:106:10:150:64:167:received,2a07:de40:b281:104:10:150:64:97:from]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.cz:s=susede2_rsa,suse.cz:s=susede2_ed25519]; DKIM_TRACE(0.00)[suse.cz:+] X-Rspamd-Action: no action X-Spam-Score: -4.49 X-Spam-Level: X-Rspamd-Queue-Id: 57E1E21BBC On Wed Oct 7, 2026 21:45, Mario Limonciello wrote: > On 10/7/26 14:38, Giovanni Gherdovich wrote: >> On Wed Oct 7, 2026 16:56, Mario Limonciello wrote: >>> [...] >>> I don't understand why core count matters though. >> >> My thinking was: >> >> 1. I want to make the "quirk" to match as many chips as possible, to >> make it more useful and worthwhile. >> 2. The doc I have, "Power and Thermal Data Sheet" (publication #56736 >> in the AMD doc library), is for family 0x17, models 0x30-0x3F >> processors. >> 3. Problem: these have different nominal frequencies, depending on the >> core count. Specifically: >> 24 cores: 3800 MHz (like the Ryzen 3090x I need) >> 32 cores: 3700 Mhz >> 64 cores: 2900 MHz >> 4. Thus I decided to match for family 0x17, model 0x30-0x3f, 24 cores. >> Without the core count constraint, I couldn't tell which of the >> three nominal frequencies above should apply. > > If there does need to be a quirk I guess I would actually say there > should be 3 quirks then. One for each core count version. Makes sense. >> All that said, I've asked the openSUSE user to test the newer BIOS, >> we'll see what that gives. > > Thanks! Based on the findings from the BIOS update everything in > this thread should be enough to either make a v2 incorporating > feedback (mostly making it clearer) or to drop the patch. Yes I think so. Thanks a lot for your support so far. Giovanni