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Mon, 13 Jul 2026 09:56:13 -0700 (PDT) X-Received: by 2002:a05:6a21:3992:b0:3b3:23a2:edff with SMTP id adf61e73a8af0-3c1102a15c4mr10772622637.28.1783961772810; Mon, 13 Jul 2026 09:56:12 -0700 (PDT) Received: from [192.168.1.100] ([157.48.180.168]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-313cb804197sm23242316eec.13.2026.07.13.09.56.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jul 2026 09:56:12 -0700 (PDT) Message-ID: Date: Mon, 13 Jul 2026 22:26:03 +0530 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring To: Jonathan Cameron Cc: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , David Collins , Anjelique Melendez , Neil Armstrong , Stephan Gerhold References: <20260705-gen3_adc_tm-v3-0-ac62f387dbce@oss.qualcomm.com> <20260705-gen3_adc_tm-v3-3-ac62f387dbce@oss.qualcomm.com> <20260706005134.7add6bbe@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20260706005134.7add6bbe@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEzMDE3NSBTYWx0ZWRfX3q1Nt8m5kKyW o6IsnaDO0p4SGOyD0cQ3xbcDSToQPr23ukw2TA7kkbp+jbZfx53tEr1vUiw+c1q1MxqKQ8zrKvQ TDnbTDukhj4zoGgImDInzB+xLuLp+4z6yfnD81iFdq2yOUZDfZyeTVccbWZBZmEFJpptWJ9dWbu 0yw+g/SUlPeDdLuExZ5a7Mok9QMZSDB8RFBYp7SOdByGM0CFkW879hmJoaIYBPym2dMZAQR52MD Xja1+oCwKz+Hq6a0NGu5bJx1IEznoUajYm0L6mGPTgYG2JHVyUor3pHUczBH01RgQ+9xyContIu UyU82gs9M0mWTuAS/qmuOzpHX1c2NSagc4ndm2breVTbgX8R9od+p1VN7pH/yf3Fs/T6JwUk7AF urnycEhy1Xr3eoQulHBsMX102Y6o2WrF3/j51d6HGrZL/kKoRUhePQWtr6pW6GVryxf+ZoTHtUR i1HRe7BjPY3OcOl8NnQ== X-Proofpoint-ORIG-GUID: JOnaOHudqVXobwShpP4DvUnWKaxYdygv X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEzMDE3NSBTYWx0ZWRfX4GM2mEI0Rf05 b74tpLKq3WXDL5dgdLM0nHpZQin8n3Jn8um87bYIXv6NVt77OcjDBebu69RbTULcKO5w7/khEe0 fkBokKU5BMBUY3BR1XWkw3wN9R9vCdA= X-Proofpoint-GUID: JOnaOHudqVXobwShpP4DvUnWKaxYdygv X-Authority-Analysis: v=2.4 cv=aaJRWxot c=1 sm=1 tr=0 ts=6a5518ae cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=62VzjLAzdHZQ3L95IMgkXw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=Q30daxf-3pjc-4xqwVQA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-13_04,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607130175 Hi Jonathan, On 7/6/2026 5:21 AM, Jonathan Cameron wrote: > On Sun, 05 Jul 2026 22:23:35 +0530 > Jishnu Prakash wrote: > >> Add support for ADC_TM part of PMIC5 Gen3. >> >> This is an auxiliary driver under the Gen3 ADC driver, which implements the >> threshold setting and interrupt generating functionalities of QCOM ADC_TM >> drivers, used to support thermal trip points. >> >> Signed-off-by: Jishnu Prakash > Hi Jishnu, > > I took a quick look at this. A few really minor suggestions inline. > >> diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c >> new file mode 100644 >> index 000000000000..5a82c4d8a37e >> --- /dev/null >> +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c > > >> +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5) >> +{ >> + struct thermal_zone_device *tzd; >> + unsigned int channel; >> + int ret; >> + >> + for (int i = 0; i < adc_tm5->nchannels; i++) { >> + channel = ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props); >> + tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel, >> + &adc_tm5->chan_props[i], >> + &adc_tm_ops); >> + if (IS_ERR(tzd)) { >> + if (PTR_ERR(tzd) == -ENODEV) { >> + dev_info(adc_tm5->dev, >> + "thermal sensor on channel %d is not used\n", > > That seems noisy. Maybe dev_dbg() appropriate if this is an expected > board dependent condition? > >> + channel); >> + continue; >> + } >> + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd), >> + "Error registering TZ zone:%ld for channel:%d\n", >> + PTR_ERR(tzd), channel); >> + } >> + adc_tm5->chan_props[i].tzd = tzd; >> + ret = devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd); >> + if (ret) >> + return ret; >> + } >> + return 0; >> +} > > >> +static int adc_tm5_probe(struct auxiliary_device *aux_dev, >> + const struct auxiliary_device_id *id) >> +{ >> + struct adc_tm5_gen3_chip *adc_tm5; >> + struct tm5_aux_dev_wrapper *aux_dev_wrapper; >> + struct device *dev = &aux_dev->dev; >> + u32 irq_flags; >> + int ret; >> + >> + adc_tm5 = devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL); >> + if (!adc_tm5) >> + return -ENOMEM; >> + >> + aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, aux_dev); >> + >> + adc_tm5->dev = dev; >> + adc_tm5->dev_data = aux_dev_wrapper->dev_data; >> + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels; >> + adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels, >> + sizeof(*adc_tm5->chan_props), GFP_KERNEL); >> + if (!adc_tm5->chan_props) >> + return -ENOMEM; >> + >> + for (int i = 0; i < adc_tm5->nchannels; i++) { >> + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i]; >> + adc_tm5->chan_props[i].timer = MEAS_INT_1S; >> + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8; >> + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8; >> + adc_tm5->chan_props[i].chip = adc_tm5; >> + } >> + >> + /* This is to disable all ADC_TM channels in case of probe failure. */ > > Perhaps indicate who turned them on? On from reset or something hidden > somewhere else? In the probe, ADC_TM channels are only enabled in the loop in adc_tm5_register_tzd(), when they have the set_trips API called during thermal zone registration. I'll update the comment to mention this. > >> + ret = devm_add_action(dev, adc5_gen3_disable, adc_tm5); >> + if (ret) >> + return ret; > > ... > >> + /* >> + * First SDAM's interrupt is shared between main ADC driver >> + * and auxiliary TM driver, so its flags must include >> + * IRQF_SHARED. This is not needed for other SDAMs as they >> + * will be used only for TM functionality. > > If indent of this doesn't change, rewrap to 80 chars. > >> + */ >> + irq_flags = IRQF_ONESHOT | IRQF_SHARED; >> + for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) { >> + ret = devm_request_threaded_irq(dev, >> + adc_tm5->dev_data->base[i].irq, >> + adctm5_gen3_isr, adctm5_gen3_isr_thread, >> + irq_flags, adc_tm5->dev_data->base[i].irq_name, >> + adc_tm5); >> + if (ret < 0) >> + return ret; >> + irq_flags = IRQF_ONESHOT; > Whilst this code works, I'd be tempted to make it less ordering dependent. E.g. > for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) { > u32 irq_flags = IRQF_ONESHOT; > > /* > * First SDAM's interrupt is shared between main ADC driver > * and auxiliary TM driver, so its flags must include > * IRQF_SHARED. This is not needed for other SDAMs as they > * will be used only for TM functionality. > */ > if (i == 0) > irq_flags |= IRQF_SHARED; Sure, I'll update the function this way and also address your other comments. Thanks, Jishnu > > ret = devm_request_threaded_irq(dev, >> + adc_tm5->dev_data->base[i].irq, >> + adctm5_gen3_isr, adctm5_gen3_isr_thread, >> + irq_flags, adc_tm5->dev_data->base[i].irq_name, >> + adc_tm5); >> + } >> + >> + return 0; >> +} > >