linux-pm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Mario Limonciello <superm1@kernel.org>
To: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>,
	"Gautham R . Shenoy" <gautham.shenoy@amd.com>,
	Perry Yuan <perry.yuan@amd.com>
Cc: "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
	<linux-kernel@vger.kernel.org>,
	"open list:CPU FREQUENCY SCALING FRAMEWORK"
	<linux-pm@vger.kernel.org>,
	Mario Limonciello <mario.limonciello@amd.com>
Subject: Re: [PATCH 07/14] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks
Date: Tue, 11 Feb 2025 12:31:22 -0600	[thread overview]
Message-ID: <f43e7708-ebac-48dd-945c-647f8908bc7c@kernel.org> (raw)
In-Reply-To: <21250cdb-e398-448c-be08-e9b3778b3771@amd.com>

On 2/11/2025 00:16, Dhananjay Ugwekar wrote:
> On 2/7/2025 3:26 AM, Mario Limonciello wrote:
>> From: Mario Limonciello <mario.limonciello@amd.com>
>>
>> Bitfield masks are easier to follow and less error prone.
> 
> Looks good to me, just one suggestion below, apart from that,
> 
> Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
> 
>>
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>>   arch/x86/include/asm/msr-index.h | 18 +++++++++---------
>>   arch/x86/kernel/acpi/cppc.c      |  2 +-
>>   drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
>>   drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
>>   4 files changed, 20 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 3eadc4d5de837..f77335ebae981 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -700,15 +700,15 @@
>>   #define MSR_AMD_CPPC_REQ		0xc00102b3
>>   #define MSR_AMD_CPPC_STATUS		0xc00102b4
>>   
>> -#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
>> -#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
>> -#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
>> -#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
>> -
>> -#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
>> -#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
>> -#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
>> -#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
>> +#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)
> 
> How about  AMD_CPPC_"CAP"_LOWEST_PERF_MASK and
> 
>> +#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
>> +#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
>> +#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
>> +
>> +#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
> 
> 	   AMD_CPPC_"REQ"_MAX_PERF_MASK, just to indicate these fields
> belong to which register? But we can keep it as is, if you think it
> would be a mouthful, I'll leave it upto you.

I'll split the difference and include a comment around them to indicate 
what they're for.

> 
> Thanks,
> Dhananjay
> 
>> +#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
>> +#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
>> +#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>>   
>>   /* AMD Performance Counter Global Status and Control MSRs */
>>   #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
>> diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
>> index d745dd586303c..d68a4cb0168fa 100644
>> --- a/arch/x86/kernel/acpi/cppc.c
>> +++ b/arch/x86/kernel/acpi/cppc.c
>> @@ -149,7 +149,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
>>   		if (ret)
>>   			goto out;
>>   
>> -		val = AMD_CPPC_HIGHEST_PERF(val);
>> +		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
>>   	} else {
>>   		ret = cppc_get_highest_perf(cpu, &val);
>>   		if (ret)
>> diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
>> index adaa62fb2b04e..2595faa492bf1 100644
>> --- a/drivers/cpufreq/amd-pstate-ut.c
>> +++ b/drivers/cpufreq/amd-pstate-ut.c
>> @@ -158,10 +158,10 @@ static void amd_pstate_ut_check_perf(u32 index)
>>   				return;
>>   			}
>>   
>> -			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
>> -			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
>> -			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
>> -			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> +			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
>> +			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
>> +			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
>> +			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>>   		}
>>   
>>   		if (highest_perf != READ_ONCE(cpudata->perf.highest_perf) &&
>> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
>> index 71636bd9884c8..cd96443fc117f 100644
>> --- a/drivers/cpufreq/amd-pstate.c
>> +++ b/drivers/cpufreq/amd-pstate.c
>> @@ -89,11 +89,6 @@ static bool cppc_enabled;
>>   static bool amd_pstate_prefcore = true;
>>   static struct quirk_entry *quirks;
>>   
>> -#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
>> -#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
>> -#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
>> -#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>> -
>>   /*
>>    * AMD Energy Preference Performance (EPP)
>>    * The EPP is used in the CCLK DPM controller to drive
>> @@ -445,12 +440,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
>>   
>>   	perf.highest_perf = numerator;
>>   	perf.max_limit_perf = numerator;
>> -	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> -	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
>> -	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
>> -	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> +	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>> +	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
>> +	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
>> +	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>>   	WRITE_ONCE(cpudata->perf, perf);
>> -	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
>> +	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
>> +
>>   	return 0;
>>   }
>>   
> 


  reply	other threads:[~2025-02-11 18:31 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 21:56 [PATCH 00/14] amd-pstate cleanups Mario Limonciello
2025-02-06 21:56 ` [PATCH 01/14] cpufreq/amd-pstate: Show a warning when a CPU fails to setup Mario Limonciello
2025-02-10 11:59   ` Dhananjay Ugwekar
2025-02-10 13:50     ` Gautham R. Shenoy
2025-02-10 15:13       ` Mario Limonciello
2025-02-06 21:56 ` [PATCH 02/14] cpufreq/amd-pstate: Drop min and max cached frequencies Mario Limonciello
2025-02-07 10:44   ` Dhananjay Ugwekar
2025-02-07 16:15     ` Mario Limonciello
2025-02-06 21:56 ` [PATCH 03/14] cpufreq/amd-pstate: Move perf values into a union Mario Limonciello
2025-02-10 13:38   ` Dhananjay Ugwekar
2025-02-11 22:14     ` Mario Limonciello
2025-02-12  6:31       ` Dhananjay Ugwekar
2025-02-12 22:03         ` Mario Limonciello
2025-02-06 21:56 ` [PATCH 04/14] cpufreq/amd-pstate: Overhaul locking Mario Limonciello
2025-02-11  5:02   ` Dhananjay Ugwekar
2025-02-11 21:54     ` Mario Limonciello
2025-02-12  5:15       ` Dhananjay Ugwekar
2025-02-12 22:05         ` Mario Limonciello
2025-02-06 21:56 ` [PATCH 05/14] cpufreq/amd-pstate: Drop `cppc_cap1_cached` Mario Limonciello
2025-02-11  5:46   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 06/14] cpufreq/amd-pstate-ut: Use _free macro to free put policy Mario Limonciello
2025-02-11  5:58   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 07/14] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks Mario Limonciello
2025-02-11  6:16   ` Dhananjay Ugwekar
2025-02-11 18:31     ` Mario Limonciello [this message]
2025-02-06 21:56 ` [PATCH 08/14] cpufreq/amd-pstate: Cache CPPC request in shared mem case too Mario Limonciello
2025-02-11  9:18   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 09/14] cpufreq/amd-pstate: Move all EPP tracing into *_update_perf and *_set_epp functions Mario Limonciello
2025-02-12  6:39   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 10/14] cpufreq/amd-pstate: Update cppc_req_cached for shared mem EPP writes Mario Limonciello
2025-02-11 13:01   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 11/14] cpufreq/amd-pstate: Drop debug statements for policy setting Mario Limonciello
2025-02-11 13:03   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 12/14] cpufreq/amd-pstate: Cache a pointer to policy in cpudata Mario Limonciello
2025-02-11 13:13   ` Dhananjay Ugwekar
2025-02-11 19:17     ` Mario Limonciello
2025-02-12  3:52       ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 13/14] cpufreq/amd-pstate: Rework CPPC enabling Mario Limonciello
2025-02-13  4:42   ` Dhananjay Ugwekar
2025-02-06 21:56 ` [PATCH 14/14] cpufreq/amd-pstate: Stop caching EPP Mario Limonciello
2025-02-11 13:27   ` Dhananjay Ugwekar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f43e7708-ebac-48dd-945c-647f8908bc7c@kernel.org \
    --to=superm1@kernel.org \
    --cc=Dhananjay.Ugwekar@amd.com \
    --cc=gautham.shenoy@amd.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=mario.limonciello@amd.com \
    --cc=perry.yuan@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).