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Thu, 09 Jul 2026 05:58:27 -0700 (PDT) X-Received: by 2002:a05:620a:178f:b0:92e:7436:5284 with SMTP id af79cd13be357-92ed7a1c5cemr287073385a.5.1783601907084; Thu, 09 Jul 2026 05:58:27 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15c6bd0d72sm296238466b.7.2026.07.09.05.58.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jul 2026 05:58:26 -0700 (PDT) Message-ID: Date: Thu, 9 Jul 2026 14:58:23 +0200 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/4] powercap: qcom: Add SPEL powercap driver To: Manaf Meethalavalappu Pallikunhi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: Gaurav Kohli , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260702-qcom_spel_driver_upstream-v3-0-434d50f0c5b0@oss.qualcomm.com> <20260702-qcom_spel_driver_upstream-v3-3-434d50f0c5b0@oss.qualcomm.com> <21f13da7-94ee-4eb2-b2bd-6200d70f38f9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <21f13da7-94ee-4eb2-b2bd-6200d70f38f9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA5MDEyNyBTYWx0ZWRfX2O80Uap4j3Te D/zRCF+vI+a8+yp/t86SXj18KD6MBtzdiDVcCBfhL9nQaNIiziEPR6L3y2v6/7d6blMvSLN54s6 MPOYNA0ISTYXLQubwMqchB60N8r8raI= X-Proofpoint-GUID: Y2CQ1jHJ9npUXKp5qW-J6rq5IJNl5xM_ X-Proofpoint-ORIG-GUID: Y2CQ1jHJ9npUXKp5qW-J6rq5IJNl5xM_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA5MDEyNyBTYWx0ZWRfX/i5L2KpAcmSf qCtiMvPSeGjrWDj+vEAfDMsuuezbIEpwtTTUv93rWd51kJeWz8J45PeOIDBODvQsVxQHcE/Ael0 BVVtGkKjnEnmi/rzQ9fDS4Usas0S+fZbJrRk6aYo/oGSa35lNE2VtejQk1pJclv1diaHYPtMf6e 7XDglPc2Bw5VUDqO21HF3iqsOms8yNYumKm8ntpc27CPFbvRwDO1o1Z4uMdr0TAGwAeVsBc2fk9 q0du0QmmLjom0Hw96eKj3CI6+26BXjb74hNkcXXPEeifSl2bPpnNof8nY7KZhd5MC0oplFWp1W3 zQnR8uWsPXGFD9nd9+myogKx4kKDfHbZ9uS+nxYjwwUujmidfUs1czVakvlSKO3qirln9SAe7p6 gtUTy0cIy7z7OBWNiObqerIyEMJkTn20wu35YXaPmEsU3RPByFV0q5QDzSpFwK817ped35dmGAE CZfQ+QsdfK0VJmjYH5w== X-Authority-Analysis: v=2.4 cv=H43rBeYi c=1 sm=1 tr=0 ts=6a4f9af4 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=fz3elM8aSJ4FunxCNjAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-09_02,2026-07-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607090127 On 7/6/26 1:57 PM, Konrad Dybcio wrote: > On 7/2/26 7:22 PM, Manaf Meethalavalappu Pallikunhi wrote: >> The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware >> based power monitoring and limiting capabilities for various power >> domains including System, SoC, CPU clusters, GPU, and various other >> subsystems. >> >> The driver integrates with the Linux powercap framework, exposing SPEL >> capabilities through powercap sysfs interfaces. >> >> Signed-off-by: Manaf Meethalavalappu Pallikunhi >> --- > > [...] > >> +#define TIME_WINDOW_MASK_L GENMASK(14, 0) >> +#define TIME_WINDOW_MASK_H GENMASK(22, 16) >> +#define TIME_WINDOW_MAX ((FIELD_MAX(TIME_WINDOW_MASK_H) << 15) | \ >> + FIELD_MAX(TIME_WINDOW_MASK_L)) > > I am having difficulty correlating this mask to the register > description I have available. Are you sure what you call > TIME_WINDOW_MASK_L actually exists? > > [...] > >> +/* Constraint configuration */ >> +static const struct spel_constraint_info constraints[] = { >> + /* SYS domain constraints */ >> + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, >> + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, >> + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, >> + { 0x1c, 0x7c, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, >> + /* SoC domain constraints */ >> + { 0x00, 0x60, BIT(4), SPEL_DOMAIN_SOC, POWER_LIMIT1 }, >> + { 0x04, 0x64, BIT(5), SPEL_DOMAIN_SOC, POWER_LIMIT2 }, >> + { 0x08, 0x68, BIT(6), SPEL_DOMAIN_SOC, POWER_LIMIT3 }, >> + { 0x0c, 0x6c, BIT(7), SPEL_DOMAIN_SOC, POWER_LIMIT4 }, > > Similarly, these offsets are difficult for me to correlate with the > register names in the constraints/0x0ef3_d000 space They are apparently correct, I had outdated information at hand Konrad