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From: Sathyanarayanan Kuppuswamy  <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>,
	Kai-Heng Feng <kai.heng.feng@canonical.com>,
	Rajvi Jingar <rajvi.jingar@linux.intel.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Koba Ko <koba.ko@canonical.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	"David E . Box" <david.e.box@linux.intel.com>,
	linux-pci@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v4 6/9] PCI/PTM: Preserve RsvdP bits in PTM Control register
Date: Fri, 9 Sep 2022 16:46:51 -0700	[thread overview]
Message-ID: <f8249b66-0ee6-0b47-9ee1-86a96a27e7fa@linux.intel.com> (raw)
In-Reply-To: <20220909202505.314195-7-helgaas@kernel.org>



On 9/9/22 1:25 PM, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
> 
> Even though only the low 16 bits of PTM Control are currently defined, the
> register is 32 bits wide and the unused bits are RsvdP ("Reserved and
> Preserved"), so software must preserve the values of those bits when
> writing the register.
> 
> Update PTM Control reads and writes to use 32-bit accesses and preserve the
> reserved bits on writes.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---

Looks good to me.

Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>


>  drivers/pci/pcie/ptm.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
> index fc296b352fe2..5b8598b222b0 100644
> --- a/drivers/pci/pcie/ptm.c
> +++ b/drivers/pci/pcie/ptm.c
> @@ -12,14 +12,14 @@
>  static void __pci_disable_ptm(struct pci_dev *dev)
>  {
>  	u16 ptm = dev->ptm_cap;
> -	u16 ctrl;
> +	u32 ctrl;
>  
>  	if (!ptm)
>  		return;
>  
> -	pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl);
> +	pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
>  	ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
> -	pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl);
> +	pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl);
>  }
>  
>  /**
> @@ -41,7 +41,7 @@ void pci_save_ptm_state(struct pci_dev *dev)
>  {
>  	u16 ptm = dev->ptm_cap;
>  	struct pci_cap_saved_state *save_state;
> -	u16 *cap;
> +	u32 *cap;
>  
>  	if (!ptm)
>  		return;
> @@ -50,15 +50,15 @@ void pci_save_ptm_state(struct pci_dev *dev)
>  	if (!save_state)
>  		return;
>  
> -	cap = (u16 *)&save_state->cap.data[0];
> -	pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap);
> +	cap = (u32 *)&save_state->cap.data[0];
> +	pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, cap);
>  }
>  
>  void pci_restore_ptm_state(struct pci_dev *dev)
>  {
>  	u16 ptm = dev->ptm_cap;
>  	struct pci_cap_saved_state *save_state;
> -	u16 *cap;
> +	u32 *cap;
>  
>  	if (!ptm)
>  		return;
> @@ -67,8 +67,8 @@ void pci_restore_ptm_state(struct pci_dev *dev)
>  	if (!save_state)
>  		return;
>  
> -	cap = (u16 *)&save_state->cap.data[0];
> -	pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap);
> +	cap = (u32 *)&save_state->cap.data[0];
> +	pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, *cap);
>  }
>  
>  /*
> @@ -112,7 +112,7 @@ void pci_ptm_init(struct pci_dev *dev)
>  		return;
>  
>  	dev->ptm_cap = ptm;
> -	pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16));
> +	pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32));
>  
>  	pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap);
>  	dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
> @@ -170,7 +170,10 @@ static int __pci_enable_ptm(struct pci_dev *dev)
>  			return -EINVAL;
>  	}
>  
> -	ctrl = PCI_PTM_CTRL_ENABLE;
> +	pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
> +
> +	ctrl |= PCI_PTM_CTRL_ENABLE;
> +	ctrl &= ~PCI_PTM_GRANULARITY_MASK;
>  	ctrl |= dev->ptm_granularity << 8;
>  	if (dev->ptm_root)
>  		ctrl |= PCI_PTM_CTRL_ROOT;

-- 
Sathyanarayanan Kuppuswamy
Linux Kernel Developer

  reply	other threads:[~2022-09-09 23:46 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-09 20:24 [PATCH v4 0/9] PCI/PM: Always disable PTM for all devices during suspend Bjorn Helgaas
2022-09-09 20:24 ` [PATCH v4 1/9] PCI/PTM: Cache PTM Capability offset Bjorn Helgaas
2022-09-09 23:38   ` Sathyanarayanan Kuppuswamy
2022-09-09 20:24 ` [PATCH v4 2/9] PCI/PTM: Add pci_upstream_ptm() helper Bjorn Helgaas
2022-09-09 23:38   ` Sathyanarayanan Kuppuswamy
2022-09-09 20:24 ` [PATCH v4 3/9] PCI/PTM: Separate configuration and enable Bjorn Helgaas
2022-09-09 20:25 ` [PATCH v4 4/9] PCI/PTM: Add pci_suspend_ptm() and pci_resume_ptm() Bjorn Helgaas
2022-09-09 23:44   ` Sathyanarayanan Kuppuswamy
2022-09-09 20:25 ` [PATCH v4 5/9] PCI/PTM: Move pci_ptm_info() body into its only caller Bjorn Helgaas
2022-09-09 23:45   ` Sathyanarayanan Kuppuswamy
2022-09-09 20:25 ` [PATCH v4 6/9] PCI/PTM: Preserve RsvdP bits in PTM Control register Bjorn Helgaas
2022-09-09 23:46   ` Sathyanarayanan Kuppuswamy [this message]
2022-09-09 20:25 ` [PATCH v4 7/9] PCI/PTM: Reorder functions in logical order Bjorn Helgaas
2022-09-09 20:25 ` [PATCH v4 8/9] PCI/PTM: Consolidate PTM interface declarations Bjorn Helgaas
2022-09-09 20:25 ` [PATCH v4 9/9] PCI/PM: Always disable PTM for all devices during suspend Bjorn Helgaas
2022-09-12  4:16 ` [PATCH v4 0/9] " Mika Westerberg
2022-09-12 20:36   ` Bjorn Helgaas
2022-09-13  8:13     ` Rafael J. Wysocki

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