* [RFC PATCH v2 06/11] ARM: OMAP4+: Adding the temperature sensor register set bit fields
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin, Keerthy
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
OMAP4460 specific temperature sensor register bit fields are added.
Existing OMAP4 entries are renamed to OMAP4430.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
---
arch/arm/mach-omap2/include/mach/control.h | 116 ++++++++++++++++++++++++++++
1 files changed, 116 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/control.h b/arch/arm/mach-omap2/include/mach/control.h
index cf42764..171b504 100644
--- a/arch/arm/mach-omap2/include/mach/control.h
+++ b/arch/arm/mach-omap2/include/mach/control.h
@@ -230,6 +230,122 @@
/* OMAP44xx control McBSP padconf */
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
+/* TEMP_SENSOR OMAP4430 */
+#define OMAP4430_BGAP_TEMPSOFF_SHIFT 12
+#define OMAP4430_BGAP_TEMPSOFF_MASK (1 << 12)
+#define OMAP4430_BGAP_TSHUT_SHIFT 11
+#define OMAP4430_BGAP_TSHUT_MASK (1 << 11)
+#define OMAP4430_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
+#define OMAP4430_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
+#define OMAP4430_BGAP_TEMP_SENSOR_SOC_SHIFT 9
+#define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
+#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
+#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
+#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
+#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
+
+/* TEMP_SENSOR OMAP4460 */
+#define OMAP4460_BGAP_TEMPSOFF_SHIFT 13
+#define OMAP4460_BGAP_TEMPSOFF_MASK (1 << 13)
+#define OMAP4460_BGAP_TEMP_SENSOR_SOC_SHIFT 11
+#define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK (1 << 11)
+#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_SHIFT 10
+#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 10)
+#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
+#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
+
+/* BANDGAP_CTRL */
+#define OMAP4460_SINGLE_MODE_SHIFT 31
+#define OMAP4460_SINGLE_MODE_MASK (1 << 31)
+#define OMAP4460_MASK_HOT_SHIFT 1
+#define OMAP4460_MASK_HOT_MASK (1 << 1)
+#define OMAP4460_MASK_COLD_SHIFT 0
+#define OMAP4460_MASK_COLD_MASK (1 << 0)
+
+/* BANDGAP_COUNTER */
+#define OMAP4460_COUNTER_SHIFT 0
+#define OMAP4460_COUNTER_MASK (0xffffff << 0)
+
+/* BANDGAP_THRESHOLD */
+#define OMAP4460_T_HOT_SHIFT 16
+#define OMAP4460_T_HOT_MASK (0x3ff << 16)
+#define OMAP4460_T_COLD_SHIFT 0
+#define OMAP4460_T_COLD_MASK (0x3ff << 0)
+
+/* TSHUT_THRESHOLD */
+#define OMAP4460_TSHUT_HOT_SHIFT 16
+#define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16)
+#define OMAP4460_TSHUT_COLD_SHIFT 0
+#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
+
+/* BANDGAP_STATUS */
+#define OMAP4460_CLEAN_STOP_SHIFT 3
+#define OMAP4460_CLEAN_STOP_MASK (1 << 3)
+#define OMAP4460_BGAP_ALERT_SHIFT 2
+#define OMAP4460_BGAP_ALERT_MASK (1 << 2)
+#define OMAP4460_HOT_FLAG_SHIFT 1
+#define OMAP4460_HOT_FLAG_MASK (1 << 1)
+#define OMAP4460_COLD_FLAG_SHIFT 0
+#define OMAP4460_COLD_FLAG_MASK (1 << 0)
+
+/* TEMP_SENSOR OMAP5430 */
+#define OMAP5430_BGAP_TEMP_SENSOR_SOC_SHIFT 12
+#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK (1 << 12)
+#define OMAP5430_BGAP_TEMPSOFF_SHIFT 11
+#define OMAP5430_BGAP_TEMPSOFF_MASK (1 << 11)
+#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_SHIFT 10
+#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 10)
+#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
+#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
+
+/* BANDGAP_CTRL */
+#define OMAP5430_MASK_HOT_CORE_SHIFT 5
+#define OMAP5430_MASK_HOT_CORE_MASK (1 << 5)
+#define OMAP5430_MASK_COLD_CORE_SHIFT 4
+#define OMAP5430_MASK_COLD_CORE_MASK (1 << 4)
+#define OMAP5430_MASK_HOT_MM_SHIFT 3
+#define OMAP5430_MASK_HOT_MM_MASK (1 << 3)
+#define OMAP5430_MASK_COLD_MM_SHIFT 2
+#define OMAP5430_MASK_COLD_MM_MASK (1 << 2)
+#define OMAP5430_MASK_HOT_MPU_SHIFT 1
+#define OMAP5430_MASK_HOT_MPU_MASK (1 << 1)
+#define OMAP5430_MASK_COLD_MPU_SHIFT 0
+#define OMAP5430_MASK_COLD_MPU_MASK (1 << 0)
+
+/* BANDGAP_COUNTER */
+#define OMAP5430_REPEAT_MODE_SHIFT 31
+#define OMAP5430_REPEAT_MODE_MASK (1 << 31)
+#define OMAP5430_COUNTER_SHIFT 0
+#define OMAP5430_COUNTER_MASK (0xffffff << 0)
+
+/* BANDGAP_THRESHOLD */
+#define OMAP5430_T_HOT_SHIFT 16
+#define OMAP5430_T_HOT_MASK (0x3ff << 16)
+#define OMAP5430_T_COLD_SHIFT 0
+#define OMAP5430_T_COLD_MASK (0x3ff << 0)
+
+/* TSHUT_THRESHOLD */
+#define OMAP5430_TSHUT_HOT_SHIFT 16
+#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
+#define OMAP5430_TSHUT_COLD_SHIFT 0
+#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
+
+/* BANDGAP_STATUS */
+#define OMAP5430_BGAP_ALERT_SHIFT 31
+#define OMAP5430_BGAP_ALERT_MASK (1 << 31)
+#define OMAP5430_HOT_CORE_FLAG_SHIFT 5
+#define OMAP5430_HOT_CORE_FLAG_MASK (1 << 5)
+#define OMAP5430_COLD_CORE_FLAG_SHIFT 4
+#define OMAP5430_COLD_CORE_FLAG_MASK (1 << 4)
+#define OMAP5430_HOT_MM_FLAG_SHIFT 3
+#define OMAP5430_HOT_MM_FLAG_MASK (1 << 3)
+#define OMAP5430_COLD_MM_FLAG_SHIFT 2
+#define OMAP5430_COLD_MM_FLAG_MASK (1 << 2)
+#define OMAP5430_HOT_MPU_FLAG_SHIFT 1
+#define OMAP5430_HOT_MPU_FLAG_MASK (1 << 1)
+#define OMAP5430_COLD_MPU_FLAG_SHIFT 0
+#define OMAP5430_COLD_MPU_FLAG_MASK (1 << 0)
+
/* AM35XX only CONTROL_GENERAL register offsets */
#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
--
1.7.7.1.488.ge8e1c
^ permalink raw reply related
* [RFC PATCH v2 05/11] mfd: omap: control: usb-phy: introduce the ctrl-module usb driver
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
Created a new platform driver for the platform device created by the
control module mfd core, wrt usb. This driver has API's to power on/off
the phy and the API's to write to musb mailbox.
Changes since previous version:
- Bandgap and usb phy: drivers are now independent from control module driver, they use their own API functions.
Dependency was removed from Kconfig.
- Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
(p.s. the mailbox for musb in omap4 is present in system control
module)
[kishon@ti.com: wrote the original API's related to USB functions]
Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
---
drivers/usb/otg/Kconfig | 12 ++
drivers/usb/otg/Makefile | 1
drivers/usb/otg/omap4-usb-phy.c | 167 ++++++++++++++++++++++++++++++++++++++
include/linux/usb/omap4_usb_phy.h | 53 ++++++++++++
4 files changed, 233 insertions(+)
Index: linux-2.6/drivers/usb/otg/Kconfig
===================================================================
--- linux-2.6.orig/drivers/usb/otg/Kconfig
+++ linux-2.6/drivers/usb/otg/Kconfig
@@ -78,6 +78,18 @@ config TWL6030_USB
are hooked to this driver through platform_data structure.
The definition of internal PHY APIs are in the mach-omap2 layer.
+config OMAP4_USB_PHY
+ tristate "Texas Instruments OMAP4+ USB pin control driver"
+ help
+ If you say yes here you get support for the Texas Instruments
+ OMAP4+ USB pin control driver. The register set is part of system
+ control module.
+
+ USB phy in OMAP configures control module register for powering on
+ the phy, configuring VBUSVALID, AVALID, IDDIG and SESSEND. For
+ performing the above mentioned configuration, API's are added in
+ by this children of the control module driver.
+
config NOP_USB_XCEIV
tristate "NOP USB Transceiver Driver"
select USB_OTG_UTILS
Index: linux-2.6/drivers/usb/otg/Makefile
===================================================================
--- linux-2.6.orig/drivers/usb/otg/Makefile
+++ linux-2.6/drivers/usb/otg/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_USB_GPIO_VBUS) += gpio_vbus
obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o
obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
obj-$(CONFIG_TWL6030_USB) += twl6030-usb.o
+obj-$(CONFIG_OMAP4_USB_PHY) += omap4-usb-phy.o
obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-xceiv.o
obj-$(CONFIG_USB_ULPI) += ulpi.o
obj-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi_viewport.o
Index: linux-2.6/drivers/usb/otg/omap4-usb-phy.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/usb/otg/omap4-usb-phy.c
@@ -0,0 +1,167 @@
+/*
+ * OMAP4 system control module driver, USB control children
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Contact:
+ * Kishon Vijay Abraham I <kishon@ti.com>
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/usb/omap4_usb_phy.h>
+
+void __iomem *omap_usb_phy_base;
+spinlock_t omap_usb_phy_lock;
+
+static int omap_usb_phy_readl(u32 reg, u32 *val)
+{
+ if (!omap_usb_phy_base)
+ return -EINVAL;
+
+ *val = __raw_readl(omap_usb_phy_base + reg);
+ return 0;
+}
+
+/*
+ * TODO: Get rid from omap_usb_phy_writel() return value -
+ * It's useless.
+ */
+static int omap_usb_phy_writel(u32 val, u32 reg)
+{
+ unsigned long flags;
+
+ if (!omap_usb_phy_base)
+ return -EINVAL;
+
+ spin_lock_irqsave(&omap_usb_phy_lock, flags);
+ __raw_writel(val, omap_usb_phy_base + reg);
+ spin_unlock_irqrestore(&omap_usb_phy_lock, flags);
+ return 0;
+}
+
+/**
+ * omap4_usb_phy_power - power on/off the phy using control module reg
+ * @dev: struct device *
+ * @on: 0 or 1, based on powering on or off the PHY
+ *
+ * omap_usb2 can call this API to power on or off the PHY.
+ */
+int omap4_usb_phy_power(struct device *dev, int on)
+{
+ u32 val;
+ int ret;
+
+ if (on) {
+ ret = omap_usb_phy_readl(CONTROL_DEV_CONF, &val);
+ if (!ret && (val & PHY_PD)) {
+ ret = omap_usb_phy_writel(~PHY_PD,
+ CONTROL_DEV_CONF);
+ /* XXX: add proper documentation for this delay */
+ mdelay(200);
+ }
+ } else
+ ret = omap_usb_phy_writel(PHY_PD, CONTROL_DEV_CONF);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(omap4_usb_phy_power);
+
+/**
+ * omap4_usb_phy_mailbox - write to usb otg mailbox
+ * @dev: struct device *
+ * @val: the value to be written to the mailbox
+ *
+ * On detection of a device (ID pin is grounded), the phy should call this API
+ * to set AVALID, VBUSVALID and ID pin is grounded.
+ *
+ * When OMAP is connected to a host (OMAP in device mode), the phy should call
+ * this API to set AVALID, VBUSVALID and ID pin in high impedance.
+ *
+ * The phy should call this API, if OMAP is disconnected from host or device.
+ */
+int omap4_usb_phy_mailbox(struct device *dev, u32 val)
+{
+ return omap_usb_phy_writel(val, CONTROL_USBOTGHS_CONTROL);
+}
+EXPORT_SYMBOL_GPL(omap4_usb_phy_mailbox);
+
+static int __devinit omap_usb_phy_probe(struct platform_device *pdev)
+{
+ struct resource *io_res;
+
+// printk("\n\t\t **** omap_usb_phy_probe(): enter ");
+
+ io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!io_res)
+ return -ENOENT;
+
+// printk("\n\t\t **** omap_usb_phy_probe(): start %x ", io_res->start);
+// printk("\n\t\t **** omap_usb_phy_probe(): size %x ", resource_size(io_res));
+ omap_usb_phy_base = ioremap(io_res->start, resource_size(io_res));
+// printk("\n\t\t **** omap_usb_phy_probe(): omap_usb_phy_base %x ", omap_usb_phy_base);
+ if (!omap_usb_phy_base)
+ return -ENOMEM;
+
+ /* Initialize register lock */
+ spin_lock_init(&omap_usb_phy_lock);
+
+ return 0;
+}
+
+static int __devexit omap_usb_phy_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id of_omap_usb_phy_match[] = {
+ { .compatible = "ti,omap4-usb-phy", },
+ { },
+};
+
+static struct platform_driver omap_usb_phy_driver = {
+ .probe = omap_usb_phy_probe,
+ .remove = __devexit_p(omap_usb_phy_remove),
+ .driver = {
+ .name = "omap4-usb-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_omap_usb_phy_match,
+ },
+};
+
+static int __init omap_usb_phy_init(void)
+{
+ return platform_driver_register(&omap_usb_phy_driver);
+}
+postcore_initcall(omap_usb_phy_init);
+
+static void __exit omap_usb_phy_exit(void)
+{
+ platform_driver_unregister(&omap_usb_phy_driver);
+}
+module_exit(omap_usb_phy_exit);
+
+MODULE_DESCRIPTION("OMAP4+ USB-phy driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform: omap4-usb-phy");
+MODULE_AUTHOR("Texas Instrument Inc.");
Index: linux-2.6/include/linux/usb/omap4_usb_phy.h
===================================================================
--- /dev/null
+++ linux-2.6/include/linux/usb/omap4_usb_phy.h
@@ -0,0 +1,53 @@
+/*
+ * OMAP4 USB-phy
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Contact:
+ * Kishon Vijay Abraham I <kishon@ti.com>
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP4_USB_PHY_H
+#define __OMAP4_USB_PHY_H
+
+#define PHY_PD 0x1
+#define AVALID BIT(0)
+#define BVALID BIT(1)
+#define VBUSVALID BIT(2)
+#define SESSEND BIT(3)
+#define IDDIG BIT(4)
+#define CONTROL_DEV_CONF 0x00000300
+#define CONTROL_USBOTGHS_CONTROL 0x0000033C
+
+/* USB-PHY helpers */
+#if (defined(CONFIG_OMAP4_USB_PHY)) || (defined(CONFIG_OMAP4_USB_PHY_MODULE))
+extern int omap4_usb_phy_mailbox(struct device *dev, u32 val);
+extern int omap4_usb_phy_power(struct device *dev, int on);
+#else
+static inline int omap4_usb_phy_mailbox(struct device *dev, u32 val)
+{
+ return 0;
+}
+static inline int omap4_usb_phy_power(struct device *dev, int on)
+{
+ return 0;
+}
+#endif
+
+#endif
^ permalink raw reply
* [RFC PATCH v2 04/11] OMAP2+: use control module mfd driver in omap_type
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
OMAP system control module can be probed early, then
omap_type is safe to use its APIs.
TODO: add support for other omap versions
Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
---
arch/arm/mach-omap2/id.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
Index: linux-2.6/arch/arm/mach-omap2/id.c
===================================================================
--- linux-2.6.orig/arch/arm/mach-omap2/id.c
+++ linux-2.6/arch/arm/mach-omap2/id.c
@@ -18,6 +18,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/mfd/omap_control.h>
#include <asm/cputype.h>
@@ -38,6 +39,8 @@ unsigned int omap_rev(void)
}
EXPORT_SYMBOL(omap_rev);
+u32 omap_control_readl(u16 offset);
+
int omap_type(void)
{
u32 val = 0;
@@ -49,7 +52,7 @@ int omap_type(void)
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
- val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+ val = omap_control_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
} else {
pr_err("Cannot detect omap type!\n");
goto out;
^ permalink raw reply
* [RFC PATCH v2 03/11] mfd: omap: control: core system control driver
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin, J Keerthy
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
This patch introduces a MFD core device driver for
OMAP system control module.
The control module allows software control of
various static modes supported by the device. It is
composed of two control submodules: general control
module and device (padconfiguration) control
module.
Changes since previous version:
- omap-control-core: driver is basically the same as arch/arm/mach-omap2/control.c, but resources aren't hardcoded, they are specified in dts file.
- omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
Probably, no configuration option is required!
- omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows
omap-control-core.c API to be called very early, for example from omap_type()
- omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
module device.
Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
---
Documentation/devicetree/bindings/mfd/omap_control.txt | 44 +++++
arch/arm/mach-omap2/Kconfig | 1
arch/arm/plat-omap/Kconfig | 4
drivers/mfd/Kconfig | 9 +
drivers/mfd/Makefile | 1
drivers/mfd/omap-control-core.c | 141 +++++++++++++++++
include/linux/mfd/omap_control.h | 70 ++++++++
7 files changed, 270 insertions(+)
Index: linux-2.6/Documentation/devicetree/bindings/mfd/omap_control.txt
===================================================================
--- /dev/null
+++ linux-2.6/Documentation/devicetree/bindings/mfd/omap_control.txt
@@ -0,0 +1,44 @@
+* Texas Instrument OMAP System Control Module (SCM) bindings
+
+The control module allows software control of various static modes supported by
+the device. The control module controls the settings of various device modules
+through register configuration and internal signals. It also controls the pad
+configuration, pin functional multiplexing, and the routing of internal signals
+(such as PRCM signals or DMA requests) to output pins configured for hardware
+observability.
+
+Required properties:
+- compatible : Should be:
+ - "ti,omap3-control" for OMAP3 support
+ - "ti,omap4-control" for OMAP4 support
+ - "ti,omap5-control" for OMAP5 support
+
+OMAP specific properties:
+- ti,hwmods: Name of the hwmod associated to the control module:
+ Should be "ctrl_module_core";
+
+Sub-nodes:
+- bandgap : contains the bandgap node
+
+ The bindings details of individual bandgap device can be found in:
+ Documentation/devicetree/bindings/thermal/omap_bandgap.txt
+
+- usb : contains the usb phy pin control node
+
+ The only required property for this child is:
+ - compatible = "ti,omap4-control-usb";
+
+Examples:
+
+ctrl_module_core: ctrl_module_core@4a002000 {
+ compatible = "ti,omap4-control";
+ ti,hwmods = "ctrl_module_core";
+ bandgap {
+ compatible = "ti,omap4460-bandgap";
+ interrupts = <0 126 4>; /* talert */
+ ti,tshut-gpio = <86>; /* tshut */
+ };
+ usb {
+ compatible = "ti,omap4-usb-phy";
+ };
+};
Index: linux-2.6/arch/arm/mach-omap2/Kconfig
===================================================================
--- linux-2.6.orig/arch/arm/mach-omap2/Kconfig
+++ linux-2.6/arch/arm/mach-omap2/Kconfig
@@ -52,6 +52,7 @@ config ARCH_OMAP4
select PL310_ERRATA_727915
select ARM_ERRATA_720789
select ARCH_HAS_OPP
+ select ARCH_HAS_CONTROL_MODULE
select PM_OPP if PM
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_CPU_SUSPEND if PM
Index: linux-2.6/arch/arm/plat-omap/Kconfig
===================================================================
--- linux-2.6.orig/arch/arm/plat-omap/Kconfig
+++ linux-2.6/arch/arm/plat-omap/Kconfig
@@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
config ARCH_OMAP_OTG
bool
+config ARCH_HAS_CONTROL_MODULE
+ bool
+ select MFD_OMAP_CONTROL
+
choice
prompt "OMAP System Type"
default ARCH_OMAP2PLUS
Index: linux-2.6/drivers/mfd/Kconfig
===================================================================
--- linux-2.6.orig/drivers/mfd/Kconfig
+++ linux-2.6/drivers/mfd/Kconfig
@@ -822,6 +822,15 @@ config MFD_WL1273_CORE
driver connects the radio-wl1273 V4L2 module and the wl1273
audio codec.
+config MFD_OMAP_CONTROL
+ bool "Texas Instruments OMAP System control module"
+ depends on ARCH_HAS_CONTROL_MODULE
+ help
+ This is the core driver for system control module. This driver
+ is responsible for creating the control module mfd child,
+ like USB-pin control, pin muxing, MMC-pbias and DDR IO dynamic
+ change for off mode.
+
config MFD_OMAP_USB_HOST
bool "Support OMAP USBHS core driver"
depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
Index: linux-2.6/drivers/mfd/Makefile
===================================================================
--- linux-2.6.orig/drivers/mfd/Makefile
+++ linux-2.6/drivers/mfd/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
obj-$(CONFIG_MFD_VX855) += vx855.o
obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
+obj-$(CONFIG_MFD_OMAP_CONTROL) += omap-control-core.o
obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
Index: linux-2.6/drivers/mfd/omap-control-core.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/mfd/omap-control-core.c
@@ -0,0 +1,141 @@
+/*
+ * OMAP system control module driver file
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Contacts:
+ * Based on original code written by:
+ * J Keerthy <j-keerthy@ti.com>
+ * Moiz Sonasath <m-sonasath@ti.com>
+ * MFD clean up and re-factoring:
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/omap_control.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+void __iomem *omap_control_base;
+
+void __iomem *omap_control_get(void)
+{
+ return omap_control_base;
+}
+
+u32 omap_control_readl(u16 offset)
+{
+ return __raw_readl(omap_control_base + (offset));
+}
+
+void omap_control_writel(u32 val, u16 offset)
+{
+ __raw_writel(val, omap_control_base + (offset));
+}
+
+static const struct of_device_id of_omap_control_match[] = {
+ { .compatible = "ti,omap3-control", },
+ { .compatible = "ti,omap4-control", },
+ { .compatible = "ti,omap5-control", },
+ { },
+};
+
+static int __devinit omap_control_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
+ /*
+ * Build child defvices of ctrl_module_core
+ */
+ return of_platform_populate(np, of_omap_control_match, NULL, dev);
+}
+
+
+static struct platform_driver omap_control_driver = {
+ .probe = omap_control_probe,
+ .driver = {
+ .name = "omap-control-core",
+ .owner = THIS_MODULE,
+ .of_match_table = of_omap_control_match,
+ },
+};
+
+int __init omap_control_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct resource res;
+
+ if (WARN_ON(!node))
+ return -ENODEV;
+
+ if (of_address_to_resource(node, 0, &res)) {
+ WARN(1, "unable to get intc registers\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+void __init of_omap_control_init(const struct of_device_id *matches)
+{
+ struct device_node *np;
+ struct property *pp = 0;
+ unsigned long phys_base = 0;
+ size_t mapsize = 0;
+
+ for_each_matching_node(np, matches) {
+
+ pp = of_find_property(np, "reg", NULL);
+ if(pp) {
+ phys_base = (unsigned long)be32_to_cpup(pp->value);
+ mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
+ omap_control_base = ioremap(phys_base, mapsize);
+ }
+ }
+}
+
+static int __init
+omap_control_early_initcall(void)
+{
+ of_omap_control_init(of_omap_control_match);
+
+ return 0;
+}
+early_initcall(omap_control_early_initcall);
+
+static int __init omap_control_init(void)
+{
+ return platform_driver_register(&omap_control_driver);
+}
+postcore_initcall_sync(omap_control_init);
+
+static void __exit omap_control_exit(void)
+{
+ platform_driver_unregister(&omap_control_driver);
+}
+module_exit(omap_control_exit);
+early_platform_init("early_omap_control", &omap_control_driver);
+
+MODULE_DESCRIPTION("OMAP system control module driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:omap-control-core");
+MODULE_AUTHOR("Texas Instruments Inc.");
Index: linux-2.6/include/linux/mfd/omap_control.h
===================================================================
--- /dev/null
+++ linux-2.6/include/linux/mfd/omap_control.h
@@ -0,0 +1,70 @@
+/*
+ * OMAP system control module header file
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact:
+ * J Keerthy <j-keerthy@ti.com>
+ * Moiz Sonasath <m-sonasath@ti.com>
+ * Abraham, Kishon Vijay <kishon@ti.com>
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_OMAP_CONTROL_H
+#define __DRIVERS_OMAP_CONTROL_H
+
+#include <linux/err.h>
+
+/**
+ * struct system control module - scm device structure
+ * @dev: device pointer
+ * @base: Base of the temp I/O
+ * @reg_lock: protect omap_control structure
+ * @use_count: track API users
+ */
+struct omap_control {
+ struct device *dev;
+ void __iomem *base;
+ /* protect this data structure and register access */
+ spinlock_t reg_lock;
+ int use_count;
+};
+
+/* TODO: Add helpers for 16bit and byte access */
+#ifdef CONFIG_MFD_OMAP_CONTROL
+void __iomem *omap_control_get(void);
+u32 omap_control_readl(u16 offset);
+void omap_control_writel(u32 val, u16 offset);
+
+extern void omap_control_put(struct device *dev);
+#else
+static inline int omap_control_readl(struct device *dev, u32 reg, u32 *val)
+{
+ return 0;
+}
+
+static inline int omap_control_writel(struct device *dev, u32 val, u32 reg)
+{
+ return 0;
+}
+
+static inline struct device *omap_control_get(void)
+{
+ return ERR_PTR(-EINVAL);
+}
+
+static inline void omap_control_put(struct device *dev)
+{
+}
+#endif
+
+#endif /* __DRIVERS_OMAP_CONTROL_H */
^ permalink raw reply
* [RFC PATCH v2 02/11] ARM: OMAP: expose control.h to mach area
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
This patch exposes the definitions under control.h to
drivers outside the machine code.
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
---
arch/arm/mach-omap2/am35xx-emac.c | 2 +-
arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-4430sdp.c | 2 +-
arch/arm/mach-omap2/board-am3517crane.c | 2 +-
arch/arm/mach-omap2/board-am3517evm.c | 2 +-
arch/arm/mach-omap2/board-apollon.c | 2 +-
arch/arm/mach-omap2/board-cm-t3517.c | 2 +-
arch/arm/mach-omap2/board-h4.c | 2 +-
arch/arm/mach-omap2/board-igep0020.c | 2 +-
arch/arm/mach-omap2/board-ldp.c | 2 +-
arch/arm/mach-omap2/board-omap3logic.c | 2 +-
arch/arm/mach-omap2/board-omap4panda.c | 2 +-
arch/arm/mach-omap2/board-omap4pcm049.c | 2 +-
arch/arm/mach-omap2/clock2420_data.c | 2 +-
arch/arm/mach-omap2/clock2430_data.c | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
arch/arm/mach-omap2/clock44xx_data.c | 2 +-
arch/arm/mach-omap2/common.c | 2 +-
arch/arm/mach-omap2/control.c | 2 +-
arch/arm/mach-omap2/cpuidle34xx.c | 2 +-
arch/arm/mach-omap2/devices.c | 2 +-
arch/arm/mach-omap2/display.c | 2 +-
arch/arm/mach-omap2/hsmmc.c | 2 +-
arch/arm/mach-omap2/id.c | 2 +-
arch/arm/mach-omap2/{ => include/mach}/control.h | 2 +-
arch/arm/mach-omap2/mcbsp.c | 2 +-
arch/arm/mach-omap2/mux.c | 2 +-
arch/arm/mach-omap2/omap_phy_internal.c | 2 +-
arch/arm/mach-omap2/opp3xxx_data.c | 2 +-
arch/arm/mach-omap2/opp4xxx_data.c | 2 +-
arch/arm/mach-omap2/pm24xx.c | 2 +-
arch/arm/mach-omap2/pm34xx.c | 2 +-
arch/arm/mach-omap2/prcm.c | 2 +-
arch/arm/mach-omap2/serial.c | 2 +-
arch/arm/mach-omap2/sleep34xx.S | 2 +-
arch/arm/mach-omap2/sr_device.c | 2 +-
arch/arm/mach-omap2/usb-fs.c | 2 +-
arch/arm/mach-omap2/voltage.c | 2 +-
38 files changed, 38 insertions(+), 38 deletions(-)
rename arch/arm/mach-omap2/{ => include/mach}/control.h (99%)
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 447682c..c3da28a 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -21,7 +21,7 @@
#include <plat/irqs.h>
#include <mach/am35xx.h>
-#include "control.h"
+#include <mach/control.h>
static struct mdio_platform_data am35xx_emac_mdio_pdata;
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 37abb0d..ad1132b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -46,7 +46,7 @@
#include "sdram-qimonda-hyb18m512160af-6.h"
#include "hsmmc.h"
#include "pm.h"
-#include "control.h"
+#include <mach/control.h>
#include "common-board-devices.h"
#define CONFIG_DISABLE_HFCLK 1
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 94af6cd..8f7f76b 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -47,7 +47,7 @@
#include "mux.h"
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#include "common-board-devices.h"
#define ETH_KS8851_IRQ 34
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 3b8a53c..2ad514d 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -32,7 +32,7 @@
#include "am35xx-emac.h"
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#define GPIO_USB_POWER 35
#define GPIO_USB_NRESET 38
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 99790eb..bef6586 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -41,7 +41,7 @@
#include "am35xx-emac.h"
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#include "hsmmc.h"
#define LCD_PANEL_PWR 176
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 768ece2..bd04fe2 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -44,7 +44,7 @@
#include <video/omap-panel-generic-dpi.h>
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
/* LED & Switch macros */
#define LED0_GPIO13 13
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 9e66e16..1d2b7a3 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -47,7 +47,7 @@
#include <mach/am35xx.h>
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#include "common-board-devices.h"
#include "am35xx-emac.h"
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0bbbabe..623a231 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -43,7 +43,7 @@
#include <video/omap-panel-generic-dpi.h>
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#define H4_FLASH_CS 0
#define H4_SMC91X_CS 1
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 7a27409..ebef044 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -42,7 +42,7 @@
#include "sdram-numonyx-m65kxxxxam.h"
#include "common-board-devices.h"
#include "board-flash.h"
-#include "control.h"
+#include <mach/control.h>
#define IGEP2_SMSC911X_CS 5
#define IGEP2_SMSC911X_GPIO 176
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 1b60495..6383a76 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -50,7 +50,7 @@
#include "board-flash.h"
#include "mux.h"
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#include "common-board-devices.h"
#define LDP_SMSC911X_CS 1
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index c008bf8..ca3e075 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -37,7 +37,7 @@
#include "mux.h"
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#include "common-board-devices.h"
#include <plat/mux.h>
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 847a857..b1c8517 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -45,7 +45,7 @@
#include <video/omap-panel-tfp410.h>
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#include "mux.h"
#include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/board-omap4pcm049.c b/arch/arm/mach-omap2/board-omap4pcm049.c
index a95f426..101e984 100644
--- a/arch/arm/mach-omap2/board-omap4pcm049.c
+++ b/arch/arm/mach-omap2/board-omap4pcm049.c
@@ -48,7 +48,7 @@
#include "common.h"
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#include "mux.h"
#include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index bace930..f350e96 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -30,7 +30,7 @@
#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
-#include "control.h"
+#include <mach/control.h>
#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 3b4d09a..dd08bcb 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -29,7 +29,7 @@
#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
-#include "control.h"
+#include <mach/control.h>
#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 4e1a3b0..694625f 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -34,7 +34,7 @@
#include "cm-regbits-34xx.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
-#include "control.h"
+#include <mach/control.h>
/*
* clocks
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2172f66..ce11ee4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -39,7 +39,7 @@
#include "cm-regbits-44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
-#include "control.h"
+#include <mach/control.h>
#include "scrm44xx.h"
/* OMAP4 modulemode control */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8a6953a..3dc94d0 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -25,7 +25,7 @@
#include "iomap.h"
#include "common.h"
#include "sdrc.h"
-#include "control.h"
+#include <mach/control.h>
/* Global address base setup code */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 08e674b..92e35bf 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -26,7 +26,7 @@
#include "cm2xxx_3xxx.h"
#include "sdrc.h"
#include "pm.h"
-#include "control.h"
+#include <mach/control.h>
/* Used by omap3_ctrl_save_padconf() */
#define START_PADCONF_SAVE 0x2
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 207bc1c..7d82c6bb 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -33,7 +33,7 @@
#include "clockdomain.h"
#include "pm.h"
-#include "control.h"
+#include <mach/control.h>
#include "common.h"
#ifdef CONFIG_CPU_IDLE
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b932..152c266 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -34,7 +34,7 @@
#include <plat/omap4-keypad.h>
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#include "devices.h"
#define L3_MODULES_MAX_LEN 12
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index db5a88a..0681407 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -32,7 +32,7 @@
#include "iomap.h"
#include "mux.h"
-#include "control.h"
+#include <mach/control.h>
#include "display.h"
#define DISPC_CONTROL 0x0040
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index be697d4..33b3d62 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -22,7 +22,7 @@
#include "mux.h"
#include "hsmmc.h"
-#include "control.h"
+#include <mach/control.h>
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0389b32..5bb9746 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -26,7 +26,7 @@
#include <mach/id.h>
-#include "control.h"
+#include <mach/control.h>
static unsigned int omap_revision;
static const char *cpu_rev;
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/include/mach/control.h
similarity index 99%
rename from arch/arm/mach-omap2/control.h
rename to arch/arm/mach-omap2/include/mach/control.h
index dad2903..cf42764 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/include/mach/control.h
@@ -1,5 +1,5 @@
/*
- * arch/arm/mach-omap2/control.h
+ * arch/arm/mach-omap2/include/mach/control.h
*
* OMAP2/3/4 System Control Module definitions
*
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77..0367035 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,7 +25,7 @@
#include <plat/omap_device.h>
#include <linux/pm_runtime.h>
-#include "control.h"
+#include <mach/control.h>
/*
* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 3268ee2..f23e6618 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -38,7 +38,7 @@
#include <plat/omap_hwmod.h>
-#include "control.h"
+#include <mach/control.h>
#include "mux.h"
#include "prm.h"
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 4c90477..b2c9253 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -29,7 +29,7 @@
#include <linux/usb.h>
#include <plat/usb.h>
-#include "control.h"
+#include <mach/control.h>
/* OMAP control module register for UTMI PHY */
#define CONTROL_DEV_CONF 0x300
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index d95f3f9..6dafdbb 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -21,7 +21,7 @@
#include <plat/cpu.h>
-#include "control.h"
+#include <mach/control.h>
#include "omap_opp_data.h"
#include "pm.h"
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba2..27f823c 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -22,7 +22,7 @@
#include <plat/cpu.h>
-#include "control.h"
+#include <mach/control.h>
#include "omap_opp_data.h"
#include "pm.h"
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index facfffc..7ebca30 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -49,7 +49,7 @@
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
-#include "control.h"
+#include <mach/control.h>
#include "powerdomain.h"
#include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8b43aef..1d2a51c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -49,7 +49,7 @@
#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "sdrc.h"
-#include "control.h"
+#include <mach/control.h>
/* pm34xx errata defined in pm.h */
u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 480f40a..fff0b09 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -37,7 +37,7 @@
#include "prminst44xx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-44xx.h"
-#include "control.h"
+#include <mach/control.h>
void __iomem *prm_base;
void __iomem *cm_base;
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 678dd1d..97b09da5 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -39,7 +39,7 @@
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
-#include "control.h"
+#include <mach/control.h>
#include "mux.h"
/*
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 1f62f23..b3f6bfc 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -33,7 +33,7 @@
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#include "sdrc.h"
-#include "control.h"
+#include <mach/control.h>
/*
* Registers access definitions
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index a503e1e..48a01f6 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -26,7 +26,7 @@
#include "smartreflex.h"
#include "voltage.h"
-#include "control.h"
+#include <mach/control.h>
#include "pm.h"
static bool sr_enable_on_init;
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index 1481078..94d471c 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -32,7 +32,7 @@
#include <plat/usb.h>
#include <plat/board.h>
-#include "control.h"
+#include <mach/control.h>
#include "mux.h"
#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4dc60e8..d2f0644 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -34,7 +34,7 @@
#include "prm44xx.h"
#include "prcm44xx.h"
#include "prminst44xx.h"
-#include "control.h"
+#include <mach/control.h>
#include "voltage.h"
#include "powerdomain.h"
-- 1.7.7.1.488.ge8e1c
^ permalink raw reply related
* [RFC PATCH v2 01/11] ARM: OMAP4: Remove un-used control module headers and defines.
From: Konstantin Baydarov @ 2012-06-18 11:32 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: amit.kucheria, Eduardo Valentin, balbi, linux-pm, linux-omap,
linux-arm-kernel, amit.kachhap
In-Reply-To: <1337934361-1606-1-git-send-email-eduardo.valentin@ti.com>
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Most of the OMAP4 control module register defines are not used and
can be removed. Keep only needed defines and move them to common
control module header just like other OMAP versions.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
---
arch/arm/mach-omap2/control.h | 45 +-
.../include/mach/ctrl_module_core_44xx.h | 391 ------
.../include/mach/ctrl_module_pad_core_44xx.h | 1409 --------------------
.../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ----
.../include/mach/ctrl_module_wkup_44xx.h | 92 --
5 files changed, 40 insertions(+), 2133 deletions(-)
delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd0..dad2903 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,11 +16,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
-#include <mach/ctrl_module_core_44xx.h>
-#include <mach/ctrl_module_wkup_44xx.h>
-#include <mach/ctrl_module_pad_core_44xx.h>
-#include <mach/ctrl_module_pad_wkup_44xx.h>
-
#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -183,6 +178,43 @@
#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
+/* OMAP4 IDCODE CONTROL */
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
+#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
+
+/* CONTROL_I2C_1 */
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
+
+/* DSI CONTROL_DSIPHY */
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
+#define OMAP4_DSI2_LANEENABLE_SHIFT 29
+#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT 24
+#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT 19
+#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT 14
+#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
+
+/* CONTROL_PBIASLITE */
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
+#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
+
+/* CONTROL_MMC1 */
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
+
/* OMAP44xx control efuse offsets */
#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
#define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
@@ -195,6 +227,9 @@
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
+/* OMAP44xx control McBSP padconf */
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
+
/* AM35XX only CONTROL_GENERAL register offsets */
#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
deleted file mode 100644
index 2f7ac70..0000000
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_CORE registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_CORE 0x4a002000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
-#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
-#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
-#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
-#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
-#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
-#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
-#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
-#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
-#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT 30
-#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT 16
-#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT 11
-#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT 8
-#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT 6
-#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT 0
-#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT 0
-#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
-
-/* STD_FUSE_DIE_ID_0 */
-#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
-#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
-
-/* ID_CODE */
-#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
-#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_1 */
-#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
-#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_2 */
-#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
-#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_3 */
-#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
-#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_0 */
-#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
-#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_1 */
-#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
-#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
-
-/* STD_FUSE_USB_CONF */
-#define OMAP4_USB_PROD_ID_SHIFT 16
-#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
-#define OMAP4_USB_VENDOR_ID_SHIFT 0
-#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
-
-/* STD_FUSE_OPP_VDD_WKUP */
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
-
-/* STD_FUSE_OPP_BGAP */
-#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
-#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_0 */
-#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
-#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_1 */
-#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
-#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
-
-/* STATUS */
-#define OMAP4_ATTILA_CONF_SHIFT 11
-#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
-#define OMAP4_DEVICE_TYPE_SHIFT 8
-#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
-#define OMAP4_SYS_BOOT_SHIFT 0
-#define OMAP4_SYS_BOOT_MASK (0xff << 0)
-
-/* DEV_CONF */
-#define OMAP4_DEV_CONF_SHIFT 1
-#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
-#define OMAP4_USBPHY_PD_SHIFT 0
-#define OMAP4_USBPHY_PD_MASK (1 << 0)
-
-/* LDOVBB_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
-
-/* LDOVBB_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
-
-/* LDOSRAM_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
-
-/* LDOSRAM_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
-
-/* LDOSRAM_CORE_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
-
-/* TEMP_SENSOR */
-#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
-#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
-#define OMAP4_BGAP_TSHUT_SHIFT 11
-#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
-
-/* DPLL_NWELL_TRIM_0 */
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
-#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
-#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
-#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
-
-/* DPLL_NWELL_TRIM_1 */
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
-#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
-#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
-
-/* USBOTGHS_CONTROL */
-#define OMAP4_DISCHRGVBUS_SHIFT 8
-#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
-#define OMAP4_CHRGVBUS_SHIFT 7
-#define OMAP4_CHRGVBUS_MASK (1 << 7)
-#define OMAP4_DRVVBUS_SHIFT 6
-#define OMAP4_DRVVBUS_MASK (1 << 6)
-#define OMAP4_IDPULLUP_SHIFT 5
-#define OMAP4_IDPULLUP_MASK (1 << 5)
-#define OMAP4_IDDIG_SHIFT 4
-#define OMAP4_IDDIG_MASK (1 << 4)
-#define OMAP4_SESSEND_SHIFT 3
-#define OMAP4_SESSEND_MASK (1 << 3)
-#define OMAP4_VBUSVALID_SHIFT 2
-#define OMAP4_VBUSVALID_MASK (1 << 2)
-#define OMAP4_BVALID_SHIFT 1
-#define OMAP4_BVALID_MASK (1 << 1)
-#define OMAP4_AVALID_SHIFT 0
-#define OMAP4_AVALID_MASK (1 << 0)
-
-/* DSS_CONTROL */
-#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
-#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
-
-/* HWOBS_CONTROL */
-#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
-#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
-#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
-#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
-#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
-#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
-#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
-#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
-
-/* DEBOBS_FINAL_MUX_SEL */
-#define OMAP4_SELECT_SHIFT 0
-#define OMAP4_SELECT_MASK (0xffffffff << 0)
-
-/* DEBOBS_MMR_MPU */
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
-
-/* CONF_SDMA_REQ_SEL0 */
-#define OMAP4_MULT_SHIFT 0
-#define OMAP4_MULT_MASK (0x7f << 0)
-
-/* CONF_CLK_SEL0 */
-#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
-#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
-
-/* CONF_CLK_SEL1 */
-#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
-#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
-
-/* CONF_CLK_SEL2 */
-#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
-#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
-
-/* CONF_DPLL_FREQLOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
-
-/* CONF_DPLL_TINITZ_SEL */
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
-
-/* CONF_DPLL_PHASELOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
-
-/* CONF_DEBUG_SEL_TST_0 */
-#define OMAP4_MODE_SHIFT 0
-#define OMAP4_MODE_MASK (0xf << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
deleted file mode 100644
index c88420d..0000000
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ /dev/null
@@ -1,1409 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
-#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
-#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
-#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
-#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT 30
-#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT 16
-#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT 11
-#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT 8
-#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT 6
-#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT 0
-#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT 0
-#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
-
-/* PADCONF_WAKEUPEVENT_0 */
-#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_1 */
-#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_2 */
-#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_3 */
-#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_4 */
-#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_5 */
-#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
-#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
-#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
-#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
-#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
-#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
-#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
-#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
-#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
-#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
-#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
-#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
-#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
-#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
-#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* PADCONF_WAKEUPEVENT_6 */
-#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* CONTROL_PADCONF_GLOBAL */
-#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
-#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
-
-/* CONTROL_PADCONF_MODE */
-#define OMAP4_VDDS_DV_BANK0_SHIFT 31
-#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
-#define OMAP4_VDDS_DV_BANK1_SHIFT 30
-#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
-#define OMAP4_VDDS_DV_BANK3_SHIFT 29
-#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
-#define OMAP4_VDDS_DV_BANK4_SHIFT 28
-#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
-#define OMAP4_VDDS_DV_BANK5_SHIFT 27
-#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
-#define OMAP4_VDDS_DV_BANK6_SHIFT 26
-#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
-#define OMAP4_VDDS_DV_C2C_SHIFT 25
-#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
-#define OMAP4_VDDS_DV_CAM_SHIFT 24
-#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
-#define OMAP4_VDDS_DV_GPMC_SHIFT 23
-#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
-#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
-#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
-
-/* CONTROL_SMART1IO_PADCONF_0 */
-#define OMAP4_ABE_DR0_SC_SHIFT 30
-#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
-#define OMAP4_CAM_DR0_SC_SHIFT 28
-#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
-#define OMAP4_FREF_DR2_SC_SHIFT 26
-#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
-#define OMAP4_FREF_DR3_SC_SHIFT 24
-#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
-#define OMAP4_GPIO_DR8_SC_SHIFT 22
-#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
-#define OMAP4_GPIO_DR9_SC_SHIFT 20
-#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
-#define OMAP4_GPMC_DR2_SC_SHIFT 18
-#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
-#define OMAP4_GPMC_DR3_SC_SHIFT 16
-#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
-#define OMAP4_GPMC_DR6_SC_SHIFT 14
-#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
-#define OMAP4_HDMI_DR0_SC_SHIFT 12
-#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
-#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
-#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
-#define OMAP4_UART1_DR0_SC_SHIFT 8
-#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
-#define OMAP4_UART3_DR0_SC_SHIFT 6
-#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
-#define OMAP4_UART3_DR1_SC_SHIFT 4
-#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
-#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
-#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
-#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
-#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
-
-/* CONTROL_SMART1IO_PADCONF_1 */
-#define OMAP4_ABE_DR0_LB_SHIFT 30
-#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
-#define OMAP4_CAM_DR0_LB_SHIFT 28
-#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
-#define OMAP4_FREF_DR2_LB_SHIFT 26
-#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
-#define OMAP4_FREF_DR3_LB_SHIFT 24
-#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
-#define OMAP4_GPIO_DR8_LB_SHIFT 22
-#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
-#define OMAP4_GPIO_DR9_LB_SHIFT 20
-#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
-#define OMAP4_GPMC_DR2_LB_SHIFT 18
-#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
-#define OMAP4_GPMC_DR3_LB_SHIFT 16
-#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
-#define OMAP4_GPMC_DR6_LB_SHIFT 14
-#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
-#define OMAP4_HDMI_DR0_LB_SHIFT 12
-#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
-#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
-#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
-#define OMAP4_UART1_DR0_LB_SHIFT 8
-#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
-#define OMAP4_UART3_DR0_LB_SHIFT 6
-#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
-#define OMAP4_UART3_DR1_LB_SHIFT 4
-#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
-#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
-#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
-#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
-#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
-
-/* CONTROL_SMART2IO_PADCONF_0 */
-#define OMAP4_C2C_DR0_LB_SHIFT 31
-#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
-#define OMAP4_DPM_DR1_LB_SHIFT 30
-#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
-#define OMAP4_DPM_DR2_LB_SHIFT 29
-#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
-#define OMAP4_DPM_DR3_LB_SHIFT 28
-#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
-#define OMAP4_GPIO_DR0_LB_SHIFT 27
-#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
-#define OMAP4_GPIO_DR1_LB_SHIFT 26
-#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
-#define OMAP4_GPIO_DR10_LB_SHIFT 25
-#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
-#define OMAP4_GPIO_DR2_LB_SHIFT 24
-#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
-#define OMAP4_GPMC_DR0_LB_SHIFT 23
-#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
-#define OMAP4_GPMC_DR1_LB_SHIFT 22
-#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
-#define OMAP4_GPMC_DR4_LB_SHIFT 21
-#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
-#define OMAP4_GPMC_DR5_LB_SHIFT 20
-#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
-#define OMAP4_GPMC_DR7_LB_SHIFT 19
-#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
-#define OMAP4_HSI2_DR0_LB_SHIFT 18
-#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
-#define OMAP4_HSI2_DR1_LB_SHIFT 17
-#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
-#define OMAP4_HSI2_DR2_LB_SHIFT 16
-#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
-#define OMAP4_KPD_DR0_LB_SHIFT 15
-#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
-#define OMAP4_KPD_DR1_LB_SHIFT 14
-#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
-#define OMAP4_PDM_DR0_LB_SHIFT 13
-#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
-#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
-#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
-#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
-#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
-#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
-#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
-#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
-#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
-#define OMAP4_SPI3_DR0_LB_SHIFT 8
-#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
-#define OMAP4_SPI3_DR1_LB_SHIFT 7
-#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
-#define OMAP4_UART3_DR2_LB_SHIFT 6
-#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
-#define OMAP4_UART3_DR3_LB_SHIFT 5
-#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
-#define OMAP4_UART3_DR4_LB_SHIFT 4
-#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
-#define OMAP4_UART3_DR5_LB_SHIFT 3
-#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
-#define OMAP4_USBA0_DR1_LB_SHIFT 2
-#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
-#define OMAP4_USBA_DR2_LB_SHIFT 1
-#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
-
-/* CONTROL_SMART2IO_PADCONF_1 */
-#define OMAP4_USBB1_DR0_LB_SHIFT 31
-#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
-#define OMAP4_USBB2_DR0_LB_SHIFT 30
-#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
-#define OMAP4_USBA0_DR0_LB_SHIFT 29
-#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
-
-/* CONTROL_SMART3IO_PADCONF_0 */
-#define OMAP4_DMIC_DR0_MB_SHIFT 30
-#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
-#define OMAP4_GPIO_DR3_MB_SHIFT 28
-#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
-#define OMAP4_GPIO_DR4_MB_SHIFT 26
-#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
-#define OMAP4_GPIO_DR5_MB_SHIFT 24
-#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
-#define OMAP4_GPIO_DR6_MB_SHIFT 22
-#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
-#define OMAP4_HSI_DR1_MB_SHIFT 20
-#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
-#define OMAP4_HSI_DR2_MB_SHIFT 18
-#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
-#define OMAP4_HSI_DR3_MB_SHIFT 16
-#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
-#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
-#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
-#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
-#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
-#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
-#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
-#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
-#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
-#define OMAP4_SPI2_DR0_MB_SHIFT 0
-#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
-
-/* CONTROL_SMART3IO_PADCONF_1 */
-#define OMAP4_SPI2_DR1_MB_SHIFT 30
-#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
-#define OMAP4_SPI2_DR2_MB_SHIFT 28
-#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
-#define OMAP4_UART2_DR0_MB_SHIFT 26
-#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
-#define OMAP4_UART2_DR1_MB_SHIFT 24
-#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
-#define OMAP4_UART4_DR0_MB_SHIFT 22
-#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
-#define OMAP4_HSI_DR0_MB_SHIFT 20
-#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
-
-/* CONTROL_SMART3IO_PADCONF_2 */
-#define OMAP4_DMIC_DR0_LB_SHIFT 31
-#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
-#define OMAP4_GPIO_DR3_LB_SHIFT 30
-#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
-#define OMAP4_GPIO_DR4_LB_SHIFT 29
-#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
-#define OMAP4_GPIO_DR5_LB_SHIFT 28
-#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
-#define OMAP4_GPIO_DR6_LB_SHIFT 27
-#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
-#define OMAP4_HSI_DR1_LB_SHIFT 26
-#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
-#define OMAP4_HSI_DR2_LB_SHIFT 25
-#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
-#define OMAP4_HSI_DR3_LB_SHIFT 24
-#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
-#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
-#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
-#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
-#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
-#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
-#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
-#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
-#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
-#define OMAP4_SPI2_DR0_LB_SHIFT 16
-#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
-#define OMAP4_SPI2_DR1_LB_SHIFT 15
-#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
-#define OMAP4_SPI2_DR2_LB_SHIFT 14
-#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
-#define OMAP4_UART2_DR0_LB_SHIFT 13
-#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
-#define OMAP4_UART2_DR1_LB_SHIFT 12
-#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
-#define OMAP4_UART4_DR0_LB_SHIFT 11
-#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
-#define OMAP4_HSI_DR0_LB_SHIFT 10
-#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
-
-/* CONTROL_USBB_HSIC */
-#define OMAP4_USBB2_DR1_SR_SHIFT 30
-#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
-#define OMAP4_USBB2_DR1_I_SHIFT 27
-#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
-#define OMAP4_USBB1_DR1_SR_SHIFT 25
-#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
-#define OMAP4_USBB1_DR1_I_SHIFT 22
-#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
-#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
-#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
-#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
-#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
-#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
-#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
-#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
-#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
-#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
-#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
-#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
-#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
-
-/* CONTROL_SLIMBUS */
-#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
-#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
-#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
-#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
-#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
-#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
-#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
-#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
-#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
-#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
-#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
-#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
-#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
-#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
-#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
-#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
-
-/* CONTROL_PBIASLITE */
-#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
-#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
-#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
-#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
-#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
-#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
-#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
-#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
-#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
-#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
-#define OMAP4_MMC1_PWRDNZ_SHIFT 26
-#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
-#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
-#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
-#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
-#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
-
-/* CONTROL_I2C_0 */
-#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
-#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
-#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
-#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
-#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
-#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
-#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
-#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
-#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
-#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
-#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
-#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
-#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
-#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
-#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
-#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
-#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
-#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
-#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
-#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
-#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
-#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
-#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
-#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
-#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
-#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
-#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
-#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
-#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
-#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
-#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
-#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
-#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
-#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
-#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
-#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
-#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
-#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
-#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
-#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
-#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
-#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
-#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
-#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
-#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
-#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
-#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
-#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
-
-/* CONTROL_CAMERA_RX */
-#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
-#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
-#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
-#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
-#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
-#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
-#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
-#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
-#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
-#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
-#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
-#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
-#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
-#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
-#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
-#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
-
-/* CONTROL_AVDAC */
-#define OMAP4_AVDAC_ACEN_SHIFT 31
-#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
-#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
-#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
-#define OMAP4_AVDAC_INPUTINV_SHIFT 29
-#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
-#define OMAP4_AVDAC_CTL_SHIFT 13
-#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
-#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
-#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
-
-/* CONTROL_HDMI_TX_PHY */
-#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
-#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
-#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
-#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
-#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
-#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
-#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
-#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
-
-/* CONTROL_MMC2 */
-#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
-#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
-
-/* CONTROL_DSIPHY */
-#define OMAP4_DSI2_LANEENABLE_SHIFT 29
-#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
-#define OMAP4_DSI1_LANEENABLE_SHIFT 24
-#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
-#define OMAP4_DSI1_PIPD_SHIFT 19
-#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
-#define OMAP4_DSI2_PIPD_SHIFT 14
-#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
-
-/* CONTROL_MCBSPLP */
-#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
-#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
-#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
-#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
-#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
-#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
-
-/* CONTROL_USB2PHYCORE */
-#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
-#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
-#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
-#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
-#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
-#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
-#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
-#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
-#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
-#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
-#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
-#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
-#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
-#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
-#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
-#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
-#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
-#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
-#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
-#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
-#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
-#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
-#define OMAP4_USB2PHY_DATADET_SHIFT 18
-#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
-#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
-#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
-#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
-#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
-#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
-#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
-#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
-#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
-#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
-#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
-#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
-#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
-#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
-#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
-#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
-#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
-#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
-#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
-#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
-#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
-#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
-#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
-#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
-#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
-#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
-#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
-
-/* CONTROL_I2C_1 */
-#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
-#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
-#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
-#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
-#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
-#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
-#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
-#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
-#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
-#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
-#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
-#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
-#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
-#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
-#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
-#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
-#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
-#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
-#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
-#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
-
-/* CONTROL_MMC1 */
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
-#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
-#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
-#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
-#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
-#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
-#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
-#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
-#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
-#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
-#define OMAP4_USB_FD_CDEN_SHIFT 23
-#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
-#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
-#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
-#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
-#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
-
-/* CONTROL_HSI */
-#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
-#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
-#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
-#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
-#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
-#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
-#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
-#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
-
-/* CONTROL_USB */
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
-#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
-
-/* CONTROL_HDQ */
-#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
-#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
-
-/* CONTROL_LPDDR2IO1_0 */
-#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
-#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
-#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
-#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
-#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
-#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
-#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
-#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
-#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
-#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
-#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
-#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
-#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
-#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
-#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
-#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
-
-/* CONTROL_LPDDR2IO1_1 */
-#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
-#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
-#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
-#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
-#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
-#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
-#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
-#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
-#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
-#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
-#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
-#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
-#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
-#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
-#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
-#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
-
-/* CONTROL_LPDDR2IO1_2 */
-#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
-#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
-#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
-#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
-#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
-#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
-#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
-#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
-#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
-#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
-
-/* CONTROL_LPDDR2IO1_3 */
-#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
-#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
-#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
-#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
-#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
-#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
-#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
-#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
-#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
-#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
-#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
-#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
-#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
-#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
-#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
-#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
-#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
-#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
-#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
-#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
-#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
-#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
-
-/* CONTROL_LPDDR2IO2_0 */
-#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
-#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
-#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
-#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
-#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
-#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
-#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
-#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
-#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
-#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
-#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
-#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
-#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
-#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
-#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
-#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
-
-/* CONTROL_LPDDR2IO2_1 */
-#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
-#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
-#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
-#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
-#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
-#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
-#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
-#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
-#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
-#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
-#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
-#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
-#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
-#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
-#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
-#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
-
-/* CONTROL_LPDDR2IO2_2 */
-#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
-#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
-#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
-#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
-#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
-#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
-#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
-#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
-#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
-#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
-#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
-#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
-#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
-#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
-#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
-#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
-#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
-#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
-
-/* CONTROL_LPDDR2IO2_3 */
-#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
-#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
-#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
-#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
-#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
-#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
-#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
-#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
-#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
-#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
-#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
-#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
-#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
-#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
-#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
-#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
-#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
-#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
-#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
-#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
-#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
-#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
-
-/* CONTROL_BUS_HOLD */
-#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
-#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
-#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
-#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
-
-/* CONTROL_C2C */
-#define OMAP4_MIRROR_MODE_EN_SHIFT 31
-#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
-#define OMAP4_C2C_SPARE_SHIFT 24
-#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
-
-/* CORE_CONTROL_SPARE_RW */
-#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
-#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
-
-/* CORE_CONTROL_SPARE_R */
-#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
-#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
-
-/* CORE_CONTROL_SPARE_R_C0 */
-#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
-#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
-#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
-#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
-#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
-#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
-#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
-#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
-#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
-#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
-#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
-#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
-#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
-#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
-#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
-#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
-
-/* CONTROL_EFUSE_1 */
-#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
-#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
-#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
-#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
-#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
-#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
-#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
-#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
-
-/* CONTROL_EFUSE_2 */
-#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
-#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
-#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
-#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
-#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
-#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
-#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
-#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
-#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
-#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
-#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
-#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
-#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
-#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
-#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
-#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
-#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
-#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
-#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
-#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
-#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
-#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
-#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
-#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
-#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
-#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
-#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
-#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
-#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
-#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
-#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
-#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
-#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
-#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
-#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
-#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
-
-/* CONTROL_EFUSE_3 */
-#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
-#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
-#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
-#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
-#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
-#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
-#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
-#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
-
-/* CONTROL_EFUSE_4 */
-#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
-#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
-#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
-#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
-#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
-#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
-#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
-#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
deleted file mode 100644
index 17c9b37..0000000
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
-#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
-#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
-#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
-#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT 30
-#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT 16
-#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT 11
-#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT 8
-#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT 6
-#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT 0
-#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT 0
-#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
-
-/* PADCONF_WAKEUPEVENT_0 */
-#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
-#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
-#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
-#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
-#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
-#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
-#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
-#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
-#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
-#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
-#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
-#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
-#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
-#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
-#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
-#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
-#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
-#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
-#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
-#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
-#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
-#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
-#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
-#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
-#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
-#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
-#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
-#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
-#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
-#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
-#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
-#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
-#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
-#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
-#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
-#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
-#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
-#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
-#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
-#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
-#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
-#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
-#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
-#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
-#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
-#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
-#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
-#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
-#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
-#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
-
-/* CONTROL_SMART1NOPMIO_PADCONF_0 */
-#define OMAP4_FREF_DR0_SC_SHIFT 30
-#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
-#define OMAP4_FREF_DR1_SC_SHIFT 28
-#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
-#define OMAP4_FREF_DR4_SC_SHIFT 26
-#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
-#define OMAP4_FREF_DR5_SC_SHIFT 24
-#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
-#define OMAP4_FREF_DR6_SC_SHIFT 22
-#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
-#define OMAP4_FREF_DR7_SC_SHIFT 20
-#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
-#define OMAP4_GPIO_DR7_SC_SHIFT 18
-#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
-#define OMAP4_DPM_DR0_SC_SHIFT 14
-#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
-#define OMAP4_SIM_DR0_SC_SHIFT 12
-#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
-
-/* CONTROL_SMART1NOPMIO_PADCONF_1 */
-#define OMAP4_FREF_DR0_LB_SHIFT 30
-#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
-#define OMAP4_FREF_DR1_LB_SHIFT 28
-#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
-#define OMAP4_FREF_DR4_LB_SHIFT 26
-#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
-#define OMAP4_FREF_DR5_LB_SHIFT 24
-#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
-#define OMAP4_FREF_DR6_LB_SHIFT 22
-#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
-#define OMAP4_FREF_DR7_LB_SHIFT 20
-#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
-#define OMAP4_GPIO_DR7_LB_SHIFT 18
-#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
-#define OMAP4_DPM_DR0_LB_SHIFT 14
-#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
-#define OMAP4_SIM_DR0_LB_SHIFT 12
-#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
-
-/* CONTROL_PADCONF_MODE */
-#define OMAP4_VDDS_DV_FREF_SHIFT 31
-#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
-#define OMAP4_VDDS_DV_BANK2_SHIFT 30
-#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
-
-/* CONTROL_XTAL_OSCILLATOR */
-#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
-#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
-#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
-#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
-
-/* CONTROL_USIMIO */
-#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
-#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
-#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
-#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
-#define OMAP4_USIM_PWRDNZ_SHIFT 28
-#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
-
-/* CONTROL_I2C_2 */
-#define OMAP4_SR_SDA_GLFENB_SHIFT 31
-#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
-#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
-#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
-#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
-#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
-#define OMAP4_SR_SCL_GLFENB_SHIFT 27
-#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
-#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
-#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
-#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
-#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
-
-/* CONTROL_JTAG */
-#define OMAP4_JTAG_NTRST_EN_SHIFT 31
-#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
-#define OMAP4_JTAG_TCK_EN_SHIFT 30
-#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
-#define OMAP4_JTAG_RTCK_EN_SHIFT 29
-#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
-#define OMAP4_JTAG_TDI_EN_SHIFT 28
-#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
-#define OMAP4_JTAG_TDO_EN_SHIFT 27
-#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
-
-/* CONTROL_SYS */
-#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
-#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
-
-/* WKUP_CONTROL_SPARE_RW */
-#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
-#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
-
-/* WKUP_CONTROL_SPARE_R */
-#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
-#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
-
-/* WKUP_CONTROL_SPARE_R_C0 */
-#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
-#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
-#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
-#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
-#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
-#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
-#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
-#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
-#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
-#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
-
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
deleted file mode 100644
index a0af9ba..0000000
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
-#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
-#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
-#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT 30
-#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT 16
-#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT 11
-#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT 8
-#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT 6
-#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT 0
-#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT 0
-#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
-
-/* CONF_DEBUG_SEL_TST_0 */
-#define OMAP4_WKUP_MODE_SHIFT 0
-#define OMAP4_WKUP_MODE_MASK (1 << 0)
-
-#endif
-- 1.7.7.1.488.ge8e1c
^ permalink raw reply related
* [RFC PATCH v2 00/11] OMAP System Control Module
From: Konstantin Baydarov @ 2012-06-18 11:31 UTC (permalink / raw)
To: b-cousson, kishon, kbaidarov, santosh.shilimkar, tony, paul
Cc: balbi, amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
Hello.
This is a next version of series of patches(based on Eduardo Valentin's patch set) adding a basic support for system control module, on OMAP4+ context. It is a working in progress.
Main changes since previous patch set version:
- Bandgap and usb phy: drivers are now independent from control module driver, they use their own API functions.
Dependency was removed from Kconfig.
- omap-control-core: driver is basically the same as arch/arm/mach-omap2/control.c, but resources aren't hardcoded, they are specified in dts file.
- omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
Probably, no configuration option is required!
- omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows
omap-control-core.c API to be called very early, for example from omap_type()
- omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
module device.
- Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
- Bandgap: Check the type of bandgap dynamically in bandgap driver probe function by reading
omap core control module revision register CONTROL_GEN_CORE_REVISION.
TODO list for bandgap driver:
- Currently, bandgap and usb phy are children of control module, but, in fact, the drivers are independent,
so probably they should be independent entries in dts as well.
- Reserve omap-control-core IOMEM window.
- Improve thermal zone definition for OMAP4
- Introduce the thermal zones for OMAP5
Overall series has been tested only with panda board OMAP4430, so bandgap and usb phy drivers weren't tested at all.
---
Documentation/devicetree/bindings/mfd/omap_control.txt | 44
Documentation/devicetree/bindings/thermal/omap_bandgap.txt | 27
arch/arm/boot/dts/omap4.dtsi | 17
arch/arm/mach-omap2/Kconfig | 1
arch/arm/mach-omap2/am35xx-emac.c | 2
arch/arm/mach-omap2/board-3430sdp.c | 2
arch/arm/mach-omap2/board-4430sdp.c | 2
arch/arm/mach-omap2/board-am3517crane.c | 2
arch/arm/mach-omap2/board-am3517evm.c | 2
arch/arm/mach-omap2/board-apollon.c | 2
arch/arm/mach-omap2/board-cm-t3517.c | 2
arch/arm/mach-omap2/board-h4.c | 2
arch/arm/mach-omap2/board-igep0020.c | 2
arch/arm/mach-omap2/board-ldp.c | 2
arch/arm/mach-omap2/board-omap3logic.c | 2
arch/arm/mach-omap2/board-omap4panda.c | 2
arch/arm/mach-omap2/clock2420_data.c | 2
arch/arm/mach-omap2/clock2430_data.c | 2
arch/arm/mach-omap2/clock3xxx_data.c | 2
arch/arm/mach-omap2/clock44xx_data.c | 2
arch/arm/mach-omap2/common.c | 2
arch/arm/mach-omap2/control.c | 2
arch/arm/mach-omap2/control.h | 416 --
arch/arm/mach-omap2/cpuidle34xx.c | 2
arch/arm/mach-omap2/devices.c | 2
arch/arm/mach-omap2/display.c | 2
arch/arm/mach-omap2/hsmmc.c | 2
arch/arm/mach-omap2/id.c | 7
arch/arm/mach-omap2/include/mach/control.h | 567 +++
arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h | 391 --
arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h | 1409 ---------
arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h | 236 -
arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h | 92
arch/arm/mach-omap2/mcbsp.c | 2
arch/arm/mach-omap2/mux.c | 2
arch/arm/mach-omap2/omap_phy_internal.c | 2
arch/arm/mach-omap2/opp3xxx_data.c | 2
arch/arm/mach-omap2/opp4xxx_data.c | 2
arch/arm/mach-omap2/pm24xx.c | 2
arch/arm/mach-omap2/pm34xx.c | 2
arch/arm/mach-omap2/prcm.c | 2
arch/arm/mach-omap2/serial.c | 2
arch/arm/mach-omap2/sleep34xx.S | 2
arch/arm/mach-omap2/sr_device.c | 2
arch/arm/mach-omap2/usb-fs.c | 2
arch/arm/mach-omap2/voltage.c | 2
arch/arm/plat-omap/Kconfig | 4
drivers/mfd/Kconfig | 9
drivers/mfd/Makefile | 1
drivers/mfd/omap-control-core.c | 141
drivers/thermal/Kconfig | 24
drivers/thermal/Makefile | 5
drivers/thermal/omap-bandgap.c | 1658 +++++++++++
drivers/thermal/omap-bandgap.h | 76
drivers/thermal/omap4-thermal.c | 72
drivers/usb/otg/Kconfig | 12
drivers/usb/otg/Makefile | 1
drivers/usb/otg/omap4-usb-phy.c | 167 +
include/linux/mfd/omap_control.h | 70
include/linux/usb/omap4_usb_phy.h | 53
60 files changed, 2988 insertions(+), 2582 deletions(-)
^ permalink raw reply
* cpuidle future and improvements
From: Daniel Lezcano @ 2012-06-18 8:40 UTC (permalink / raw)
To: linux-acpi, linux-pm, Lists Linaro-dev, Linux Kernel Mailing List
Cc: Kevin Hilman, Peter De Schrijver, Amit Kucheria, linux-next,
Colin Cross, Andrew Morton, Linus Torvalds, Rob Lee
Dear all,
A few weeks ago, Peter De Schrijver proposed a patch [1] to allow per
cpu latencies. We had a discussion about this patchset because it
reverse the modifications Deepthi did some months ago [2] and we may
want to provide a different implementation.
The Linaro Connect [3] event bring us the opportunity to meet people
involved in the power management and the cpuidle area for different SoC.
With the Tegra3 and big.LITTLE architecture, making per cpu latencies
for cpuidle is vital.
Also, the SoC vendors would like to have the ability to tune their cpu
latencies through the device tree.
We agreed in the following steps:
1. factor out / cleanup the cpuidle code as much as possible
2. better sharing of code amongst SoC idle drivers by moving common bits
to core code
3. make the cpuidle_state structure contain only data
4. add a API to register latencies per cpu
These four steps impacts all the architecture. I began the factor out
code / cleanup [4] and that has been accepted upstream and I proposed
some modifications [5] but I had a very few answers.
The patch review are very slow and done at the last minute at the merge
window and that makes code upstreaming very difficult. It is not a
reproach, it is just how it is and I would like to propose a solution
for that.
I propose to host a cpuidle-next tree where all these modifications will
be and where people can send patches against, preventing last minutes
conflicts and perhaps Lenb will agree to pull from this tree. In the
meantime, the tree will be part of the linux-next, the patches will be
more widely tested and could be fixed earlier.
Thanks
-- Daniel
[1] http://lwn.net/Articles/491257/
[2] http://lwn.net/Articles/464808/
[3] http://summit.linaro.org/
[4]
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67033.html,
http://www.spinics.net/lists/linux-pm/msg27330.html,
http://comments.gmane.org/gmane.linux.ports.arm.omap/76311,
http://www.digipedia.pl/usenet/thread/18885/11795/
[5] https://lkml.org/lkml/2012/6/8/375
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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^ permalink raw reply
* Re: [PATCH] cpuidle: move field disable from per-driver to per-cpu
From: Yanmin Zhang @ 2012-06-18 6:42 UTC (permalink / raw)
To: Deepthi Dharwar, lenb
Cc: shuox.liu, linux-kernel@vger.kernel.org, Andrew Morton,
Brown, Len, Zhang, Yanmin, Andrew J. Schorr, linux-pm
In-Reply-To: <4FDB25B6.2040909@linux.vnet.ibm.com>
On Fri, 2012-06-15 at 17:38 +0530, Deepthi Dharwar wrote:
> On 06/14/2012 08:22 AM, ShuoX Liu wrote:
>
> > From: ShuoX Liu <shuox.liu@intel.com>
> >
> > Andrew J.Schorr raises a question. When he changes the disable setting
> > on a single CPU, it affects all the other CPUs. Basically, currently,
> > the disable field is per-driver instead of per-cpu. All the C states of
> > the same driver are shared by all CPU in the same machine.
> >
> > Below patch changes field disable to per-cpu, so we could set this
> > separately for each cpu.
> >
>
>
> This would help us have asymmetric C-states on cpus.
>
> > Reported-by: Andrew J.Schorr <aschorr@telemetry-investments.com>
> > Reviewed-by: Yanmin Zhang <yanmin_zhang@intel.com>
> > Signed-off-by: ShuoX Liu <shuox.liu@intel.com>
>
>
> Acked-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
Len,
Would you like to accept the patch into your testing tree?
Both Deepthi Dharwar and Andrew J. Schorr acked the patch is
useful.
>
> > ---
> > drivers/cpuidle/cpuidle.c | 1 -
> > drivers/cpuidle/governors/menu.c | 5 +++--
> > drivers/cpuidle/sysfs.c | 21 ++++++++++++---------
> > include/linux/cpuidle.h | 2 +-
> > 4 files changed, 16 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
> > index d90519c..04e4b76 100644
> > --- a/drivers/cpuidle/cpuidle.c
> > +++ b/drivers/cpuidle/cpuidle.c
> > @@ -265,7 +265,6 @@ static void poll_idle_init(struct cpuidle_driver *drv)
> > state->power_usage = -1;
> > state->flags = 0;
> > state->enter = poll_idle;
> > - state->disable = 0;
> > }
> > #else
> > static void poll_idle_init(struct cpuidle_driver *drv) {}
> > diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c
> > index 0633575..8391d93 100644
> > --- a/drivers/cpuidle/governors/menu.c
> > +++ b/drivers/cpuidle/governors/menu.c
> > @@ -281,7 +281,7 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
> > * unless the timer is happening really really soon.
> > */
> > if (data->expected_us > 5 &&
> > - drv->states[CPUIDLE_DRIVER_STATE_START].disable == 0)
> > + dev->states_usage[CPUIDLE_DRIVER_STATE_START].disable == 0)
> > data->last_state_idx = CPUIDLE_DRIVER_STATE_START;
> >
> > /*
> > @@ -290,8 +290,9 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
> > */
> > for (i = CPUIDLE_DRIVER_STATE_START; i < drv->state_count; i++) {
> > struct cpuidle_state *s = &drv->states[i];
> > + struct cpuidle_state_usage *su = &dev->states_usage[i];
> >
> > - if (s->disable)
> > + if (su->disable)
> > continue;
> > if (s->target_residency > data->predicted_us)
> > continue;
> > diff --git a/drivers/cpuidle/sysfs.c b/drivers/cpuidle/sysfs.c
> > index 88032b4..5f809e3 100644
> > --- a/drivers/cpuidle/sysfs.c
> > +++ b/drivers/cpuidle/sysfs.c
> > @@ -217,7 +217,8 @@ struct cpuidle_state_attr {
> > struct attribute attr;
> > ssize_t (*show)(struct cpuidle_state *, \
> > struct cpuidle_state_usage *, char *);
> > - ssize_t (*store)(struct cpuidle_state *, const char *, size_t);
> > + ssize_t (*store)(struct cpuidle_state *, \
> > + struct cpuidle_state_usage *, const char *, size_t);
> > };
> >
> > #define define_one_state_ro(_name, show) \
> > @@ -233,21 +234,22 @@ static ssize_t show_state_##_name(struct cpuidle_state *state, \
> > return sprintf(buf, "%u\n", state->_name);\
> > }
> >
> > -#define define_store_state_function(_name) \
> > +#define define_store_state_ull_function(_name) \
> > static ssize_t store_state_##_name(struct cpuidle_state *state, \
> > + struct cpuidle_state_usage *state_usage, \
> > const char *buf, size_t size) \
> > { \
> > - long value; \
> > + unsigned long long value; \
> > int err; \
> > if (!capable(CAP_SYS_ADMIN)) \
> > return -EPERM; \
> > - err = kstrtol(buf, 0, &value); \
> > + err = kstrtoull(buf, 0, &value); \
> > if (err) \
> > return err; \
> > if (value) \
> > - state->disable = 1; \
> > + state_usage->_name = 1; \
> > else \
> > - state->disable = 0; \
> > + state_usage->_name = 0; \
> > return size; \
> > }
> >
> > @@ -273,8 +275,8 @@ define_show_state_ull_function(usage)
> > define_show_state_ull_function(time)
> > define_show_state_str_function(name)
> > define_show_state_str_function(desc)
> > -define_show_state_function(disable)
> > -define_store_state_function(disable)
> > +define_show_state_ull_function(disable)
> > +define_store_state_ull_function(disable)
> >
> > define_one_state_ro(name, show_state_name);
> > define_one_state_ro(desc, show_state_desc);
> > @@ -318,10 +320,11 @@ static ssize_t cpuidle_state_store(struct kobject *kobj,
> > {
> > int ret = -EIO;
> > struct cpuidle_state *state = kobj_to_state(kobj);
> > + struct cpuidle_state_usage *state_usage = kobj_to_state_usage(kobj);
> > struct cpuidle_state_attr *cattr = attr_to_stateattr(attr);
> >
> > if (cattr->store)
> > - ret = cattr->store(state, buf, size);
> > + ret = cattr->store(state, state_usage, buf, size);
> >
> > return ret;
> > }
> > diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
> > index 6c26a3d..8570012 100644
> > --- a/include/linux/cpuidle.h
> > +++ b/include/linux/cpuidle.h
> > @@ -34,6 +34,7 @@ struct cpuidle_driver;
> > struct cpuidle_state_usage {
> > void *driver_data;
> >
> > + unsigned long long disable;
> > unsigned long long usage;
> > unsigned long long time; /* in US */
> > };
> > @@ -46,7 +47,6 @@ struct cpuidle_state {
> > unsigned int exit_latency; /* in US */
> > int power_usage; /* in mW */
> > unsigned int target_residency; /* in US */
> > - unsigned int disable;
> >
> > int (*enter) (struct cpuidle_device *dev,
> > struct cpuidle_driver *drv,
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: acpi_idle and max_cpus
From: Daniel Lezcano @ 2012-06-17 20:18 UTC (permalink / raw)
To: linux-acpi, linux-pm
In-Reply-To: <4FDB549F.1020002@linaro.org>
On 06/15/2012 05:28 PM, Daniel Lezcano wrote:
>
> Hi all,
>
> I have a dual core Intel T9500.
>
> I boot the cpu with the acpi_idle driver and intel_idle enabled in the
> config.
>
> The kernel is booted with maxcpus=1.
>
> After the system has boot, I put cpu1 online via sysfs.
>
> But I don't see any 'cpuidle' directory in the cpu's sysfs entry:
>
> /sys/devices/system/cpu/cpu1/cpuidle (?)
>
> When I look at the code I see the notifier is present for hotplug in
> processor_driver.c and the cpuidle intel init routine should be called
> there.
>
> I am wondering is it a bug or an expected behavior ?
Any thoughts on that ?
Thanks
-- Daniel
--
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Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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^ permalink raw reply
* Re: [PATCH] ACPI, cpuidle: Fix suspend/resume regression caused by cpuidle cleanup.
From: Rafael J. Wysocki @ 2012-06-16 13:36 UTC (permalink / raw)
To: Deepthi Dharwar
Cc: Dave Hansen, Linux PM mailing list, linux-pm, linux-acpi,
Len Brown, Jean Pihet, Arjan van de Ven, Kevin Hilman,
Arnd Bergmann, Ferenc Wagner, Tomas M., Srivatsa S. Bhat, preeti,
Len Brown, H. Peter Anvin
In-Reply-To: <4FD87249.6010302@linux.vnet.ibm.com>
On Wednesday, June 13, 2012, Deepthi Dharwar wrote:
>
> From: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>
> Fix suspend/resume regression caused by cpuidle cleanup.
>
> Commit e978aa7d7d57d04eb5f88a7507c4fb98577def77 ( cpuidle: Move
> dev->last_residency update to driver enter routine; remove dev->last_state)
> was breaking suspend on laptops, as reported in the below link
> - https://lkml.org/lkml/2011/11/11/164
>
> This was fixed in commit 3439a8da16bcad6b0982ece938c9f8299bb53584
> (ACPI / cpuidle: Remove acpi_idle_suspend (to fix suspend regression)
> by removing acpi_idle_suspend flag.
> - https://lkml.org/lkml/2011/11/14/74
>
> But this fix did not work on all systems
> as Suspend/resume regression was reported on Lenovo S10-3
> recently by Dave.
> - https://lkml.org/lkml/2012/5/27/115
> It looked like with commit e978aa7d broke suspend and
> with commit 3439a8da resume was not working with acpi_idle driver.
>
> This patch fixes the regression that caused this issue
> in the first place. acpi_idle_suspend flag is essential on
> some x86 systems to prevent the cpus from going to deeper C-states
> when suspend is triggered ( commit b04e7bdb984 )
> So reverting the commit 3439a8da is essential.
>
> By default, irqs are disabled in cpu_idle arch specific call
> and re-enabled in idle state return path . As the acpi_idle_suspend
> flag was being set during suspend, which prevented the cpus
> going to deeper idle states, it is essential to
> enabling the irqs in its return path too.
>
> To address the suspend issue,
> we were not re-enabling the interrupts while returning from
> acpi_idle_enter_bm() routine if acpi_idle_suspend flag is set.
> and this was causing suspend failure.
>
> In addition to the above fix, a sanity check has also been added
> in x86 arch specific cpu_idle call to ensure that the idle call
> always returns with IRQs enabled.
>
> This patch applies on 3.5-rc2
> ---
>
> Reported-and-Tested-by: Dav Hansen <dave@linux.vnet.ibm.com>
> Tested-by: Preeti Murthy <preeti@linux.vnet.ibm.com>
> Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
> Reviewed-by: Srivatsa S Bhat <srivatsa.bhat@linux.vnet.ibm.com>
This appears to be an urgent regression fix.
Is anyone going to take it, or should I do that?
Rafael
> ---
> arch/x86/kernel/process.c | 6 ++++++
> drivers/acpi/processor_idle.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> index 735279e..8ab76ad 100644
> --- a/arch/x86/kernel/process.c
> +++ b/arch/x86/kernel/process.c
> @@ -460,6 +460,12 @@ void cpu_idle(void)
> pm_idle();
>
> rcu_idle_exit();
> +
> + /*
> + * Sanity check to ensure that idle call returns
> + * with IRQs enabled
> + */
> + WARN_ON(irqs_disabled());
> start_critical_timings();
>
> /* In many cases the interrupt that ended idle
> diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
> index f3decb3..c2ffd84 100644
> --- a/drivers/acpi/processor_idle.c
> +++ b/drivers/acpi/processor_idle.c
> @@ -224,6 +224,7 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
> /*
> * Suspend / resume control
> */
> +static int acpi_idle_suspend;
> static u32 saved_bm_rld;
>
> static void acpi_idle_bm_rld_save(void)
> @@ -242,13 +243,21 @@ static void acpi_idle_bm_rld_restore(void)
>
> int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
> {
> + if (acpi_idle_suspend == 1)
> + return 0;
> +
> acpi_idle_bm_rld_save();
> + acpi_idle_suspend = 1;
> return 0;
> }
>
> int acpi_processor_resume(struct acpi_device * device)
> {
> + if (acpi_idle_suspend == 0)
> + return 0;
> +
> acpi_idle_bm_rld_restore();
> + acpi_idle_suspend = 0;
> return 0;
> }
>
> @@ -754,6 +763,12 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
>
> local_irq_disable();
>
> + if (acpi_idle_suspend) {
> + local_irq_enable();
> + cpu_relax();
> + return -EINVAL;
> + }
> +
> lapic_timer_state_broadcast(pr, cx, 1);
> kt1 = ktime_get_real();
> acpi_idle_do_entry(cx);
> @@ -823,6 +838,12 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
>
> local_irq_disable();
>
> + if (acpi_idle_suspend) {
> + local_irq_enable();
> + cpu_relax();
> + return -EINVAL;
> + }
> +
> if (cx->entry_method != ACPI_CSTATE_FFH) {
> current_thread_info()->status &= ~TS_POLLING;
> /*
> @@ -901,6 +922,13 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
> if (unlikely(!pr))
> return -EINVAL;
>
> + if (acpi_idle_suspend) {
> + if (irqs_disabled())
> + local_irq_enable();
> + cpu_relax();
> + return -EINVAL;
> + }
> +
> if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
> if (drv->safe_state_index >= 0) {
> return drv->states[drv->safe_state_index].enter(dev,
>
> Regards,
> Deepthi
>
>
>
^ permalink raw reply
* acpi_idle and max_cpus
From: Daniel Lezcano @ 2012-06-15 15:28 UTC (permalink / raw)
To: linux-acpi, linux-pm
Hi all,
I have a dual core Intel T9500.
I boot the cpu with the acpi_idle driver and intel_idle enabled in the
config.
The kernel is booted with maxcpus=1.
After the system has boot, I put cpu1 online via sysfs.
But I don't see any 'cpuidle' directory in the cpu's sysfs entry:
/sys/devices/system/cpu/cpu1/cpuidle (?)
When I look at the code I see the notifier is present for hotplug in
processor_driver.c and the cpuidle intel init routine should be called
there.
I am wondering is it a bug or an expected behavior ?
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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^ permalink raw reply
* Re: [PATCH] ACPI, cpuidle: Fix suspend/resume regression caused by cpuidle cleanup.
From: Deepthi Dharwar @ 2012-06-15 12:27 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Dave Hansen, Linux PM mailing list, linux-pm, linux-acpi,
Len Brown, Jean Pihet, Arjan van de Ven, Kevin Hilman,
Arnd Bergmann, Ferenc Wagner, Tomas M., Srivatsa S. Bhat, preeti,
linux-kernel@vger.kernel.org, stable
In-Reply-To: <4FDB279F.7020801@linux.vnet.ibm.com>
Apologies for the confusion.
Please add the Cc: stable tag for this patch as this regression affects
older kernels too.
Link to the patch :
http://permalink.gmane.org/gmane.linux.power-management.general/27614
Thanks !
Deepthi
On 06/15/2012 05:46 PM, Deepthi Dharwar wrote:
> Please include this in -stable tree, as this is a regression fix which
> affects older kernels ( 3.1 onwards )
> Link to the patch :
> http://permalink.gmane.org/gmane.linux.power-management.general/27614
>
> Thanks !
> Deepthi
>
> On 06/14/2012 01:31 AM, Rafael J. Wysocki wrote:
>
>> On Wednesday, June 13, 2012, Deepthi Dharwar wrote:
>>>
>>> From: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>>>
>>> Fix suspend/resume regression caused by cpuidle cleanup.
>>>
>>> Commit e978aa7d7d57d04eb5f88a7507c4fb98577def77 ( cpuidle: Move
>>> dev->last_residency update to driver enter routine; remove dev->last_state)
>>> was breaking suspend on laptops, as reported in the below link
>>> - https://lkml.org/lkml/2011/11/11/164
>>>
>>> This was fixed in commit 3439a8da16bcad6b0982ece938c9f8299bb53584
>>> (ACPI / cpuidle: Remove acpi_idle_suspend (to fix suspend regression)
>>> by removing acpi_idle_suspend flag.
>>> - https://lkml.org/lkml/2011/11/14/74
>>>
>>> But this fix did not work on all systems
>>> as Suspend/resume regression was reported on Lenovo S10-3
>>> recently by Dave.
>>> - https://lkml.org/lkml/2012/5/27/115
>>> It looked like with commit e978aa7d broke suspend and
>>> with commit 3439a8da resume was not working with acpi_idle driver.
>>>
>>> This patch fixes the regression that caused this issue
>>> in the first place. acpi_idle_suspend flag is essential on
>>> some x86 systems to prevent the cpus from going to deeper C-states
>>> when suspend is triggered ( commit b04e7bdb984 )
>>> So reverting the commit 3439a8da is essential.
>>>
>>> By default, irqs are disabled in cpu_idle arch specific call
>>> and re-enabled in idle state return path . As the acpi_idle_suspend
>>> flag was being set during suspend, which prevented the cpus
>>> going to deeper idle states, it is essential to
>>> enabling the irqs in its return path too.
>>>
>>> To address the suspend issue,
>>> we were not re-enabling the interrupts while returning from
>>> acpi_idle_enter_bm() routine if acpi_idle_suspend flag is set.
>>> and this was causing suspend failure.
>>>
>>> In addition to the above fix, a sanity check has also been added
>>> in x86 arch specific cpu_idle call to ensure that the idle call
>>> always returns with IRQs enabled.
>>>
>>> This patch applies on 3.5-rc2
>>> ---
>>>
>>> Reported-and-Tested-by: Dav Hansen <dave@linux.vnet.ibm.com>
>>> Tested-by: Preeti Murthy <preeti@linux.vnet.ibm.com>
>>> Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>>> Reviewed-by: Srivatsa S Bhat <srivatsa.bhat@linux.vnet.ibm.com>
>>
>> Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
>>
>>> ---
>>> arch/x86/kernel/process.c | 6 ++++++
>>> drivers/acpi/processor_idle.c | 28 ++++++++++++++++++++++++++++
>>> 2 files changed, 34 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
>>> index 735279e..8ab76ad 100644
>>> --- a/arch/x86/kernel/process.c
>>> +++ b/arch/x86/kernel/process.c
>>> @@ -460,6 +460,12 @@ void cpu_idle(void)
>>> pm_idle();
>>>
>>> rcu_idle_exit();
>>> +
>>> + /*
>>> + * Sanity check to ensure that idle call returns
>>> + * with IRQs enabled
>>> + */
>>> + WARN_ON(irqs_disabled());
>>> start_critical_timings();
>>>
>>> /* In many cases the interrupt that ended idle
>>> diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
>>> index f3decb3..c2ffd84 100644
>>> --- a/drivers/acpi/processor_idle.c
>>> +++ b/drivers/acpi/processor_idle.c
>>> @@ -224,6 +224,7 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
>>> /*
>>> * Suspend / resume control
>>> */
>>> +static int acpi_idle_suspend;
>>> static u32 saved_bm_rld;
>>>
>>> static void acpi_idle_bm_rld_save(void)
>>> @@ -242,13 +243,21 @@ static void acpi_idle_bm_rld_restore(void)
>>>
>>> int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
>>> {
>>> + if (acpi_idle_suspend == 1)
>>> + return 0;
>>> +
>>> acpi_idle_bm_rld_save();
>>> + acpi_idle_suspend = 1;
>>> return 0;
>>> }
>>>
>>> int acpi_processor_resume(struct acpi_device * device)
>>> {
>>> + if (acpi_idle_suspend == 0)
>>> + return 0;
>>> +
>>> acpi_idle_bm_rld_restore();
>>> + acpi_idle_suspend = 0;
>>> return 0;
>>> }
>>>
>>> @@ -754,6 +763,12 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
>>>
>>> local_irq_disable();
>>>
>>> + if (acpi_idle_suspend) {
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> lapic_timer_state_broadcast(pr, cx, 1);
>>> kt1 = ktime_get_real();
>>> acpi_idle_do_entry(cx);
>>> @@ -823,6 +838,12 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
>>>
>>> local_irq_disable();
>>>
>>> + if (acpi_idle_suspend) {
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> if (cx->entry_method != ACPI_CSTATE_FFH) {
>>> current_thread_info()->status &= ~TS_POLLING;
>>> /*
>>> @@ -901,6 +922,13 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
>>> if (unlikely(!pr))
>>> return -EINVAL;
>>>
>>> + if (acpi_idle_suspend) {
>>> + if (irqs_disabled())
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
>>> if (drv->safe_state_index >= 0) {
>>> return drv->states[drv->safe_state_index].enter(dev,
>>>
>>> Regards,
>>> Deepthi
>>>
>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
^ permalink raw reply
* Re: [PATCH] ACPI, cpuidle: Fix suspend/resume regression caused by cpuidle cleanup.
From: Deepthi Dharwar @ 2012-06-15 12:25 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Kevin Hilman, Len Brown, Arnd Bergmann, Linux PM mailing list,
Tomas M., linux-kernel@vger.kernel.org, stable, Dave Hansen,
linux-acpi, Srivatsa S. Bhat, preeti, linux-pm, Ferenc Wagner,
Arjan van de Ven, Jean Pihet
In-Reply-To: <4FDB279F.7020801@linux.vnet.ibm.com>
Apologies for the confusion.
Please add the Cc: stable tag for this patch as this regression affects
older kernels too.
Link to the patch :
http://permalink.gmane.org/gmane.linux.power-management.general/27614
Thanks !
Deepthi
On 06/15/2012 05:46 PM, Deepthi Dharwar wrote:
> Please include this in -stable tree, as this is a regression fix which
> affects older kernels ( 3.1 onwards )
Sorry for the typo. :(
> Link to the patch :
> http://permalink.gmane.org/gmane.linux.power-management.general/27614
>
> Thanks !
> Deepthi
>
> On 06/14/2012 01:31 AM, Rafael J. Wysocki wrote:
>
>> On Wednesday, June 13, 2012, Deepthi Dharwar wrote:
>>>
>>> From: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>>>
>>> Fix suspend/resume regression caused by cpuidle cleanup.
>>>
>>> Commit e978aa7d7d57d04eb5f88a7507c4fb98577def77 ( cpuidle: Move
>>> dev->last_residency update to driver enter routine; remove dev->last_state)
>>> was breaking suspend on laptops, as reported in the below link
>>> - https://lkml.org/lkml/2011/11/11/164
>>>
>>> This was fixed in commit 3439a8da16bcad6b0982ece938c9f8299bb53584
>>> (ACPI / cpuidle: Remove acpi_idle_suspend (to fix suspend regression)
>>> by removing acpi_idle_suspend flag.
>>> - https://lkml.org/lkml/2011/11/14/74
>>>
>>> But this fix did not work on all systems
>>> as Suspend/resume regression was reported on Lenovo S10-3
>>> recently by Dave.
>>> - https://lkml.org/lkml/2012/5/27/115
>>> It looked like with commit e978aa7d broke suspend and
>>> with commit 3439a8da resume was not working with acpi_idle driver.
>>>
>>> This patch fixes the regression that caused this issue
>>> in the first place. acpi_idle_suspend flag is essential on
>>> some x86 systems to prevent the cpus from going to deeper C-states
>>> when suspend is triggered ( commit b04e7bdb984 )
>>> So reverting the commit 3439a8da is essential.
>>>
>>> By default, irqs are disabled in cpu_idle arch specific call
>>> and re-enabled in idle state return path . As the acpi_idle_suspend
>>> flag was being set during suspend, which prevented the cpus
>>> going to deeper idle states, it is essential to
>>> enabling the irqs in its return path too.
>>>
>>> To address the suspend issue,
>>> we were not re-enabling the interrupts while returning from
>>> acpi_idle_enter_bm() routine if acpi_idle_suspend flag is set.
>>> and this was causing suspend failure.
>>>
>>> In addition to the above fix, a sanity check has also been added
>>> in x86 arch specific cpu_idle call to ensure that the idle call
>>> always returns with IRQs enabled.
>>>
>>> This patch applies on 3.5-rc2
>>> ---
>>>
>>> Reported-and-Tested-by: Dav Hansen <dave@linux.vnet.ibm.com>
>>> Tested-by: Preeti Murthy <preeti@linux.vnet.ibm.com>
>>> Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>>> Reviewed-by: Srivatsa S Bhat <srivatsa.bhat@linux.vnet.ibm.com>
>>
>> Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
>>
>>> ---
>>> arch/x86/kernel/process.c | 6 ++++++
>>> drivers/acpi/processor_idle.c | 28 ++++++++++++++++++++++++++++
>>> 2 files changed, 34 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
>>> index 735279e..8ab76ad 100644
>>> --- a/arch/x86/kernel/process.c
>>> +++ b/arch/x86/kernel/process.c
>>> @@ -460,6 +460,12 @@ void cpu_idle(void)
>>> pm_idle();
>>>
>>> rcu_idle_exit();
>>> +
>>> + /*
>>> + * Sanity check to ensure that idle call returns
>>> + * with IRQs enabled
>>> + */
>>> + WARN_ON(irqs_disabled());
>>> start_critical_timings();
>>>
>>> /* In many cases the interrupt that ended idle
>>> diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
>>> index f3decb3..c2ffd84 100644
>>> --- a/drivers/acpi/processor_idle.c
>>> +++ b/drivers/acpi/processor_idle.c
>>> @@ -224,6 +224,7 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
>>> /*
>>> * Suspend / resume control
>>> */
>>> +static int acpi_idle_suspend;
>>> static u32 saved_bm_rld;
>>>
>>> static void acpi_idle_bm_rld_save(void)
>>> @@ -242,13 +243,21 @@ static void acpi_idle_bm_rld_restore(void)
>>>
>>> int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
>>> {
>>> + if (acpi_idle_suspend == 1)
>>> + return 0;
>>> +
>>> acpi_idle_bm_rld_save();
>>> + acpi_idle_suspend = 1;
>>> return 0;
>>> }
>>>
>>> int acpi_processor_resume(struct acpi_device * device)
>>> {
>>> + if (acpi_idle_suspend == 0)
>>> + return 0;
>>> +
>>> acpi_idle_bm_rld_restore();
>>> + acpi_idle_suspend = 0;
>>> return 0;
>>> }
>>>
>>> @@ -754,6 +763,12 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
>>>
>>> local_irq_disable();
>>>
>>> + if (acpi_idle_suspend) {
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> lapic_timer_state_broadcast(pr, cx, 1);
>>> kt1 = ktime_get_real();
>>> acpi_idle_do_entry(cx);
>>> @@ -823,6 +838,12 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
>>>
>>> local_irq_disable();
>>>
>>> + if (acpi_idle_suspend) {
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> if (cx->entry_method != ACPI_CSTATE_FFH) {
>>> current_thread_info()->status &= ~TS_POLLING;
>>> /*
>>> @@ -901,6 +922,13 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
>>> if (unlikely(!pr))
>>> return -EINVAL;
>>>
>>> + if (acpi_idle_suspend) {
>>> + if (irqs_disabled())
>>> + local_irq_enable();
>>> + cpu_relax();
>>> + return -EINVAL;
>>> + }
>>> +
>>> if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
>>> if (drv->safe_state_index >= 0) {
>>> return drv->states[drv->safe_state_index].enter(dev,
>>>
>>> Regards,
>>> Deepthi
>>>
>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
^ permalink raw reply
* Re: [PATCH] ACPI, cpuidle: Fix suspend/resume regression caused by cpuidle cleanup.
From: Deepthi Dharwar @ 2012-06-15 12:16 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Dave Hansen, Linux PM mailing list, linux-pm, linux-acpi,
Len Brown, Jean Pihet, Arjan van de Ven, Kevin Hilman,
Arnd Bergmann, Ferenc Wagner, Tomas M., Srivatsa S. Bhat, preeti,
linux-kernel@vger.kernel.org, stable
In-Reply-To: <201206132201.26058.rjw@sisk.pl>
Please include this in -stable tree, as this is a regression fix which
affects older kernels ( 3.1 onwards )
Link to the patch :
http://permalink.gmane.org/gmane.linux.power-management.general/27614
Thanks !
Deepthi
On 06/14/2012 01:31 AM, Rafael J. Wysocki wrote:
> On Wednesday, June 13, 2012, Deepthi Dharwar wrote:
>>
>> From: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>>
>> Fix suspend/resume regression caused by cpuidle cleanup.
>>
>> Commit e978aa7d7d57d04eb5f88a7507c4fb98577def77 ( cpuidle: Move
>> dev->last_residency update to driver enter routine; remove dev->last_state)
>> was breaking suspend on laptops, as reported in the below link
>> - https://lkml.org/lkml/2011/11/11/164
>>
>> This was fixed in commit 3439a8da16bcad6b0982ece938c9f8299bb53584
>> (ACPI / cpuidle: Remove acpi_idle_suspend (to fix suspend regression)
>> by removing acpi_idle_suspend flag.
>> - https://lkml.org/lkml/2011/11/14/74
>>
>> But this fix did not work on all systems
>> as Suspend/resume regression was reported on Lenovo S10-3
>> recently by Dave.
>> - https://lkml.org/lkml/2012/5/27/115
>> It looked like with commit e978aa7d broke suspend and
>> with commit 3439a8da resume was not working with acpi_idle driver.
>>
>> This patch fixes the regression that caused this issue
>> in the first place. acpi_idle_suspend flag is essential on
>> some x86 systems to prevent the cpus from going to deeper C-states
>> when suspend is triggered ( commit b04e7bdb984 )
>> So reverting the commit 3439a8da is essential.
>>
>> By default, irqs are disabled in cpu_idle arch specific call
>> and re-enabled in idle state return path . As the acpi_idle_suspend
>> flag was being set during suspend, which prevented the cpus
>> going to deeper idle states, it is essential to
>> enabling the irqs in its return path too.
>>
>> To address the suspend issue,
>> we were not re-enabling the interrupts while returning from
>> acpi_idle_enter_bm() routine if acpi_idle_suspend flag is set.
>> and this was causing suspend failure.
>>
>> In addition to the above fix, a sanity check has also been added
>> in x86 arch specific cpu_idle call to ensure that the idle call
>> always returns with IRQs enabled.
>>
>> This patch applies on 3.5-rc2
>> ---
>>
>> Reported-and-Tested-by: Dav Hansen <dave@linux.vnet.ibm.com>
>> Tested-by: Preeti Murthy <preeti@linux.vnet.ibm.com>
>> Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
>> Reviewed-by: Srivatsa S Bhat <srivatsa.bhat@linux.vnet.ibm.com>
>
> Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
>
>> ---
>> arch/x86/kernel/process.c | 6 ++++++
>> drivers/acpi/processor_idle.c | 28 ++++++++++++++++++++++++++++
>> 2 files changed, 34 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
>> index 735279e..8ab76ad 100644
>> --- a/arch/x86/kernel/process.c
>> +++ b/arch/x86/kernel/process.c
>> @@ -460,6 +460,12 @@ void cpu_idle(void)
>> pm_idle();
>>
>> rcu_idle_exit();
>> +
>> + /*
>> + * Sanity check to ensure that idle call returns
>> + * with IRQs enabled
>> + */
>> + WARN_ON(irqs_disabled());
>> start_critical_timings();
>>
>> /* In many cases the interrupt that ended idle
>> diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
>> index f3decb3..c2ffd84 100644
>> --- a/drivers/acpi/processor_idle.c
>> +++ b/drivers/acpi/processor_idle.c
>> @@ -224,6 +224,7 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
>> /*
>> * Suspend / resume control
>> */
>> +static int acpi_idle_suspend;
>> static u32 saved_bm_rld;
>>
>> static void acpi_idle_bm_rld_save(void)
>> @@ -242,13 +243,21 @@ static void acpi_idle_bm_rld_restore(void)
>>
>> int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
>> {
>> + if (acpi_idle_suspend == 1)
>> + return 0;
>> +
>> acpi_idle_bm_rld_save();
>> + acpi_idle_suspend = 1;
>> return 0;
>> }
>>
>> int acpi_processor_resume(struct acpi_device * device)
>> {
>> + if (acpi_idle_suspend == 0)
>> + return 0;
>> +
>> acpi_idle_bm_rld_restore();
>> + acpi_idle_suspend = 0;
>> return 0;
>> }
>>
>> @@ -754,6 +763,12 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
>>
>> local_irq_disable();
>>
>> + if (acpi_idle_suspend) {
>> + local_irq_enable();
>> + cpu_relax();
>> + return -EINVAL;
>> + }
>> +
>> lapic_timer_state_broadcast(pr, cx, 1);
>> kt1 = ktime_get_real();
>> acpi_idle_do_entry(cx);
>> @@ -823,6 +838,12 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
>>
>> local_irq_disable();
>>
>> + if (acpi_idle_suspend) {
>> + local_irq_enable();
>> + cpu_relax();
>> + return -EINVAL;
>> + }
>> +
>> if (cx->entry_method != ACPI_CSTATE_FFH) {
>> current_thread_info()->status &= ~TS_POLLING;
>> /*
>> @@ -901,6 +922,13 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
>> if (unlikely(!pr))
>> return -EINVAL;
>>
>> + if (acpi_idle_suspend) {
>> + if (irqs_disabled())
>> + local_irq_enable();
>> + cpu_relax();
>> + return -EINVAL;
>> + }
>> +
>> if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
>> if (drv->safe_state_index >= 0) {
>> return drv->states[drv->safe_state_index].enter(dev,
>>
>> Regards,
>> Deepthi
>>
>>
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [RFC PATCH 03/11] arm: omap: device: create a device for system control module
From: Valentin, Eduardo @ 2012-06-15 9:22 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FD9EC1B.6010506@dev.rtsoft.ru>
Hello Konstantin,
Sorry for the delayed reply.
On Thu, Jun 14, 2012 at 4:50 PM, Konstantin Baydarov
<kbaidarov@dev.rtsoft.ru> wrote:
> Hi.
>
> On 05/29/2012 01:44 PM, Eduardo Valentin wrote:
>> On Fri, May 25, 2012 at 02:30:44PM +0200, Cousson Benoit wrote:
>>> On 5/25/2012 10:25 AM, Eduardo Valentin wrote:
>>>> From: Kishon Vijay Abraham I<kishon@ti.com>
>>>>
>>>> Extracts the device data from hwmod database and create a platform device
>>>> using omap device build.
>>>>
>>>> The device build is done during postcore_initcall.
>>> Do you still need that since you are supporting only DT?
>>> The device will be built automatically in the DT case.
>> In fact this is not needed for DT only probing. Dropping this one.
> Yes, platform device(struct platform_device) will be built automatically, but omap device(struct omap_device) will not be built.
The platform_device will be built as well as the omap_device. There
are hooks at the platform_device creation that will proceed with the
omap_device deployment. Please check:
arch/arm/plat-omap/omap_device.c: _omap_device_notifier_call and
omap_device_build_from_dt
> Also when omap device is allocated(omap_device_alloc) hwmod_clocks are registered, but in case of ctrl_module_core device - no new clock are registered.
> So, is it fine to drop omap device and skip omap_device_build() call?
As explained above, when booting with DT, you will get both, pdev and omap_dev.
>
> BR,
> Konstantin Baydarov.
All best,
Eduardo
>
>>
>>> Regards,
>>> Benoit
>>>
>>>> Signed-off-by: Kishon Vijay Abraham I<kishon@ti.com>
>>>> Signed-off-by: Eduardo Valentin<eduardo.valentin@ti.com>
>>>> ---
>>>> arch/arm/mach-omap2/devices.c | 26 ++++++++++++++++++++++++++
>>>> 1 files changed, 26 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
>>>> index 152c266..9332673 100644
>>>> --- a/arch/arm/mach-omap2/devices.c
>>>> +++ b/arch/arm/mach-omap2/devices.c
>>>> @@ -40,6 +40,32 @@
>>>> #define L3_MODULES_MAX_LEN 12
>>>> #define L3_MODULES 3
>>>>
>>>> +static int omap_init_control(void)
>>>> +{
>>>> + struct omap_hwmod *oh;
>>>> + struct platform_device *pdev;
>>>> + const char *oh_name, *name;
>>>> +
>>>> + oh_name = "ctrl_module_core";
>>>> + name = "omap-control-core";
>>>> +
>>>> + oh = omap_hwmod_lookup(oh_name);
>>>> + if (!oh) {
>>>> + pr_err("Could not lookup hwmod for %s\n", oh_name);
>>>> + return PTR_ERR(oh);
>>>> + }
>>>> +
>>>> + pdev = omap_device_build(name, -1, oh, NULL, 0, NULL, 0, true);
>>>> + if (IS_ERR(pdev)) {
>>>> + pr_err("Could not build omap_device for %s %s\n",
>>>> + name, oh_name);
>>>> + return PTR_ERR(pdev);
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +postcore_initcall(omap_init_control);
>>>> +
>>>> static int __init omap3_l3_init(void)
>>>> {
>>>> struct omap_hwmod *oh;
>
--
Eduardo Valentin
^ permalink raw reply
* Re: [RFC PATCH 03/11] arm: omap: device: create a device for system control module
From: Konstantin Baydarov @ 2012-06-14 13:50 UTC (permalink / raw)
To: eduardo.valentin
Cc: Cousson, Benoit, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap
In-Reply-To: <20120529094400.GA3505@besouro>
Hi.
On 05/29/2012 01:44 PM, Eduardo Valentin wrote:
> On Fri, May 25, 2012 at 02:30:44PM +0200, Cousson Benoit wrote:
>> On 5/25/2012 10:25 AM, Eduardo Valentin wrote:
>>> From: Kishon Vijay Abraham I<kishon@ti.com>
>>>
>>> Extracts the device data from hwmod database and create a platform device
>>> using omap device build.
>>>
>>> The device build is done during postcore_initcall.
>> Do you still need that since you are supporting only DT?
>> The device will be built automatically in the DT case.
> In fact this is not needed for DT only probing. Dropping this one.
Yes, platform device(struct platform_device) will be built automatically, but omap device(struct omap_device) will not be built.
Also when omap device is allocated(omap_device_alloc) hwmod_clocks are registered, but in case of ctrl_module_core device - no new clock are registered.
So, is it fine to drop omap device and skip omap_device_build() call?
BR,
Konstantin Baydarov.
>
>> Regards,
>> Benoit
>>
>>> Signed-off-by: Kishon Vijay Abraham I<kishon@ti.com>
>>> Signed-off-by: Eduardo Valentin<eduardo.valentin@ti.com>
>>> ---
>>> arch/arm/mach-omap2/devices.c | 26 ++++++++++++++++++++++++++
>>> 1 files changed, 26 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
>>> index 152c266..9332673 100644
>>> --- a/arch/arm/mach-omap2/devices.c
>>> +++ b/arch/arm/mach-omap2/devices.c
>>> @@ -40,6 +40,32 @@
>>> #define L3_MODULES_MAX_LEN 12
>>> #define L3_MODULES 3
>>>
>>> +static int omap_init_control(void)
>>> +{
>>> + struct omap_hwmod *oh;
>>> + struct platform_device *pdev;
>>> + const char *oh_name, *name;
>>> +
>>> + oh_name = "ctrl_module_core";
>>> + name = "omap-control-core";
>>> +
>>> + oh = omap_hwmod_lookup(oh_name);
>>> + if (!oh) {
>>> + pr_err("Could not lookup hwmod for %s\n", oh_name);
>>> + return PTR_ERR(oh);
>>> + }
>>> +
>>> + pdev = omap_device_build(name, -1, oh, NULL, 0, NULL, 0, true);
>>> + if (IS_ERR(pdev)) {
>>> + pr_err("Could not build omap_device for %s %s\n",
>>> + name, oh_name);
>>> + return PTR_ERR(pdev);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +postcore_initcall(omap_init_control);
>>> +
>>> static int __init omap3_l3_init(void)
>>> {
>>> struct omap_hwmod *oh;
^ permalink raw reply
* Re: [RFC 1/4] cpuidle: define the enter function in the driver structure
From: Daniel Lezcano @ 2012-06-14 8:16 UTC (permalink / raw)
To: Namhyung Kim; +Cc: linux-acpi, linux-pm, linaro-dev, linux-kernel
In-Reply-To: <87r4ti49jt.fsf@sejong.aot.lge.com>
On 06/14/2012 09:49 AM, Namhyung Kim wrote:
> Hi,
>
> On Fri, 8 Jun 2012 18:02:42 +0200, Daniel Lezcano wrote:
>> We have the state index passed as parameter to the 'enter' function.
>> Most of the drivers assign their 'enter' functions several times in
>> the cpuidle_state structure, as we have the index, we can delegate
>> to the driver to handle their own callback array.
>>
>> That will have the benefit of removing multiple lines of code in the
>> different drivers.
>>
>> In order to smoothly modify the driver, the 'enter' function are in
>> the driver structure and in the cpuidle state structure. That will
>> let the time to modify the different drivers one by one.
>> So the 'cpuidle_enter' function checks if the 'enter' callback is
>> assigned in the driver structure and use it, otherwise it invokes
>> the 'enter' assigned to the cpuidle_state.
>>
>> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>> ---
>> drivers/cpuidle/cpuidle.c | 4 +++-
>> include/linux/cpuidle.h | 1 +
>> 2 files changed, 4 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
>> index d90519c..155dee7 100644
>> --- a/drivers/cpuidle/cpuidle.c
>> +++ b/drivers/cpuidle/cpuidle.c
>> @@ -46,7 +46,9 @@ static inline int cpuidle_enter(struct cpuidle_device *dev,
>> struct cpuidle_driver *drv, int index)
>> {
>> struct cpuidle_state *target_state = &drv->states[index];
>> - return target_state->enter(dev, drv, index);
>> +
>> + return drv->enter(dev, drv, index) ? drv->enter(dev, drv, index) :
>
> Do you mean:
> drv->enter ? drv->enter(dev, drv, index) :
> ?
>
> Thanks,
> Namhyung
Right :)
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [RFC 1/4] cpuidle: define the enter function in the driver structure
From: Namhyung Kim @ 2012-06-14 7:49 UTC (permalink / raw)
To: Daniel Lezcano; +Cc: lenb, linux-pm, linux-acpi, linux-kernel, linaro-dev
In-Reply-To: <1339171365-4098-1-git-send-email-daniel.lezcano@linaro.org>
Hi,
On Fri, 8 Jun 2012 18:02:42 +0200, Daniel Lezcano wrote:
> We have the state index passed as parameter to the 'enter' function.
> Most of the drivers assign their 'enter' functions several times in
> the cpuidle_state structure, as we have the index, we can delegate
> to the driver to handle their own callback array.
>
> That will have the benefit of removing multiple lines of code in the
> different drivers.
>
> In order to smoothly modify the driver, the 'enter' function are in
> the driver structure and in the cpuidle state structure. That will
> let the time to modify the different drivers one by one.
> So the 'cpuidle_enter' function checks if the 'enter' callback is
> assigned in the driver structure and use it, otherwise it invokes
> the 'enter' assigned to the cpuidle_state.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> drivers/cpuidle/cpuidle.c | 4 +++-
> include/linux/cpuidle.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
> index d90519c..155dee7 100644
> --- a/drivers/cpuidle/cpuidle.c
> +++ b/drivers/cpuidle/cpuidle.c
> @@ -46,7 +46,9 @@ static inline int cpuidle_enter(struct cpuidle_device *dev,
> struct cpuidle_driver *drv, int index)
> {
> struct cpuidle_state *target_state = &drv->states[index];
> - return target_state->enter(dev, drv, index);
> +
> + return drv->enter(dev, drv, index) ? drv->enter(dev, drv, index) :
Do you mean:
drv->enter ? drv->enter(dev, drv, index) :
?
Thanks,
Namhyung
> + target_state->enter(dev, drv, index);
> }
>
> static inline int cpuidle_enter_tk(struct cpuidle_device *dev,
> diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
> index 6c26a3d..d82e169 100644
> --- a/include/linux/cpuidle.h
> +++ b/include/linux/cpuidle.h
> @@ -130,6 +130,7 @@ struct cpuidle_driver {
> struct cpuidle_state states[CPUIDLE_STATE_MAX];
> int state_count;
> int safe_state_index;
> + int (*enter)(struct cpuidle_device *, struct cpuidle_driver *, int);
> };
>
> #ifdef CONFIG_CPU_IDLE
^ permalink raw reply
* RE: Re: [PATCH 1/2] PM: devfreq: add freq table and available_freqs
From: Xiaoguang Chen @ 2012-06-14 5:39 UTC (permalink / raw)
To: myungjoo.ham@samsung.com, Xiaoguang Chen
Cc: linux-kernel@vger.kernel.org, 박경민,
linux-pm@lists.linux-foundation.org
In-Reply-To: <29439113.474411339649027694.JavaMail.weblogic@epml17>
Hi, Myungjoo
the API is optional, but I think one frequency table is better to have.
if user space want to see what is the supported frequencies for the specific devfreq driver, then where do you think we can see this interface?
do we have to go to OPP framework to get it ? or we can just add it in our devfreq ? for example: sys/class/devfreq/xxx-devfreq/available_freqs
I think it is best for us to see this in the same sysfs path.
Thanks
Xiaoguang
-----Original Message-----
From: 함명주 [mailto:myungjoo.ham@samsung.com]
Sent: 2012年6月14日 12:44
To: Xiaoguang Chen
Cc: Xiaoguang Chen; linux-kernel@vger.kernel.org; 박경민; linux-pm@lists.linux-foundation.org
Subject: Re: Re: [PATCH 1/2] PM: devfreq: add freq table and available_freqs
> Hi, Myungjoo
>
>
> what's your opinion?
Hello Xiaoguang,
Still, I don't think we need additional API and ABI for a simple frequency table. Why a devfreq device driver would want to register a table in struct devfreq while it can hold one either with its dev-data, private data of devfreq, or even OPP.
1. Devfreq is not "combined" with OPP. OPP is optional.
2. I guess filling voltage column with some arbitrary values in OPP table won't hurt anything if the device does not care voltage values. (just a suggestion and speculation) Thus, you can still use OPP in your case as long as the frequency values are discrete and not too many.
3. Devfreq and its governors recommends the base frequency to devfreq drivers. Frequency table is only needed to be visible to devfreq drivers, not to governors or devfreq itself. The frequency table you've suggested is not need to be visible to devfreq subsystem.
I still object to adding a frequency table (which is already supported by OPP by not specifying voltage or specifying arbitrary voltage values). However, even if I don't, we won't need that API (devfreq_set_freq_table), which should've been added in device profile at devfreq_add_device() time.
Cheers!
MyungJoo.
>
>
> Thanks
> Xiaoguang
>
>
> > 2012/6/13 Xiaoguang Chen <chenxg.marvell@gmail.com>
> >
> > I think Devfreq should not be combined with OPP, OPP framework does
> > contain one frequency table, but the frequency is combined with voltage. some platforms may don't want to use this but handling voltage seperately in their clock driver.
> >
> >
> > and some platforms don't use OPP, and they want a frequency list.
> > then this is necessary. also devfreq should contain a frequency list even without any other frameworks, don't you think so ?
> >
> >
> > Thanks
> > Xiaoguang
> >
> >
> >
> > 2012/6/13 MyungJoo Ham <myungjoo.ham@samsung.com>
> > >
> > > > Devfreq framework don't have a frequency table, add it for easy
> > > > use.
> > > >
> > > > Signed-off-by: Xiaoguang Chen <chenxg@marvell.com>
> > >
> > >
> > > If you need a predefined data structure to support frequency
> > > table, you can simply use OPP, which has helper functions
> > > implemented in devfreq subsystem. Is there any reason not to use
> > > OPP and to implement another data structure to store a frequency table attached to a device?
> > >
> > >
> > > Cheers!
> > > MyungJoo.
> > >
^ permalink raw reply
* Re: Re: [PATCH 1/2] PM: devfreq: add freq table and available_freqs
From: 함명주 @ 2012-06-14 4:43 UTC (permalink / raw)
To: Xiaoguang Chen
Cc: Xiaoguang Chen, linux-kernel@vger.kernel.org,
박경민, linux-pm@lists.linux-foundation.org
> Hi, Myungjoo
>
>
> what's your opinion?
Hello Xiaoguang,
Still, I don't think we need additional API and ABI for a simple frequency table. Why a devfreq device driver would want to register a table in struct devfreq while it can hold one either with its dev-data, private data of devfreq, or even OPP.
1. Devfreq is not "combined" with OPP. OPP is optional.
2. I guess filling voltage column with some arbitrary values in OPP table won't hurt anything if the device does not care voltage values. (just a suggestion and speculation) Thus, you can still use OPP in your case as long as the frequency values are discrete and not too many.
3. Devfreq and its governors recommends the base frequency to devfreq drivers. Frequency table is only needed to be visible to devfreq drivers, not to governors or devfreq itself. The frequency table you've suggested is not need to be visible to devfreq subsystem.
I still object to adding a frequency table (which is already supported by OPP by not specifying voltage or specifying arbitrary voltage values). However, even if I don't, we won't need that API (devfreq_set_freq_table), which should've been added in device profile at devfreq_add_device() time.
Cheers!
MyungJoo.
>
>
> Thanks
> Xiaoguang
>
>
> > 2012/6/13 Xiaoguang Chen <chenxg.marvell@gmail.com>
> >
> > I think Devfreq should not be combined with OPP,
> > OPP framework does contain one frequency table, but the frequency is combined with voltage. some platforms may don't want to use this but handling voltage seperately in their clock driver.
> >
> >
> > and some platforms don't use OPP, and they want a frequency list.
> > then this is necessary. also devfreq should contain a frequency list even without any other frameworks, don't you think so ?
> >
> >
> > Thanks
> > Xiaoguang
> >
> >
> >
> > 2012/6/13 MyungJoo Ham <myungjoo.ham@samsung.com>
> > >
> > > > Devfreq framework don't have a frequency table, add it
> > > > for easy use.
> > > >
> > > > Signed-off-by: Xiaoguang Chen <chenxg@marvell.com>
> > >
> > >
> > > If you need a predefined data structure to support frequency table,
> > > you can simply use OPP, which has helper functions implemented in
> > > devfreq subsystem. Is there any reason not to use OPP and to implement
> > > another data structure to store a frequency table attached to a device?
> > >
> > >
> > > Cheers!
> > > MyungJoo.
> > >
^ permalink raw reply
* PM_RUNTIME and device driver PM
From: Chao Xie @ 2012-06-14 3:13 UTC (permalink / raw)
To: linux-pm, linux-kernel, rjw, pavel
hi
PM_RUNTIME provide a way for device driver do runtime PM. so for some
devices, they have some surrounded logic. For example, the device may
get clock from outside, or it need PHY support(USB is a example).
To get these dependency out of device driver, i define a struct
dev_pm_domain, and make dev.pm_domain point to it. So in the device
driver, when the hardware should be enabled, we can call
pm_runtime_get_sync while when the hardware is idle or does not work,
we can call pm_runtime_put_sync.
It seems work well, but i have question about the suspend/resume of
device. When the whole system will go to deep idle, and it will
suspend the devices. for the function do device suspend
__device_suspend, it will call pm_runtime_get_noresume(dev). As i
think it will make the device not do runtime suspend any more. Is that
correct?
There is the question, how device driver handle the logic surrounds
it? I want to add pm_runtime_put_sync in dev->driver->pm->suspend
function, and pm_runtime_get_sync in dev->driver->pm->resume. Because
__device_suspend increase the usage_count, pm_runtime_put_sync will
not do real work.
So is that right that i directly call pm_runtime_suspend in
dev->driver->pm->suspend and pm_runtime_resume in
dev->driver->pm->resume?
Thanks.
^ permalink raw reply
* Re: [PATCH 1/2] PM: devfreq: add freq table and available_freqs
From: Xiaoguang Chen @ 2012-06-14 1:50 UTC (permalink / raw)
To: myungjoo.ham
Cc: 박경민, Xiaoguang Chen,
linux-kernel@vger.kernel.org, linux-pm
In-Reply-To: <CAFgnuDfMVfimmYTQdB-vxCJPdB_x_nbwmd-2su45en4SpJeiow@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 5480 bytes --]
Hi, Myungjoo
what's your opinion?
Thanks
Xiaoguang
2012/6/13 Xiaoguang Chen <chenxg.marvell@gmail.com>
> I think Devfreq should not be combined with OPP,
> OPP framework does contain one frequency table, but the frequency is
> combined with voltage. some platforms may don't want to use this but
> handling voltage seperately in their clock driver.
>
> and some platforms don't use OPP, and they want a frequency list.
> then this is necessary. also devfreq should contain a frequency list even
> without any other frameworks, don't you think so ?
>
> Thanks
> Xiaoguang
>
>
> 2012/6/13 MyungJoo Ham <myungjoo.ham@samsung.com>
>
>> > Devfreq framework don't have a frequency table, add it
>> > for easy use.
>> >
>> > Signed-off-by: Xiaoguang Chen <chenxg@marvell.com>
>>
>> If you need a predefined data structure to support frequency table,
>> you can simply use OPP, which has helper functions implemented in
>> devfreq subsystem. Is there any reason not to use OPP and to implement
>> another data structure to store a frequency table attached to a device?
>>
>>
>> Cheers!
>> MyungJoo.
>>
>> > ---
>> > drivers/devfreq/devfreq.c | 26 ++++++++++++++++++++++++++
>> > include/linux/devfreq.h | 12 ++++++++++++
>> > 2 files changed, 38 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
>> > index 70c31d4..2144200 100644
>> > --- a/drivers/devfreq/devfreq.c
>> > +++ b/drivers/devfreq/devfreq.c
>> > @@ -460,6 +460,17 @@ int devfreq_remove_device(struct devfreq *devfreq)
>> > return 0;
>> > }
>> >
>> > +/*
>> > + * devfreq_set_freq_table()- Set frequency table for devfreq
>> > + * @devfreq The devfreq instance
>> > + * @table The frequency table that device supports
>> > + */
>> > +void devfreq_set_freq_table(struct devfreq *devfreq,
>> > + struct devfreq_frequency_table *table)
>> > +{
>> > + devfreq->freq_table = table;
>> > +}
>> > +
>> > static ssize_t show_governor(struct device *dev,
>> > struct device_attribute *attr, char *buf)
>> > {
>> > @@ -472,6 +483,20 @@ static ssize_t show_freq(struct device *dev,
>> > return sprintf(buf, "%lu\n", to_devfreq(dev)->previous_freq);
>> > }
>> >
>> > +static ssize_t show_avail_freq(struct device *dev,
>> > + struct device_attribute *attr, char *buf)
>> > +{
>> > + int len = 0, i;
>> > + struct devfreq *devfreq = to_devfreq(dev);
>> > + if (devfreq->freq_table)
>> > + for (i = 0; devfreq->freq_table[i].frequency !=
>> DEVFREQ_TABLE_END; i++)
>> > + len += sprintf(buf + len, "%lu\n",
>> > + devfreq->freq_table[i].frequency);
>> > + if (len == 0)
>> > + len += sprintf(buf + len, "No frequency table is
>> provided\n");
>> > + return len;
>> > +}
>> > +
>> > static ssize_t show_polling_interval(struct device *dev,
>> > struct device_attribute *attr, char
>> *buf)
>> > {
>> > @@ -595,6 +620,7 @@ static struct device_attribute devfreq_attrs[] = {
>> > store_polling_interval),
>> > __ATTR(min_freq, S_IRUGO | S_IWUSR, show_min_freq,
>> store_min_freq),
>> > __ATTR(max_freq, S_IRUGO | S_IWUSR, show_max_freq,
>> store_max_freq),
>> > + __ATTR(available_freqs, S_IRUGO, show_avail_freq, NULL),
>> > { },
>> > };
>> >
>> > diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
>> > index 281c72a..e5e4036 100644
>> > --- a/include/linux/devfreq.h
>> > +++ b/include/linux/devfreq.h
>> > @@ -52,6 +52,14 @@ struct devfreq_dev_status {
>> > */
>> > #define DEVFREQ_FLAG_LEAST_UPPER_BOUND 0x1
>> >
>> > +#define DEVFREQ_ENTRY_INVALID (~0)
>> > +#define DEVFREQ_TABLE_END (~1)
>> > +
>> > +struct devfreq_frequency_table {
>> > + unsigned int index;
>> > + unsigned long frequency;
>> > +};
>> > +
>> > /**
>> > * struct devfreq_dev_profile - Devfreq's user device profile
>> > * @initial_freq The operating frequency when devfreq_add_device()
>> is
>> > @@ -130,6 +138,7 @@ struct devfreq_governor {
>> > * "devfreq_monitor" executions to reevaluate
>> > * frequency/voltage of the device. Set by
>> > * profile's polling_ms interval.
>> > + * @freq_table The frequency table that device supports
>> > * @data Private data of the governor. The devfreq framework does
>> not
>> > * touch this.
>> > * @being_removed a flag to mark that this object is being removed
>> in
>> > @@ -157,6 +166,7 @@ struct devfreq {
>> > unsigned long polling_jiffies;
>> > unsigned long previous_freq;
>> > unsigned int next_polling;
>> > + struct devfreq_frequency_table *freq_table;
>> >
>> > void *data; /* private data for governors */
>> >
>> > @@ -180,6 +190,8 @@ extern int devfreq_register_opp_notifier(struct
>> device *dev,
>> > struct devfreq *devfreq);
>> > extern int devfreq_unregister_opp_notifier(struct device *dev,
>> > struct devfreq *devfreq);
>> > +extern void devfreq_set_freq_table(struct devfreq *devfreq,
>> > + struct devfreq_frequency_table *table);
>> >
>> > #ifdef CONFIG_DEVFREQ_GOV_POWERSAVE
>> > extern const struct devfreq_governor devfreq_powersave;
>> > --
>> > 1.7.0.4
>> >
>>
>
>
[-- Attachment #2: Type: text/html, Size: 6946 bytes --]
^ permalink raw reply
* Re: [PATCH] PCI: add NO_D3_DURING_SLEEP flag and revert 151b61284776be2
From: Steven Rostedt @ 2012-06-13 20:17 UTC (permalink / raw)
To: Greg KH
Cc: Rafael J. Wysocki, Alan Stern, Oleksij Rempel (fishor),
Dâniel Fraga, Andrey Rahmatullin,
linux-pm-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, USB list
In-Reply-To: <1339618548.13377.162.camel-f9ZlEuEWxVcI6MkJdU+c8EEOCMrvLtNR@public.gmane.org>
On Wed, 2012-06-13 at 16:15 -0400, Steven Rostedt wrote:
> One of you (or both) need to learn to use NTP, or perhaps, as we all
> suspect, Greg is really psychic.
Or maybe it's just that time moves faster at GregKH altitude.
-- Steve
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* Re: [PATCH] PCI: add NO_D3_DURING_SLEEP flag and revert 151b61284776be2
From: Steven Rostedt @ 2012-06-13 20:15 UTC (permalink / raw)
To: Greg KH
Cc: Rafael J. Wysocki, Alan Stern, Oleksij Rempel (fishor),
Dâniel Fraga, Andrey Rahmatullin,
linux-pm-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, USB list
In-Reply-To: <20120613200310.GA11110-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
On Wed, 2012-06-13 at 13:03 -0700, Greg KH wrote:
> On Wed, Jun 13, 2012 at 10:04:43PM +0200, Rafael J. Wysocki wrote:
13:03 -0700 == 20:03 UTC
10:04PM +0200 == 22:04 +0200 == 20:04 UTC
> >
> > Please take it, if that's not a problem, I don't have any other
> > patches for 3.5 pending. And please add:
> >
> > Reviewed-by: Rafael J. Wysocki <rjw-KKrjLPT3xs0@public.gmane.org>
>
> Ok, I'll go queue it up right now.
>
> greg k-h
One of you (or both) need to learn to use NTP, or perhaps, as we all
suspect, Greg is really psychic.
-- Steve
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