* Re: [PATCH v2] acpi: intel_idle : break dependency between modules
From: Srivatsa S. Bhat @ 2012-06-28 11:24 UTC (permalink / raw)
To: Daniel Lezcano
Cc: trenn, deepthi, linux-acpi, linux-pm, linux-pm, lenb, rjw, x86,
linux-kernel, linaro-dev
In-Reply-To: <1340873202-2476-1-git-send-email-daniel.lezcano@linaro.org>
On 06/28/2012 02:16 PM, Daniel Lezcano wrote:
> When the system is booted with some cpus offline, the idle
> driver is not initialized. When a cpu is set online, the
> acpi code call the intel idle init function. Unfortunately
> this code introduce a dependency between intel_idle and acpi.
>
> This patch is intended to remove this dependency by using the
> notifier of intel_idle. This patch has the benefit of
> encapsulating the intel_idle driver and remove some exported
> functions.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Looks good to me.
Regards,
Srivatsa S. Bhat
> ---
> drivers/acpi/processor_driver.c | 7 ------
> drivers/idle/intel_idle.c | 41 +++++++++++++++++++++++++-------------
> include/linux/cpuidle.h | 7 ------
> 3 files changed, 27 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
> index 0734086..8648b29 100644
> --- a/drivers/acpi/processor_driver.c
> +++ b/drivers/acpi/processor_driver.c
> @@ -427,18 +427,11 @@ static int acpi_cpu_soft_notify(struct notifier_block *nfb,
> * Initialize missing things
> */
> if (pr->flags.need_hotplug_init) {
> - struct cpuidle_driver *idle_driver =
> - cpuidle_get_driver();
> -
> printk(KERN_INFO "Will online and init hotplugged "
> "CPU: %d\n", pr->id);
> WARN(acpi_processor_start(pr), "Failed to start CPU:"
> " %d\n", pr->id);
> pr->flags.need_hotplug_init = 0;
> - if (idle_driver && !strcmp(idle_driver->name,
> - "intel_idle")) {
> - intel_idle_cpu_init(pr->id);
> - }
> /* Normal CPU soft online event */
> } else {
> acpi_processor_ppc_has_changed(pr, 0);
> diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> index d0f59c3..fe95d54 100644
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -96,6 +96,7 @@ static const struct idle_cpu *icpu;
> static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
> static int intel_idle(struct cpuidle_device *dev,
> struct cpuidle_driver *drv, int index);
> +static int intel_idle_cpu_init(int cpu);
>
> static struct cpuidle_state *cpuidle_state_table;
>
> @@ -302,22 +303,35 @@ static void __setup_broadcast_timer(void *arg)
> clockevents_notify(reason, &cpu);
> }
>
> -static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
> - unsigned long action, void *hcpu)
> +static int cpu_hotplug_notify(struct notifier_block *n,
> + unsigned long action, void *hcpu)
> {
> int hotcpu = (unsigned long)hcpu;
> + struct cpuidle_device *dev;
>
> switch (action & 0xf) {
> case CPU_ONLINE:
> - smp_call_function_single(hotcpu, __setup_broadcast_timer,
> - (void *)true, 1);
> +
> + if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
> + smp_call_function_single(hotcpu, __setup_broadcast_timer,
> + (void *)true, 1);
> +
> + /*
> + * Some systems can hotplug a cpu at runtime after
> + * the kernel has booted, we have to initialize the
> + * driver in this case
> + */
> + dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
> + if (!dev->registered)
> + intel_idle_cpu_init(hotcpu);
> +
> break;
> }
> return NOTIFY_OK;
> }
>
> -static struct notifier_block setup_broadcast_notifier = {
> - .notifier_call = setup_broadcast_cpuhp_notify,
> +static struct notifier_block cpu_hotplug_notifier = {
> + .notifier_call = cpu_hotplug_notify,
> };
>
> static void auto_demotion_disable(void *dummy)
> @@ -405,10 +419,10 @@ static int intel_idle_probe(void)
>
> if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
> lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
> - else {
> + else
> on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
> - register_cpu_notifier(&setup_broadcast_notifier);
> - }
> +
> + register_cpu_notifier(&cpu_hotplug_notifier);
>
> pr_debug(PREFIX "v" INTEL_IDLE_VERSION
> " model 0x%X\n", boot_cpu_data.x86_model);
> @@ -494,7 +508,7 @@ static int intel_idle_cpuidle_driver_init(void)
> * allocate, initialize, register cpuidle_devices
> * @cpu: cpu/core to initialize
> */
> -int intel_idle_cpu_init(int cpu)
> +static int intel_idle_cpu_init(int cpu)
> {
> int cstate;
> struct cpuidle_device *dev;
> @@ -539,7 +553,6 @@ int intel_idle_cpu_init(int cpu)
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(intel_idle_cpu_init);
>
> static int __init intel_idle_init(void)
> {
> @@ -581,10 +594,10 @@ static void __exit intel_idle_exit(void)
> intel_idle_cpuidle_devices_uninit();
> cpuidle_unregister_driver(&intel_idle_driver);
>
> - if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
> +
> + if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
> on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
> - unregister_cpu_notifier(&setup_broadcast_notifier);
> - }
> + unregister_cpu_notifier(&cpu_hotplug_notifier);
>
> return;
> }
> diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
> index 5ab7183..66d7e0d 100644
> --- a/include/linux/cpuidle.h
> +++ b/include/linux/cpuidle.h
> @@ -213,14 +213,7 @@ struct cpuidle_governor {
> extern int cpuidle_register_governor(struct cpuidle_governor *gov);
> extern void cpuidle_unregister_governor(struct cpuidle_governor *gov);
>
> -#ifdef CONFIG_INTEL_IDLE
> -extern int intel_idle_cpu_init(int cpu);
> #else
> -static inline int intel_idle_cpu_init(int cpu) { return -1; }
> -#endif
> -
> -#else
> -static inline int intel_idle_cpu_init(int cpu) { return -1; }
>
> static inline int cpuidle_register_governor(struct cpuidle_governor *gov)
> {return 0;}
>
^ permalink raw reply
* Re: [PATCH] acpi: intel_idle : break dependency between modules
From: Srivatsa S. Bhat @ 2012-06-28 11:23 UTC (permalink / raw)
To: Thomas Renninger
Cc: x86, linaro-dev, linux-pm, linux-kernel, linux-acpi, linux-pm
In-Reply-To: <201206280934.48147.trenn@suse.de>
On 06/28/2012 01:04 PM, Thomas Renninger wrote:
> On Wednesday, June 27, 2012 06:16:33 PM Srivatsa S. Bhat wrote:
>> On 06/27/2012 02:37 PM, Daniel Lezcano wrote:
>>> When the system is booted with some cpus offline, the idle
>>> driver is not initialized. When a cpu is set online, the
>>> acpi code call the intel idle init function. Unfortunately
>>> this code introduce a dependency between intel_idle and acpi.
>>>
>>> This patch is intended to remove this dependency by using the
>>> notifier of intel_idle. In order to make it work, the notifier
>>> must be initialized in the right order, acpi then intel_idle.
>>> This is done in the Makefile.
>>
>> There is a much better way of doing this. See below.
>>
>>> This patch has the benefit of
>>> encapsulating the intel_idle driver and remove some exported
>>> functions.
>>>
>>
>> Nice :)
>>
>>> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>>> ---
>>> drivers/Makefile | 3 ++-
>>> drivers/acpi/processor_driver.c | 7 -------
>>> drivers/idle/intel_idle.c | 22 ++++++++++++++--------
>>> include/linux/cpuidle.h | 7 -------
>>> 4 files changed, 16 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index 2ba29ff..a2454b8 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile
>>> @@ -12,8 +12,9 @@ obj-$(CONFIG_PCI) += pci/
>>> obj-$(CONFIG_PARISC) += parisc/
>>> obj-$(CONFIG_RAPIDIO) += rapidio/
>>> obj-y += video/
>>> -obj-y += idle/
>>> +# acpi must come before idle for initialization
>>> obj-$(CONFIG_ACPI) += acpi/
>>> +obj-y += idle/
>>> obj-$(CONFIG_SFI) += sfi/
>>> # PnP must come after ACPI since it will eventually need to check if acpi
>>> # was used and do nothing if so
>>
>> OK, so all you are trying to do here is ensure that the intel idle related
>> notifier runs _after_ the acpi related one.
> I might oversee something, if you have concerns, please point me to it.
> If it's all about keeping the order of excuting these functions:
> acpi_processor_start(pr)
> and
> intel_idle_cpu_init()
> There should be no need for it. Intel idle is pretty separated.
>
I digged through the code a bit, and even I couldn't find any reason why there
should be a dependency between the two events.
Regards,
Srivatsa S. Bhat
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Valentin, Eduardo @ 2012-06-28 10:55 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <CAGF5oy85XSfBtV_WFwYyWDHYmBbLGHK_9c9XhTFs1CgnSfyMLA@mail.gmail.com>
Hello again,
On Thu, Jun 28, 2012 at 1:51 PM, Valentin, Eduardo
<eduardo.valentin@ti.com> wrote:
> Hello,
>
> On Thu, Jun 28, 2012 at 1:26 PM, Konstantin Baydarov
> <kbaidarov@dev.rtsoft.ru> wrote:
>> On 06/28/2012 02:12 PM, Konstantin Baydarov wrote:
>>> The interface(design) of omap-control-core.c has already been discussed many times :(
>>> Eduardo, in his patch set, suggested following design:
>>> - omap-control-core.c ioremaps SCM window and provide functions to read/write SCP register for bandgap and usb.
>>>
>>> IIRC, this approach didn't satisfy and it was suggested to have private read/write in bandgap and usb.
>>>
>>> So, my patch set introduces following design:
>>> - omap-control-core.c don't provide read/write functions for bandgap and usb.
>>> - bandgap and usb use their own private read/write functions
>>> - Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped to the same virtual address. But the problem is that SMP memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach.
>> I mean:
>>
>> - Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped. So each call of ioremap in omap-control-core.c, bandgap and usb drivers returns the same virtual address. But the problem is that SCM memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach(when each driver remaps the same IOMEM).
>>
>>>
>>> Another possible design is:
>>> - omap-control-core.c ioremaps and reserves SCM IOMEM window
>>> - omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
>>> - Bandgap and usb phy uses their own private read/write function.
>>> IIUC, this way was suggested by Tony.
>
> Well I understood slightly different :-)
>
> I think the point is not really where to put the access functions, but
> to have each driver handling a separate part of the the io window. As
> I said before, so that they don't access each other io area.
>
> If you have 1 io window, for the above mentioned constraint, you won't
> protect anything. So, in that sense, it doesn't make much difference
> if you have access functions in core, or in the children, as they are
> all sharing the same io window. Of course, in case we put only 1 io
> window, for me it is safer if that window is managed in only one
> place, instead of several places.
>
> The question is then, can we split the io area into smaller windows
> for each children? Considering the children registers are not
> contiguous :-(. In theory we can put several entries in the 'reg' DT
> property, but that becomes a bit messy as it will change depending on
> OMAP version. Anyways, if we split the scm io window into several io
> smaller areas/chunks, then it makes sense to have access functions in
> each children.
>
>>>
>>> I guess It's better to settle the design(interface) of omap-control-core.c, bandgap and usb phy and then submit the next version of patch set.
>>
>
> Agreed. Here. We need to decide how to have this design and stick to it.
Once the design is agreed, the series can probably be split into
parts, so we can have the scm core and its children worked separately
>
>
> --
>
> Eduardo Valentin
--
Eduardo Valentin
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Valentin, Eduardo @ 2012-06-28 10:51 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEC3154.9050103@dev.rtsoft.ru>
Hello,
On Thu, Jun 28, 2012 at 1:26 PM, Konstantin Baydarov
<kbaidarov@dev.rtsoft.ru> wrote:
> On 06/28/2012 02:12 PM, Konstantin Baydarov wrote:
>> The interface(design) of omap-control-core.c has already been discussed many times :(
>> Eduardo, in his patch set, suggested following design:
>> - omap-control-core.c ioremaps SCM window and provide functions to read/write SCP register for bandgap and usb.
>>
>> IIRC, this approach didn't satisfy and it was suggested to have private read/write in bandgap and usb.
>>
>> So, my patch set introduces following design:
>> - omap-control-core.c don't provide read/write functions for bandgap and usb.
>> - bandgap and usb use their own private read/write functions
>> - Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped to the same virtual address. But the problem is that SMP memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach.
> I mean:
>
> - Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped. So each call of ioremap in omap-control-core.c, bandgap and usb drivers returns the same virtual address. But the problem is that SCM memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach(when each driver remaps the same IOMEM).
>
>>
>> Another possible design is:
>> - omap-control-core.c ioremaps and reserves SCM IOMEM window
>> - omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
>> - Bandgap and usb phy uses their own private read/write function.
>> IIUC, this way was suggested by Tony.
Well I understood slightly different :-)
I think the point is not really where to put the access functions, but
to have each driver handling a separate part of the the io window. As
I said before, so that they don't access each other io area.
If you have 1 io window, for the above mentioned constraint, you won't
protect anything. So, in that sense, it doesn't make much difference
if you have access functions in core, or in the children, as they are
all sharing the same io window. Of course, in case we put only 1 io
window, for me it is safer if that window is managed in only one
place, instead of several places.
The question is then, can we split the io area into smaller windows
for each children? Considering the children registers are not
contiguous :-(. In theory we can put several entries in the 'reg' DT
property, but that becomes a bit messy as it will change depending on
OMAP version. Anyways, if we split the scm io window into several io
smaller areas/chunks, then it makes sense to have access functions in
each children.
>>
>> I guess It's better to settle the design(interface) of omap-control-core.c, bandgap and usb phy and then submit the next version of patch set.
>
Agreed. Here. We need to decide how to have this design and stick to it.
--
Eduardo Valentin
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Konstantin Baydarov @ 2012-06-28 10:26 UTC (permalink / raw)
To: Valentin, Eduardo
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap
In-Reply-To: <4FEC2E1D.5040309@dev.rtsoft.ru>
On 06/28/2012 02:12 PM, Konstantin Baydarov wrote:
> The interface(design) of omap-control-core.c has already been discussed many times :(
> Eduardo, in his patch set, suggested following design:
> - omap-control-core.c ioremaps SCM window and provide functions to read/write SCP register for bandgap and usb.
>
> IIRC, this approach didn't satisfy and it was suggested to have private read/write in bandgap and usb.
>
> So, my patch set introduces following design:
> - omap-control-core.c don't provide read/write functions for bandgap and usb.
> - bandgap and usb use their own private read/write functions
> - Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped to the same virtual address. But the problem is that SMP memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach.
I mean:
- Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped. So each call of ioremap in omap-control-core.c, bandgap and usb drivers returns the same virtual address. But the problem is that SCM memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach(when each driver remaps the same IOMEM).
>
> Another possible design is:
> - omap-control-core.c ioremaps and reserves SCM IOMEM window
> - omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
> - Bandgap and usb phy uses their own private read/write function.
> IIUC, this way was suggested by Tony.
>
> I guess It's better to settle the design(interface) of omap-control-core.c, bandgap and usb phy and then submit the next version of patch set.
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Konstantin Baydarov @ 2012-06-28 10:12 UTC (permalink / raw)
To: Valentin, Eduardo
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap
In-Reply-To: <CAGF5oy9heLnjcHj4H=hMK9NAkrDoOocR-Lbv1Z4cQ4G1C5kSeQ@mail.gmail.com>
Hello.
On 06/28/2012 01:49 PM, Valentin, Eduardo wrote:
> Hello,
>
> On Thu, Jun 28, 2012 at 12:37 PM, Konstantin Baydarov
> <kbaidarov@dev.rtsoft.ru> wrote:
>> Hi.
>>
>> On 06/28/2012 08:50 AM, Eduardo Valentin wrote:
>>> Hello,
>>>
>>> On Wed, Jun 27, 2012 at 10:04:54PM +0400, Konstantin Baydarov wrote:
>>>> This patch introduces a MFD core device driver for OMAP system control module.
>>>>
>>>> The control module allows software control of various static modes supported by the device.
>>>> It is composed of two control submodules: general control module and device (padconfiguration) control module.
>>>>
>>>> Changes since previous version:
>>>> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
>>>> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
>>>> Probably, no configuration option is required!
>>>> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
>>>> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
>>>> module device.
>>>> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
>>>> - omap-control-core: added omap_control_status_read that is used early in omap_type
>>>>
>>>> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
>>>> Signed-off-by: J Keerthy <j-keerthy@ti.com>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
>>>> ---
>>>> .../devicetree/bindings/mfd/omap_control.txt | 44 +++++++
>>>> arch/arm/mach-omap2/Kconfig | 1 +
>>>> arch/arm/plat-omap/Kconfig | 4 +
>>>> drivers/mfd/Kconfig | 9 ++
>>>> drivers/mfd/Makefile | 1 +
>>>> drivers/mfd/omap-control-core.c | 131 ++++++++++++++++++++
>>>> include/linux/mfd/omap_control.h | 52 ++++++++
>>>> 7 files changed, 242 insertions(+), 0 deletions(-)
>>>> create mode 100644 Documentation/devicetree/bindings/mfd/omap_control.txt
>>>> create mode 100644 drivers/mfd/omap-control-core.c
>>>> create mode 100644 include/linux/mfd/omap_control.h
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mfd/omap_control.txt b/Documentation/devicetree/bindings/mfd/omap_control.txt
>>>> new file mode 100644
>>>> index 0000000..46d5e7e
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/mfd/omap_control.txt
>>>> @@ -0,0 +1,44 @@
>>>> +* Texas Instrument OMAP System Control Module (SCM) bindings
>>>> +
>>>> +The control module allows software control of various static modes supported by
>>>> +the device. The control module controls the settings of various device modules
>>>> +through register configuration and internal signals. It also controls the pad
>>>> +configuration, pin functional multiplexing, and the routing of internal signals
>>>> +(such as PRCM signals or DMA requests) to output pins configured for hardware
>>>> +observability.
>>>> +
>>>> +Required properties:
>>>> +- compatible : Should be:
>>>> + - "ti,omap3-control" for OMAP3 support
>>>> + - "ti,omap4-control" for OMAP4 support
>>>> + - "ti,omap5-control" for OMAP5 support
>>>> +
>>>> +OMAP specific properties:
>>>> +- ti,hwmods: Name of the hwmod associated to the control module:
>>>> + Should be "ctrl_module_core";
>>>> +
>>>> +Sub-nodes:
>>>> +- bandgap : contains the bandgap node
>>>> +
>>>> + The bindings details of individual bandgap device can be found in:
>>>> + Documentation/devicetree/bindings/thermal/omap_bandgap.txt
>>>> +
>>>> +- usb : contains the usb phy pin control node
>>>> +
>>>> + The only required property for this child is:
>>>> + - compatible = "ti,omap4-control-usb";
>>>> +
>>>> +Examples:
>>>> +
>>>> +ctrl_module_core: ctrl_module_core@4a002000 {
>>>> + compatible = "ti,omap4-control";
>>>> + ti,hwmods = "ctrl_module_core";
>>>> + bandgap {
>>>> + compatible = "ti,omap4460-bandgap";
>>> You need to update the documentation if change the DT structure.
>> Ok.
>>>> + interrupts = <0 126 4>; /* talert */
>>>> + ti,tshut-gpio = <86>; /* tshut */
>>>> + };
>>>> + usb {
>>>> + compatible = "ti,omap4-usb-phy";
>>>> + };
>>>> +};
>>>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>>>> index 4cf5142..c2ef07c 100644
>>>> --- a/arch/arm/mach-omap2/Kconfig
>>>> +++ b/arch/arm/mach-omap2/Kconfig
>>>> @@ -52,6 +52,7 @@ config ARCH_OMAP4
>>>> select PL310_ERRATA_727915
>>>> select ARM_ERRATA_720789
>>>> select ARCH_HAS_OPP
>>>> + select ARCH_HAS_CONTROL_MODULE
>>>> select PM_OPP if PM
>>>> select USB_ARCH_HAS_EHCI if USB_SUPPORT
>>>> select ARM_CPU_SUSPEND if PM
>>>> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
>>>> index ad95c7a..0f9b575 100644
>>>> --- a/arch/arm/plat-omap/Kconfig
>>>> +++ b/arch/arm/plat-omap/Kconfig
>>>> @@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
>>>> config ARCH_OMAP_OTG
>>>> bool
>>>>
>>>> +config ARCH_HAS_CONTROL_MODULE
>>>> + bool
>>>> + select MFD_OMAP_CONTROL
>>>> +
>>> OK now I got what you meant in patch 0. Fine for me.
>>>
>>>> choice
>>>> prompt "OMAP System Type"
>>>> default ARCH_OMAP2PLUS
>>>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>>>> index e129c82..d0c5456 100644
>>>> --- a/drivers/mfd/Kconfig
>>>> +++ b/drivers/mfd/Kconfig
>>>> @@ -822,6 +822,15 @@ config MFD_WL1273_CORE
>>>> driver connects the radio-wl1273 V4L2 module and the wl1273
>>>> audio codec.
>>>>
>>>> +config MFD_OMAP_CONTROL
>>>> + bool "Texas Instruments OMAP System control module"
>>>> + depends on ARCH_HAS_CONTROL_MODULE
>>>> + help
>>>> + This is the core driver for system control module. This driver
>>>> + is responsible for creating the control module mfd child,
>>>> + like USB-pin control, pin muxing, MMC-pbias and DDR IO dynamic
>>>> + change for off mode.
>>>> +
>>>> config MFD_OMAP_USB_HOST
>>>> bool "Support OMAP USBHS core driver"
>>>> depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
>>>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>>>> index 75f6ed6..b037443 100644
>>>> --- a/drivers/mfd/Makefile
>>>> +++ b/drivers/mfd/Makefile
>>>> @@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
>>>> obj-$(CONFIG_MFD_VX855) += vx855.o
>>>> obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
>>>> obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
>>>> +obj-$(CONFIG_MFD_OMAP_CONTROL) += omap-control-core.o
>>>> obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
>>>> obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
>>>> obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
>>>> diff --git a/drivers/mfd/omap-control-core.c b/drivers/mfd/omap-control-core.c
>>>> new file mode 100644
>>>> index 0000000..724c51b
>>>> --- /dev/null
>>>> +++ b/drivers/mfd/omap-control-core.c
>>>> @@ -0,0 +1,131 @@
>>>> +/*
>>>> + * OMAP system control module driver file
>>>> + *
>>>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>>>> + * Contacts:
>>>> + * Based on original code written by:
>>>> + * J Keerthy <j-keerthy@ti.com>
>>>> + * Moiz Sonasath <m-sonasath@ti.com>
>>>> + * MFD clean up and re-factoring:
>>>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> + * modify it under the terms of the GNU General Public License
>>>> + * version 2 as published by the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful, but
>>>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>>>> + * General Public License for more details.
>>>> + *
>>>> + */
>>>> +
>>>> +#include <linux/module.h>
>>>> +#include <linux/export.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/slab.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/of_platform.h>
>>>> +#include <linux/of_address.h>
>>>> +#include <linux/mfd/core.h>
>>>> +#include <linux/mfd/omap_control.h>
>>>> +
>>>> +#include <linux/of.h>
>>>> +#include <linux/of_address.h>
>>>> +
>>>> +void __iomem *omap_control_base;
>>>> +
>>>> +u32 omap_control_status_read(u16 offset)
>>>> +{
>>>> + return __raw_readl(omap_control_base + (offset));
>>>> +}
>>>> +
>>>> +static const struct of_device_id of_omap_control_match[] = {
>>>> + { .compatible = "ti,omap3-control", },
>>>> + { .compatible = "ti,omap4-control", },
>>>> + { .compatible = "ti,omap5-control", },
>>>> + { },
>>>> +};
>>>> +
>>>> +static int __devinit omap_control_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct device *dev = &pdev->dev;
>>>> + struct device_node *np = dev->of_node;
>>>> +
>>>> + /*
>>>> + * Build child defvices of ctrl_module_core
>>>> + */
>>>> + return of_platform_populate(np, of_omap_control_match, NULL, dev);
>>>> +}
>>>> +
>>>> +
>>>> +static struct platform_driver omap_control_driver = {
>>>> + .probe = omap_control_probe,
>>>> + .driver = {
>>>> + .name = "omap-control-core",
>>>> + .owner = THIS_MODULE,
>>>> + .of_match_table = of_omap_control_match,
>>>> + },
>>>> +};
>>>> +
>>>> +int __init omap_control_of_init(struct device_node *node,
>>>> + struct device_node *parent)
>>>> +{
>>>> + struct resource res;
>>>> +
>>>> + if (WARN_ON(!node))
>>>> + return -ENODEV;
>>>> +
>>>> + if (of_address_to_resource(node, 0, &res)) {
>>>> + WARN(1, "unable to get intc registers\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>> The above function is used nowhere.
>> Agree.
>>>> +
>>>> +void __init of_omap_control_init(const struct of_device_id *matches)
>>>> +{
>>>> + struct device_node *np;
>>>> + struct property *pp = 0;
>>>> + unsigned long phys_base = 0;
>>>> + size_t mapsize = 0;
>>>> +
>>>> + for_each_matching_node(np, matches) {
>>>> +
>>>> + pp = of_find_property(np, "reg", NULL);
>>>> + if(pp) {
>>>> + phys_base = (unsigned long)be32_to_cpup(pp->value);
>>>> + mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
>>>> + omap_control_base = ioremap(phys_base, mapsize);
>>> How the reservation is going to work?
>> This can be done following way:
>> - omap-control-core.c ioremaps and reserves SCM IOMEM window
>> - omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
>> IIUC, this way was suggested by Tony.
> how better is this way compared to having the access functions in the
> core? This way we just replicate the access functions in every
> children.
>
> I believe the suggestion was to have the ioremap and request done in
> chunks. So that children dont step into each other ioarea. But then
> again that can be a bit painful as the children registers are not
> contiguous.
The interface(design) of omap-control-core.c has already been discussed many times :(
Eduardo, in his patch set, suggested following design:
- omap-control-core.c ioremaps SCM window and provide functions to read/write SCP register for bandgap and usb.
IIRC, this approach didn't satisfy and it was suggested to have private read/write in bandgap and usb.
So, my patch set introduces following design:
- omap-control-core.c don't provide read/write functions for bandgap and usb.
- bandgap and usb use their own private read/write functions
- Each omap-control-core.c, bandgap and usb drivers remap SCM window. It's OK because SCM window is statically mapped to the same virtual address. But the problem is that SMP memory window isn't protected. I'm not sure whether it's possible to protect SCM window using this approach.
Another possible design is:
- omap-control-core.c ioremaps and reserves SCM IOMEM window
- omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
- Bandgap and usb phy uses their own private read/write function.
IIUC, this way was suggested by Tony.
I guess It's better to settle the design(interface) of omap-control-core.c, bandgap and usb phy and then submit the next version of patch set.
>
>>>> + }
>>>> + }
>>>> +}
>>>> +
>>>> +static int __init
>>>> +omap_control_early_initcall(void)
>>>> +{
>>>> + of_omap_control_init(of_omap_control_match);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +early_initcall(omap_control_early_initcall);
>>>> +
>>>> +static int __init omap_control_init(void)
>>>> +{
>>>> + return platform_driver_register(&omap_control_driver);
>>>> +}
>>>> +postcore_initcall_sync(omap_control_init);
>>>> +
>>>> +static void __exit omap_control_exit(void)
>>>> +{
>>>> + platform_driver_unregister(&omap_control_driver);
>>>> +}
>>>> +module_exit(omap_control_exit);
>>>> +early_platform_init("early_omap_control", &omap_control_driver);
>>> early_platform_init is not needed as you are implementing the early reads in a different way.
>> Right.
>>>> +
>>>> +MODULE_DESCRIPTION("OMAP system control module driver");
>>>> +MODULE_LICENSE("GPL v2");
>>>> +MODULE_ALIAS("platform:omap-control-core");
>>>> +MODULE_AUTHOR("Texas Instruments Inc.");
>>>> diff --git a/include/linux/mfd/omap_control.h b/include/linux/mfd/omap_control.h
>>>> new file mode 100644
>>>> index 0000000..1795403
>>>> --- /dev/null
>>>> +++ b/include/linux/mfd/omap_control.h
>>>> @@ -0,0 +1,52 @@
>>>> +/*
>>>> + * OMAP system control module header file
>>>> + *
>>>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>>>> + * Contact:
>>>> + * J Keerthy <j-keerthy@ti.com>
>>>> + * Moiz Sonasath <m-sonasath@ti.com>
>>>> + * Abraham, Kishon Vijay <kishon@ti.com>
>>>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> + * modify it under the terms of the GNU General Public License
>>>> + * version 2 as published by the Free Software Foundation.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful, but
>>>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>>>> + * General Public License for more details.
>>>> + *
>>>> + */
>>>> +
>>>> +#ifndef __DRIVERS_OMAP_CONTROL_H
>>>> +#define __DRIVERS_OMAP_CONTROL_H
>>>> +
>>>> +#include <linux/err.h>
>>>> +
>>>> +/**
>>>> + * struct system control module - scm device structure
>>>> + * @dev: device pointer
>>>> + * @base: Base of the temp I/O
>>>> + * @reg_lock: protect omap_control structure
>>>> + * @use_count: track API users
>>>> + */
>>>> +struct omap_control {
>>>> + struct device *dev;
>>>> + void __iomem *base;
>>>> + /* protect this data structure and register access */
>>>> + spinlock_t reg_lock;
>>>> + int use_count;
>>> I suppose the reg_lock and the use_count are not needed in this design?
>> Right.
>>>> +};
>>>> +
>>>> +/* TODO: Add helpers for 16bit and byte access */
>>>> +#ifdef CONFIG_MFD_OMAP_CONTROL
>>>> +u32 omap_control_status_read(u16 offset);
>>>> +#else
>>>> +static inline u32 omap_control_status_read(u16 offset)
>>>> +{
>>>> + return 0;
>>>> +}
>>>> +#endif
>>>> +
>>>> +#endif /* __DRIVERS_OMAP_CONTROL_H */
>>>> --
>>>> 1.7.7.6
>>>>
>>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
^ permalink raw reply
* Re: Cpuidle drivers,Suspend : Fix suspend/resume hang with intel_idle driver
From: Rafael J. Wysocki @ 2012-06-28 9:53 UTC (permalink / raw)
To: preeti
Cc: Dave Hansen, Linux PM mailing list, linux-pm, linux-acpi,
Srivatsa.S.Bhat, Deepthi Dharwar
In-Reply-To: <4FEC20D2.2070501@linux.vnet.ibm.com>
On Thursday, June 28, 2012, preeti wrote:
>
> From: Preeti U Murthy <preeti@linux.vnet.ibm.com>
>
> Dave Hansen reported problems with suspend/resume when used
> with intel_idle driver.More such problems were noticed.
> https://bugs.launchpad.net/ubuntu/+source/linux/+bug/674075.
>
> The reason for this could not be suspected till he reported
> resume hang issue when used with acpi idle driver on his Lenovo-S10-3
> Atom netbook.
>
> The patch-[PM / ACPI: Fix suspend/resume regression caused by cpuidle
> cleanup],fixed this issue by ensuring that acpi idle drivers prevent
> cpus from going into deeper sleep states during suspend to prevent
> resume hang on certain bios.
> http://marc.info/?l=linux-pm&m=133958534231884&w=2
>
> Commit b04e7bdb984e3b7f62fb7f44146a529f88cc7639
> (ACPI: disable lower idle C-states across suspend/resume) throws
> light on the resume hang issue on certain specific bios.
>
> Also the following lines in drivers/idle/intel_idle.c suggest intel_idle
> drivers should also ensure cpus are prevented from entering idle states
> during suspend to avoid a resume hang.
>
> /*
> * Known limitations
> * [..]
> *
> * ACPI has a .suspend hack to turn off deep c-states during suspend
> * to avoid complications with the lapic timer workaround.
> * Have not seen issues with suspend, but may need same workaround here.
> *
> */
> This patch aims at having this fix in a place common to both the idle
> drivers.
>
> Suspend is enabled only if ACPI is active on x86.Thus the setting of
> acpi_idle_suspend during suspend is moved up to ACPI specific code with
> both acpi and intel idle drivers checking if it is valid to enter deeper
> idle states.The setting of acpi_idle_suspend is done via PM_SUSPEND_PREPARE
> notifiers to avoid race conditions between processors entering idle states
> and the ongoing process of suspend.
>
> The check on acpi_idle_suspend is included in the most appropriate header
> so as to be visible to both the idle drivers irrespective of the
> different configurations.Even if ACPI is disabled intel idle drivers can
> still carry out the acpi_idle_suspend check.
>
> Reported-by: Dave Hansen <dave@linux.vnet.ibm.com>
> Reviewed-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
> Reviewed-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
> Signed-off-by: Preeti U Murthy <preeti@linux.vnet.ibm.com>
> ---
> Dave, does this patch ensure suspend/resume works
> fine on your netbook if intel_idle driver is enabled?
>
> drivers/acpi/processor_idle.c | 46 +++++++++++++++++++----------------------
> drivers/acpi/sleep.c | 38 ++++++++++++++++++++++++++++++++++
> drivers/idle/intel_idle.c | 10 +++++++++
> include/linux/suspend.h | 24 +++++++++++++++++++++
> 4 files changed, 93 insertions(+), 25 deletions(-)
>
>
> diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
> index c2ffd84..3ab0963 100644
> --- a/drivers/acpi/processor_idle.c
> +++ b/drivers/acpi/processor_idle.c
> @@ -41,7 +41,7 @@
> #include <linux/clockchips.h>
> #include <linux/cpuidle.h>
> #include <linux/irqflags.h>
> -
> +#include <linux/suspend.h>
> /*
> * Include the apic definitions for x86 to have the APIC timer related defines
> * available also for UP (on SMP it gets magically included via linux/smp.h).
> @@ -221,10 +221,6 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
>
> #endif
>
> -/*
> - * Suspend / resume control
> - */
> -static int acpi_idle_suspend;
> static u32 saved_bm_rld;
>
> static void acpi_idle_bm_rld_save(void)
> @@ -243,21 +239,13 @@ static void acpi_idle_bm_rld_restore(void)
>
> int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
> {
> - if (acpi_idle_suspend == 1)
> - return 0;
> -
> acpi_idle_bm_rld_save();
> - acpi_idle_suspend = 1;
> return 0;
> }
So, this seems to be on top of the "PM / ACPI: Fix suspend/resume regression
caused by cpuidle" patch, right?
> int acpi_processor_resume(struct acpi_device * device)
> {
> - if (acpi_idle_suspend == 0)
> - return 0;
> -
> acpi_idle_bm_rld_restore();
> - acpi_idle_suspend = 0;
> return 0;
> }
>
> @@ -762,11 +750,13 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
> return -EINVAL;
>
> local_irq_disable();
> -
> - if (acpi_idle_suspend) {
> + /*
> + * Do not enter idle states if you are in suspend path
> + */
> + if (in_suspend_path()) {
This is more than ugly. Can't you simply use the acpi_idle_suspend _variable_
here?
Besides, why the name of the variable is acpi_idle_suspend, if it is used
by the Intel driver too?
> local_irq_enable();
> cpu_relax();
> - return -EINVAL;
> + return -EBUSY;
That change is made by the "PM / ACPI: Fix suspend/resume regression
caused by cpuidle" patch already.
> }
>
> lapic_timer_state_broadcast(pr, cx, 1);
> @@ -838,10 +828,13 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
>
> local_irq_disable();
>
> - if (acpi_idle_suspend) {
> + /*
> + * Do not enter idle states if you are in suspend path
> + */
> + if (in_suspend_path()) {
> local_irq_enable();
> cpu_relax();
> - return -EINVAL;
> + return -EBUSY;
> }
>
> if (cx->entry_method != ACPI_CSTATE_FFH) {
> @@ -922,12 +915,6 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
> if (unlikely(!pr))
> return -EINVAL;
>
> - if (acpi_idle_suspend) {
> - if (irqs_disabled())
> - local_irq_enable();
> - cpu_relax();
> - return -EINVAL;
> - }
The last version of the "PM / ACPI: Fix suspend/resume regression
caused by cpuidle" patch didn't contain this hunk.
>
> if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
> if (drv->safe_state_index >= 0) {
> @@ -935,13 +922,22 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
> drv, drv->safe_state_index);
> } else {
> local_irq_disable();
> - acpi_safe_halt();
> + if (!(in_suspend_path()))
> + acpi_safe_halt();
> local_irq_enable();
> return -EINVAL;
> }
> }
>
> local_irq_disable();
> + /*
> + * Do not enter idle states if you are in suspend path
> + */
> + if (in_suspend_path()) {
> + local_irq_enable();
> + cpu_relax();
> + return -EBUSY;
> + }
>
> if (cx->entry_method != ACPI_CSTATE_FFH) {
> current_thread_info()->status &= ~TS_POLLING;
> diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
> index 8856102..4ec77db 100644
> --- a/drivers/acpi/sleep.c
> +++ b/drivers/acpi/sleep.c
> @@ -28,6 +28,11 @@
> #include "internal.h"
> #include "sleep.h"
>
> +/*
> + * Suspend/Resume control
> + */
> +int acpi_idle_suspend;
> +
> u8 wake_sleep_flags = ACPI_NO_OPTIONAL_METHODS;
> static unsigned int gts, bfs;
> static int set_param_wake_flag(const char *val, struct kernel_param *kp)
> @@ -905,6 +910,36 @@ static void __init acpi_gts_bfs_check(void)
> }
> }
>
> +/**
> + * cpuidle_pm_callback - On some bios, resume hangs
> + * if idle states are entered during suspend.
> + *
> + * acpi_idle_suspend is used by the x86 idle drivers
> + * to decide whether to go into idle states or not.
> + */
> +static int
> +cpuidle_pm_callback(struct notifier_block *nb,
> + unsigned long action, void *ptr)
> +{
> + switch (action) {
> +
> + case PM_SUSPEND_PREPARE:
> + if (acpi_idle_suspend == 0)
> + acpi_idle_suspend = 1;
> + break;
> +
> + case PM_POST_SUSPEND:
> + if (acpi_idle_suspend == 1)
> + acpi_idle_suspend = 0;
> + break;
> +
> + default:
> + return NOTIFY_DONE;
> + }
> +
> + return NOTIFY_OK;
> +}
Why don't you put this notifier into cpuidle instead?
> +
> int __init acpi_sleep_init(void)
> {
> acpi_status status;
> @@ -932,6 +967,9 @@ int __init acpi_sleep_init(void)
>
> suspend_set_ops(old_suspend_ordering ?
> &acpi_suspend_ops_old : &acpi_suspend_ops);
> +
> + pm_notifier(cpuidle_pm_callback, 0);
> +
> #endif
>
> #ifdef CONFIG_HIBERNATION
> diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> index d0f59c3..a595207 100644
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -65,6 +65,7 @@
> #include <asm/cpu_device_id.h>
> #include <asm/mwait.h>
> #include <asm/msr.h>
> +#include <linux/suspend.h>
>
> #define INTEL_IDLE_VERSION "0.4"
> #define PREFIX "intel_idle: "
> @@ -255,6 +256,15 @@ static int intel_idle(struct cpuidle_device *dev,
> cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
>
> /*
> + * Do not enter idle states if you are in suspend path
> + */
> + if (in_suspend_path()) {
> + local_irq_enable();
> + cpu_relax();
> + return -EBUSY;
> + }
> +
> + /*
> * leave_mm() to avoid costly and often unnecessary wakeups
> * for flushing the user TLB's associated with the active mm.
> */
> diff --git a/include/linux/suspend.h b/include/linux/suspend.h
> index 0c808d7..eb96670 100644
> --- a/include/linux/suspend.h
> +++ b/include/linux/suspend.h
> @@ -38,6 +38,30 @@ typedef int __bitwise suspend_state_t;
> #define PM_SUSPEND_MEM ((__force suspend_state_t) 3)
> #define PM_SUSPEND_MAX ((__force suspend_state_t) 4)
>
> +extern int acpi_idle_suspend;
> +
> +/**
> + * in_suspend_path - X86 idle drivers make a call
> + * to this function before entering idle states.
> + *
> + * Entering idle states is prevented if it is in suspend
> + * path.
> + */
> +#ifdef CONFIG_ACPI
Why #ifdef CONFIG_ACPI?
> +static inline int in_suspend_path(void)
> +{
> + if (acpi_idle_suspend == 1)
> + return 1;
> + else
> + return 0;
> +}
> +#else
> +static inline int in_suspend_path(void)
> +{
> + return 0;
> +}
> +#endif
> +
> enum suspend_stat_step {
> SUSPEND_FREEZE = 1,
> SUSPEND_PREPARE,
Thanks,
Rafael
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Valentin, Eduardo @ 2012-06-28 9:49 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap
In-Reply-To: <4FEC25CA.10105@dev.rtsoft.ru>
Hello,
On Thu, Jun 28, 2012 at 12:37 PM, Konstantin Baydarov
<kbaidarov@dev.rtsoft.ru> wrote:
> Hi.
>
> On 06/28/2012 08:50 AM, Eduardo Valentin wrote:
>> Hello,
>>
>> On Wed, Jun 27, 2012 at 10:04:54PM +0400, Konstantin Baydarov wrote:
>>> This patch introduces a MFD core device driver for OMAP system control module.
>>>
>>> The control module allows software control of various static modes supported by the device.
>>> It is composed of two control submodules: general control module and device (padconfiguration) control module.
>>>
>>> Changes since previous version:
>>> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
>>> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
>>> Probably, no configuration option is required!
>>> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
>>> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
>>> module device.
>>> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
>>> - omap-control-core: added omap_control_status_read that is used early in omap_type
>>>
>>> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
>>> Signed-off-by: J Keerthy <j-keerthy@ti.com>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
>>> ---
>>> .../devicetree/bindings/mfd/omap_control.txt | 44 +++++++
>>> arch/arm/mach-omap2/Kconfig | 1 +
>>> arch/arm/plat-omap/Kconfig | 4 +
>>> drivers/mfd/Kconfig | 9 ++
>>> drivers/mfd/Makefile | 1 +
>>> drivers/mfd/omap-control-core.c | 131 ++++++++++++++++++++
>>> include/linux/mfd/omap_control.h | 52 ++++++++
>>> 7 files changed, 242 insertions(+), 0 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/mfd/omap_control.txt
>>> create mode 100644 drivers/mfd/omap-control-core.c
>>> create mode 100644 include/linux/mfd/omap_control.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/omap_control.txt b/Documentation/devicetree/bindings/mfd/omap_control.txt
>>> new file mode 100644
>>> index 0000000..46d5e7e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mfd/omap_control.txt
>>> @@ -0,0 +1,44 @@
>>> +* Texas Instrument OMAP System Control Module (SCM) bindings
>>> +
>>> +The control module allows software control of various static modes supported by
>>> +the device. The control module controls the settings of various device modules
>>> +through register configuration and internal signals. It also controls the pad
>>> +configuration, pin functional multiplexing, and the routing of internal signals
>>> +(such as PRCM signals or DMA requests) to output pins configured for hardware
>>> +observability.
>>> +
>>> +Required properties:
>>> +- compatible : Should be:
>>> + - "ti,omap3-control" for OMAP3 support
>>> + - "ti,omap4-control" for OMAP4 support
>>> + - "ti,omap5-control" for OMAP5 support
>>> +
>>> +OMAP specific properties:
>>> +- ti,hwmods: Name of the hwmod associated to the control module:
>>> + Should be "ctrl_module_core";
>>> +
>>> +Sub-nodes:
>>> +- bandgap : contains the bandgap node
>>> +
>>> + The bindings details of individual bandgap device can be found in:
>>> + Documentation/devicetree/bindings/thermal/omap_bandgap.txt
>>> +
>>> +- usb : contains the usb phy pin control node
>>> +
>>> + The only required property for this child is:
>>> + - compatible = "ti,omap4-control-usb";
>>> +
>>> +Examples:
>>> +
>>> +ctrl_module_core: ctrl_module_core@4a002000 {
>>> + compatible = "ti,omap4-control";
>>> + ti,hwmods = "ctrl_module_core";
>>> + bandgap {
>>> + compatible = "ti,omap4460-bandgap";
>> You need to update the documentation if change the DT structure.
> Ok.
>>
>>> + interrupts = <0 126 4>; /* talert */
>>> + ti,tshut-gpio = <86>; /* tshut */
>>> + };
>>> + usb {
>>> + compatible = "ti,omap4-usb-phy";
>>> + };
>>> +};
>>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>>> index 4cf5142..c2ef07c 100644
>>> --- a/arch/arm/mach-omap2/Kconfig
>>> +++ b/arch/arm/mach-omap2/Kconfig
>>> @@ -52,6 +52,7 @@ config ARCH_OMAP4
>>> select PL310_ERRATA_727915
>>> select ARM_ERRATA_720789
>>> select ARCH_HAS_OPP
>>> + select ARCH_HAS_CONTROL_MODULE
>>> select PM_OPP if PM
>>> select USB_ARCH_HAS_EHCI if USB_SUPPORT
>>> select ARM_CPU_SUSPEND if PM
>>> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
>>> index ad95c7a..0f9b575 100644
>>> --- a/arch/arm/plat-omap/Kconfig
>>> +++ b/arch/arm/plat-omap/Kconfig
>>> @@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
>>> config ARCH_OMAP_OTG
>>> bool
>>>
>>> +config ARCH_HAS_CONTROL_MODULE
>>> + bool
>>> + select MFD_OMAP_CONTROL
>>> +
>> OK now I got what you meant in patch 0. Fine for me.
>>
>>> choice
>>> prompt "OMAP System Type"
>>> default ARCH_OMAP2PLUS
>>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>>> index e129c82..d0c5456 100644
>>> --- a/drivers/mfd/Kconfig
>>> +++ b/drivers/mfd/Kconfig
>>> @@ -822,6 +822,15 @@ config MFD_WL1273_CORE
>>> driver connects the radio-wl1273 V4L2 module and the wl1273
>>> audio codec.
>>>
>>> +config MFD_OMAP_CONTROL
>>> + bool "Texas Instruments OMAP System control module"
>>> + depends on ARCH_HAS_CONTROL_MODULE
>>> + help
>>> + This is the core driver for system control module. This driver
>>> + is responsible for creating the control module mfd child,
>>> + like USB-pin control, pin muxing, MMC-pbias and DDR IO dynamic
>>> + change for off mode.
>>> +
>>> config MFD_OMAP_USB_HOST
>>> bool "Support OMAP USBHS core driver"
>>> depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
>>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>>> index 75f6ed6..b037443 100644
>>> --- a/drivers/mfd/Makefile
>>> +++ b/drivers/mfd/Makefile
>>> @@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
>>> obj-$(CONFIG_MFD_VX855) += vx855.o
>>> obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
>>> obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
>>> +obj-$(CONFIG_MFD_OMAP_CONTROL) += omap-control-core.o
>>> obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
>>> obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
>>> obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
>>> diff --git a/drivers/mfd/omap-control-core.c b/drivers/mfd/omap-control-core.c
>>> new file mode 100644
>>> index 0000000..724c51b
>>> --- /dev/null
>>> +++ b/drivers/mfd/omap-control-core.c
>>> @@ -0,0 +1,131 @@
>>> +/*
>>> + * OMAP system control module driver file
>>> + *
>>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>>> + * Contacts:
>>> + * Based on original code written by:
>>> + * J Keerthy <j-keerthy@ti.com>
>>> + * Moiz Sonasath <m-sonasath@ti.com>
>>> + * MFD clean up and re-factoring:
>>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License
>>> + * version 2 as published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful, but
>>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>>> + * General Public License for more details.
>>> + *
>>> + */
>>> +
>>> +#include <linux/module.h>
>>> +#include <linux/export.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/io.h>
>>> +#include <linux/err.h>
>>> +#include <linux/of_platform.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/mfd/core.h>
>>> +#include <linux/mfd/omap_control.h>
>>> +
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +
>>> +void __iomem *omap_control_base;
>>> +
>>> +u32 omap_control_status_read(u16 offset)
>>> +{
>>> + return __raw_readl(omap_control_base + (offset));
>>> +}
>>> +
>>> +static const struct of_device_id of_omap_control_match[] = {
>>> + { .compatible = "ti,omap3-control", },
>>> + { .compatible = "ti,omap4-control", },
>>> + { .compatible = "ti,omap5-control", },
>>> + { },
>>> +};
>>> +
>>> +static int __devinit omap_control_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + struct device_node *np = dev->of_node;
>>> +
>>> + /*
>>> + * Build child defvices of ctrl_module_core
>>> + */
>>> + return of_platform_populate(np, of_omap_control_match, NULL, dev);
>>> +}
>>> +
>>> +
>>> +static struct platform_driver omap_control_driver = {
>>> + .probe = omap_control_probe,
>>> + .driver = {
>>> + .name = "omap-control-core",
>>> + .owner = THIS_MODULE,
>>> + .of_match_table = of_omap_control_match,
>>> + },
>>> +};
>>> +
>>> +int __init omap_control_of_init(struct device_node *node,
>>> + struct device_node *parent)
>>> +{
>>> + struct resource res;
>>> +
>>> + if (WARN_ON(!node))
>>> + return -ENODEV;
>>> +
>>> + if (of_address_to_resource(node, 0, &res)) {
>>> + WARN(1, "unable to get intc registers\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + return 0;
>>> +}
>> The above function is used nowhere.
> Agree.
>>
>>> +
>>> +void __init of_omap_control_init(const struct of_device_id *matches)
>>> +{
>>> + struct device_node *np;
>>> + struct property *pp = 0;
>>> + unsigned long phys_base = 0;
>>> + size_t mapsize = 0;
>>> +
>>> + for_each_matching_node(np, matches) {
>>> +
>>> + pp = of_find_property(np, "reg", NULL);
>>> + if(pp) {
>>> + phys_base = (unsigned long)be32_to_cpup(pp->value);
>>> + mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
>>> + omap_control_base = ioremap(phys_base, mapsize);
>> How the reservation is going to work?
> This can be done following way:
> - omap-control-core.c ioremaps and reserves SCM IOMEM window
> - omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
> IIUC, this way was suggested by Tony.
how better is this way compared to having the access functions in the
core? This way we just replicate the access functions in every
children.
I believe the suggestion was to have the ioremap and request done in
chunks. So that children dont step into each other ioarea. But then
again that can be a bit painful as the children registers are not
contiguous.
>
>>
>>> + }
>>> + }
>>> +}
>>> +
>>> +static int __init
>>> +omap_control_early_initcall(void)
>>> +{
>>> + of_omap_control_init(of_omap_control_match);
>>> +
>>> + return 0;
>>> +}
>>> +early_initcall(omap_control_early_initcall);
>>> +
>>> +static int __init omap_control_init(void)
>>> +{
>>> + return platform_driver_register(&omap_control_driver);
>>> +}
>>> +postcore_initcall_sync(omap_control_init);
>>> +
>>> +static void __exit omap_control_exit(void)
>>> +{
>>> + platform_driver_unregister(&omap_control_driver);
>>> +}
>>> +module_exit(omap_control_exit);
>>> +early_platform_init("early_omap_control", &omap_control_driver);
>> early_platform_init is not needed as you are implementing the early reads in a different way.
> Right.
>>
>>> +
>>> +MODULE_DESCRIPTION("OMAP system control module driver");
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_ALIAS("platform:omap-control-core");
>>> +MODULE_AUTHOR("Texas Instruments Inc.");
>>> diff --git a/include/linux/mfd/omap_control.h b/include/linux/mfd/omap_control.h
>>> new file mode 100644
>>> index 0000000..1795403
>>> --- /dev/null
>>> +++ b/include/linux/mfd/omap_control.h
>>> @@ -0,0 +1,52 @@
>>> +/*
>>> + * OMAP system control module header file
>>> + *
>>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>>> + * Contact:
>>> + * J Keerthy <j-keerthy@ti.com>
>>> + * Moiz Sonasath <m-sonasath@ti.com>
>>> + * Abraham, Kishon Vijay <kishon@ti.com>
>>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License
>>> + * version 2 as published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful, but
>>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>>> + * General Public License for more details.
>>> + *
>>> + */
>>> +
>>> +#ifndef __DRIVERS_OMAP_CONTROL_H
>>> +#define __DRIVERS_OMAP_CONTROL_H
>>> +
>>> +#include <linux/err.h>
>>> +
>>> +/**
>>> + * struct system control module - scm device structure
>>> + * @dev: device pointer
>>> + * @base: Base of the temp I/O
>>> + * @reg_lock: protect omap_control structure
>>> + * @use_count: track API users
>>> + */
>>> +struct omap_control {
>>> + struct device *dev;
>>> + void __iomem *base;
>>> + /* protect this data structure and register access */
>>> + spinlock_t reg_lock;
>>> + int use_count;
>> I suppose the reg_lock and the use_count are not needed in this design?
> Right.
>>
>>> +};
>>> +
>>> +/* TODO: Add helpers for 16bit and byte access */
>>> +#ifdef CONFIG_MFD_OMAP_CONTROL
>>> +u32 omap_control_status_read(u16 offset);
>>> +#else
>>> +static inline u32 omap_control_status_read(u16 offset)
>>> +{
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +#endif /* __DRIVERS_OMAP_CONTROL_H */
>>> --
>>> 1.7.7.6
>>>
>>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Eduardo Valentin
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 1/7] ARM: OMAP4: Remove un-used control module headers and defines.
From: Valentin, Eduardo @ 2012-06-28 9:46 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEC2306.1030105@dev.rtsoft.ru>
Hello,
On Thu, Jun 28, 2012 at 12:25 PM, Konstantin Baydarov
<kbaidarov@dev.rtsoft.ru> wrote:
> Hi, Eduardo.
>
> On 06/28/2012 08:45 AM, Eduardo Valentin wrote:
>> Why the authorship of these patches is changing?
> Did I change Signed-off-by field? Could you clarify.
Signed offs are there. But the From field has switched from Santosh to
Konstantin. Do you use git am to apply patches from ml?
>>
>> For instance this patch, from Santosh, I believe it is the same...
>>
>> On Wed, Jun 27, 2012 at 10:04:47PM +0400, Konstantin Baydarov wrote:
>>> Most of the OMAP4 control module register defines are not used and
>>> can be removed. Keep only needed defines and move them to common
>>> control module header just like other OMAP versions.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
>>> ---
>>> arch/arm/mach-omap2/control.h | 45 +-
>>> .../include/mach/ctrl_module_core_44xx.h | 391 ------
>>> .../include/mach/ctrl_module_pad_core_44xx.h | 1409 --------------------
>>> .../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ----
>>> .../include/mach/ctrl_module_wkup_44xx.h | 92 --
>>> 5 files changed, 40 insertions(+), 2133 deletions(-)
>>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>>>
>>> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
>>> index a406fd0..dad2903 100644
>>> --- a/arch/arm/mach-omap2/control.h
>>> +++ b/arch/arm/mach-omap2/control.h
>>> @@ -16,11 +16,6 @@
>>> #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
>>> #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
>>>
>>> -#include <mach/ctrl_module_core_44xx.h>
>>> -#include <mach/ctrl_module_wkup_44xx.h>
>>> -#include <mach/ctrl_module_pad_core_44xx.h>
>>> -#include <mach/ctrl_module_pad_wkup_44xx.h>
>>> -
>>> #ifndef __ASSEMBLY__
>>> #define OMAP242X_CTRL_REGADDR(reg) \
>>> OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
>>> @@ -183,6 +178,43 @@
>>> #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
>>> #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
>>>
>>> +/* OMAP4 IDCODE CONTROL */
>>> +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
>>> +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
>>> +
>>> +/* CONTROL_I2C_1 */
>>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
>>> +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
>>> +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
>>> +
>>> +/* DSI CONTROL_DSIPHY */
>>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
>>> +#define OMAP4_DSI2_LANEENABLE_SHIFT 29
>>> +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
>>> +#define OMAP4_DSI1_LANEENABLE_SHIFT 24
>>> +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
>>> +#define OMAP4_DSI1_PIPD_SHIFT 19
>>> +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
>>> +#define OMAP4_DSI2_PIPD_SHIFT 14
>>> +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
>>> +
>>> +/* CONTROL_PBIASLITE */
>>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
>>> +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
>>> +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
>>> +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
>>> +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
>>> +
>>> +/* CONTROL_MMC1 */
>>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
>>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
>>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
>>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
>>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
>>> +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
>>> +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
>>> +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
>>> +
>>> /* OMAP44xx control efuse offsets */
>>> #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
>>> #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
>>> @@ -195,6 +227,9 @@
>>> #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
>>> #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
>>>
>>> +/* OMAP44xx control McBSP padconf */
>>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
>>> +
>>> /* AM35XX only CONTROL_GENERAL register offsets */
>>> #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
>>> #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
>>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>>> deleted file mode 100644
>>> index 2f7ac70..0000000
>>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>>> +++ /dev/null
>>> @@ -1,391 +0,0 @@
>>> -/*
>>> - * OMAP44xx CTRL_MODULE_CORE registers and bitfields
>>> - *
>>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>>> - *
>>> - * Benoit Cousson (b-cousson@ti.com)
>>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>>> - *
>>> - * This file is automatically generated from the OMAP hardware databases.
>>> - * We respectfully ask that any modifications to this file be coordinated
>>> - * with the public linux-omap@vger.kernel.org mailing list and the
>>> - * authors above to ensure that the autogeneration scripts are kept
>>> - * up-to-date with the file contents.
>>> - *
>>> - * This program is free software; you can redistribute it and/or modify
>>> - * it under the terms of the GNU General Public License version 2 as
>>> - * published by the Free Software Foundation.
>>> - */
>>> -
>>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
>>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
>>> -
>>> -
>>> -/* Base address */
>>> -#define OMAP4_CTRL_MODULE_CORE 0x4a002000
>>> -
>>> -/* Registers offset */
>>> -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
>>> -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
>>> -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
>>> -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
>>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
>>> -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
>>> -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
>>> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
>>> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
>>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
>>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
>>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
>>> -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
>>> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
>>> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
>>> -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
>>> -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
>>> -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
>>> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
>>> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
>>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
>>> -
>>> -/* Registers shifts and masks */
>>> -
>>> -/* IP_REVISION */
>>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>>> -
>>> -/* IP_HWINFO */
>>> -#define OMAP4_IP_HWINFO_SHIFT 0
>>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>>> -
>>> -/* IP_SYSCONFIG */
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>>> -
>>> -/* STD_FUSE_DIE_ID_0 */
>>> -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
>>> -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
>>> -
>>> -/* ID_CODE */
>>> -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
>>> -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_DIE_ID_1 */
>>> -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
>>> -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_DIE_ID_2 */
>>> -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
>>> -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_DIE_ID_3 */
>>> -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
>>> -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_PROD_ID_0 */
>>> -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
>>> -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_PROD_ID_1 */
>>> -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
>>> -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_USB_CONF */
>>> -#define OMAP4_USB_PROD_ID_SHIFT 16
>>> -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
>>> -#define OMAP4_USB_VENDOR_ID_SHIFT 0
>>> -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
>>> -
>>> -/* STD_FUSE_OPP_VDD_WKUP */
>>> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
>>> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_OPP_BGAP */
>>> -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
>>> -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_OPP_DPLL_0 */
>>> -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
>>> -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
>>> -
>>> -/* STD_FUSE_OPP_DPLL_1 */
>>> -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
>>> -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
>>> -
>>> -/* STATUS */
>>> -#define OMAP4_ATTILA_CONF_SHIFT 11
>>> -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
>>> -#define OMAP4_DEVICE_TYPE_SHIFT 8
>>> -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
>>> -#define OMAP4_SYS_BOOT_SHIFT 0
>>> -#define OMAP4_SYS_BOOT_MASK (0xff << 0)
>>> -
>>> -/* DEV_CONF */
>>> -#define OMAP4_DEV_CONF_SHIFT 1
>>> -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
>>> -#define OMAP4_USBPHY_PD_SHIFT 0
>>> -#define OMAP4_USBPHY_PD_MASK (1 << 0)
>>> -
>>> -/* LDOVBB_IVA_VOLTAGE_CTRL */
>>> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
>>> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
>>> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
>>> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
>>> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
>>> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
>>> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
>>> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
>>> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
>>> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
>>> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
>>> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
>>> -
>>> -/* LDOVBB_MPU_VOLTAGE_CTRL */
>>> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
>>> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
>>> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
>>> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
>>> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
>>> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
>>> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
>>> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
>>> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
>>> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
>>> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
>>> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
>>> -
>>> -/* LDOSRAM_IVA_VOLTAGE_CTRL */
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
>>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
>>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>>> -
>>> -/* LDOSRAM_MPU_VOLTAGE_CTRL */
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
>>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
>>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>>> -
>>> -/* LDOSRAM_CORE_VOLTAGE_CTRL */
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
>>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
>>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>>> -
>>> -/* TEMP_SENSOR */
>>> -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
>>> -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
>>> -#define OMAP4_BGAP_TSHUT_SHIFT 11
>>> -#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
>>> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
>>> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
>>> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
>>> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
>>> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
>>> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
>>> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
>>> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
>>> -
>>> -/* DPLL_NWELL_TRIM_0 */
>>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
>>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
>>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
>>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
>>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
>>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
>>> -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
>>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
>>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
>>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
>>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
>>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
>>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
>>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
>>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
>>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
>>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
>>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
>>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
>>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
>>> -
>>> -/* DPLL_NWELL_TRIM_1 */
>>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
>>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
>>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
>>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
>>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
>>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
>>> -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
>>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
>>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
>>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
>>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
>>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
>>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
>>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
>>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
>>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
>>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
>>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
>>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
>>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
>>> -
>>> -/* USBOTGHS_CONTROL */
>>> -#define OMAP4_DISCHRGVBUS_SHIFT 8
>>> -#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
>>> -#define OMAP4_CHRGVBUS_SHIFT 7
>>> -#define OMAP4_CHRGVBUS_MASK (1 << 7)
>>> -#define OMAP4_DRVVBUS_SHIFT 6
>>> -#define OMAP4_DRVVBUS_MASK (1 << 6)
>>> -#define OMAP4_IDPULLUP_SHIFT 5
>>> -#define OMAP4_IDPULLUP_MASK (1 << 5)
>>> -#define OMAP4_IDDIG_SHIFT 4
>>> -#define OMAP4_IDDIG_MASK (1 << 4)
>>> -#define OMAP4_SESSEND_SHIFT 3
>>> -#define OMAP4_SESSEND_MASK (1 << 3)
>>> -#define OMAP4_VBUSVALID_SHIFT 2
>>> -#define OMAP4_VBUSVALID_MASK (1 << 2)
>>> -#define OMAP4_BVALID_SHIFT 1
>>> -#define OMAP4_BVALID_MASK (1 << 1)
>>> -#define OMAP4_AVALID_SHIFT 0
>>> -#define OMAP4_AVALID_MASK (1 << 0)
>>> -
>>> -/* DSS_CONTROL */
>>> -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
>>> -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
>>> -
>>> -/* HWOBS_CONTROL */
>>> -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
>>> -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
>>> -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
>>> -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
>>> -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
>>> -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
>>> -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
>>> -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
>>> -
>>> -/* DEBOBS_FINAL_MUX_SEL */
>>> -#define OMAP4_SELECT_SHIFT 0
>>> -#define OMAP4_SELECT_MASK (0xffffffff << 0)
>>> -
>>> -/* DEBOBS_MMR_MPU */
>>> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
>>> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
>>> -
>>> -/* CONF_SDMA_REQ_SEL0 */
>>> -#define OMAP4_MULT_SHIFT 0
>>> -#define OMAP4_MULT_MASK (0x7f << 0)
>>> -
>>> -/* CONF_CLK_SEL0 */
>>> -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
>>> -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
>>> -
>>> -/* CONF_CLK_SEL1 */
>>> -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
>>> -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
>>> -
>>> -/* CONF_CLK_SEL2 */
>>> -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
>>> -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
>>> -
>>> -/* CONF_DPLL_FREQLOCK_SEL */
>>> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
>>> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
>>> -
>>> -/* CONF_DPLL_TINITZ_SEL */
>>> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
>>> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
>>> -
>>> -/* CONF_DPLL_PHASELOCK_SEL */
>>> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
>>> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
>>> -
>>> -/* CONF_DEBUG_SEL_TST_0 */
>>> -#define OMAP4_MODE_SHIFT 0
>>> -#define OMAP4_MODE_MASK (0xf << 0)
>>> -
>>> -#endif
>>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>>> deleted file mode 100644
>>> index c88420d..0000000
>>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>>> +++ /dev/null
>>> @@ -1,1409 +0,0 @@
>>> -/*
>>> - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
>>> - *
>>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>>> - *
>>> - * Benoit Cousson (b-cousson@ti.com)
>>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>>> - *
>>> - * This file is automatically generated from the OMAP hardware databases.
>>> - * We respectfully ask that any modifications to this file be coordinated
>>> - * with the public linux-omap@vger.kernel.org mailing list and the
>>> - * authors above to ensure that the autogeneration scripts are kept
>>> - * up-to-date with the file contents.
>>> - *
>>> - * This program is free software; you can redistribute it and/or modify
>>> - * it under the terms of the GNU General Public License version 2 as
>>> - * published by the Free Software Foundation.
>>> - */
>>> -
>>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
>>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
>>> -
>>> -
>>> -/* Base address */
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
>>> -
>>> -/* Registers offset */
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
>>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
>>> -
>>> -/* Registers shifts and masks */
>>> -
>>> -/* IP_REVISION */
>>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>>> -
>>> -/* IP_HWINFO */
>>> -#define OMAP4_IP_HWINFO_SHIFT 0
>>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>>> -
>>> -/* IP_SYSCONFIG */
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_0 */
>>> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_1 */
>>> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_2 */
>>> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_3 */
>>> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_4 */
>>> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_5 */
>>> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
>>> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>>> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
>>> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>>> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
>>> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>>> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
>>> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>>> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
>>> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>>> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
>>> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>>> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
>>> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>>> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_6 */
>>> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* CONTROL_PADCONF_GLOBAL */
>>> -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
>>> -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
>>> -
>>> -/* CONTROL_PADCONF_MODE */
>>> -#define OMAP4_VDDS_DV_BANK0_SHIFT 31
>>> -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
>>> -#define OMAP4_VDDS_DV_BANK1_SHIFT 30
>>> -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
>>> -#define OMAP4_VDDS_DV_BANK3_SHIFT 29
>>> -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
>>> -#define OMAP4_VDDS_DV_BANK4_SHIFT 28
>>> -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
>>> -#define OMAP4_VDDS_DV_BANK5_SHIFT 27
>>> -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
>>> -#define OMAP4_VDDS_DV_BANK6_SHIFT 26
>>> -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
>>> -#define OMAP4_VDDS_DV_C2C_SHIFT 25
>>> -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
>>> -#define OMAP4_VDDS_DV_CAM_SHIFT 24
>>> -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
>>> -#define OMAP4_VDDS_DV_GPMC_SHIFT 23
>>> -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
>>> -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
>>> -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
>>> -
>>> -/* CONTROL_SMART1IO_PADCONF_0 */
>>> -#define OMAP4_ABE_DR0_SC_SHIFT 30
>>> -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
>>> -#define OMAP4_CAM_DR0_SC_SHIFT 28
>>> -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
>>> -#define OMAP4_FREF_DR2_SC_SHIFT 26
>>> -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
>>> -#define OMAP4_FREF_DR3_SC_SHIFT 24
>>> -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
>>> -#define OMAP4_GPIO_DR8_SC_SHIFT 22
>>> -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
>>> -#define OMAP4_GPIO_DR9_SC_SHIFT 20
>>> -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
>>> -#define OMAP4_GPMC_DR2_SC_SHIFT 18
>>> -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
>>> -#define OMAP4_GPMC_DR3_SC_SHIFT 16
>>> -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
>>> -#define OMAP4_GPMC_DR6_SC_SHIFT 14
>>> -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
>>> -#define OMAP4_HDMI_DR0_SC_SHIFT 12
>>> -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
>>> -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
>>> -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
>>> -#define OMAP4_UART1_DR0_SC_SHIFT 8
>>> -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
>>> -#define OMAP4_UART3_DR0_SC_SHIFT 6
>>> -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
>>> -#define OMAP4_UART3_DR1_SC_SHIFT 4
>>> -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
>>> -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
>>> -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
>>> -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
>>> -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
>>> -
>>> -/* CONTROL_SMART1IO_PADCONF_1 */
>>> -#define OMAP4_ABE_DR0_LB_SHIFT 30
>>> -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
>>> -#define OMAP4_CAM_DR0_LB_SHIFT 28
>>> -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
>>> -#define OMAP4_FREF_DR2_LB_SHIFT 26
>>> -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
>>> -#define OMAP4_FREF_DR3_LB_SHIFT 24
>>> -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
>>> -#define OMAP4_GPIO_DR8_LB_SHIFT 22
>>> -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
>>> -#define OMAP4_GPIO_DR9_LB_SHIFT 20
>>> -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
>>> -#define OMAP4_GPMC_DR2_LB_SHIFT 18
>>> -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
>>> -#define OMAP4_GPMC_DR3_LB_SHIFT 16
>>> -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
>>> -#define OMAP4_GPMC_DR6_LB_SHIFT 14
>>> -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
>>> -#define OMAP4_HDMI_DR0_LB_SHIFT 12
>>> -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
>>> -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
>>> -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
>>> -#define OMAP4_UART1_DR0_LB_SHIFT 8
>>> -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
>>> -#define OMAP4_UART3_DR0_LB_SHIFT 6
>>> -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
>>> -#define OMAP4_UART3_DR1_LB_SHIFT 4
>>> -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
>>> -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
>>> -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
>>> -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
>>> -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
>>> -
>>> -/* CONTROL_SMART2IO_PADCONF_0 */
>>> -#define OMAP4_C2C_DR0_LB_SHIFT 31
>>> -#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
>>> -#define OMAP4_DPM_DR1_LB_SHIFT 30
>>> -#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
>>> -#define OMAP4_DPM_DR2_LB_SHIFT 29
>>> -#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
>>> -#define OMAP4_DPM_DR3_LB_SHIFT 28
>>> -#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
>>> -#define OMAP4_GPIO_DR0_LB_SHIFT 27
>>> -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
>>> -#define OMAP4_GPIO_DR1_LB_SHIFT 26
>>> -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
>>> -#define OMAP4_GPIO_DR10_LB_SHIFT 25
>>> -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
>>> -#define OMAP4_GPIO_DR2_LB_SHIFT 24
>>> -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
>>> -#define OMAP4_GPMC_DR0_LB_SHIFT 23
>>> -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
>>> -#define OMAP4_GPMC_DR1_LB_SHIFT 22
>>> -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
>>> -#define OMAP4_GPMC_DR4_LB_SHIFT 21
>>> -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
>>> -#define OMAP4_GPMC_DR5_LB_SHIFT 20
>>> -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
>>> -#define OMAP4_GPMC_DR7_LB_SHIFT 19
>>> -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
>>> -#define OMAP4_HSI2_DR0_LB_SHIFT 18
>>> -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
>>> -#define OMAP4_HSI2_DR1_LB_SHIFT 17
>>> -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
>>> -#define OMAP4_HSI2_DR2_LB_SHIFT 16
>>> -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
>>> -#define OMAP4_KPD_DR0_LB_SHIFT 15
>>> -#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
>>> -#define OMAP4_KPD_DR1_LB_SHIFT 14
>>> -#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
>>> -#define OMAP4_PDM_DR0_LB_SHIFT 13
>>> -#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
>>> -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
>>> -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
>>> -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
>>> -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
>>> -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
>>> -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
>>> -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
>>> -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
>>> -#define OMAP4_SPI3_DR0_LB_SHIFT 8
>>> -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
>>> -#define OMAP4_SPI3_DR1_LB_SHIFT 7
>>> -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
>>> -#define OMAP4_UART3_DR2_LB_SHIFT 6
>>> -#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
>>> -#define OMAP4_UART3_DR3_LB_SHIFT 5
>>> -#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
>>> -#define OMAP4_UART3_DR4_LB_SHIFT 4
>>> -#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
>>> -#define OMAP4_UART3_DR5_LB_SHIFT 3
>>> -#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
>>> -#define OMAP4_USBA0_DR1_LB_SHIFT 2
>>> -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
>>> -#define OMAP4_USBA_DR2_LB_SHIFT 1
>>> -#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
>>> -
>>> -/* CONTROL_SMART2IO_PADCONF_1 */
>>> -#define OMAP4_USBB1_DR0_LB_SHIFT 31
>>> -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
>>> -#define OMAP4_USBB2_DR0_LB_SHIFT 30
>>> -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
>>> -#define OMAP4_USBA0_DR0_LB_SHIFT 29
>>> -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
>>> -
>>> -/* CONTROL_SMART3IO_PADCONF_0 */
>>> -#define OMAP4_DMIC_DR0_MB_SHIFT 30
>>> -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
>>> -#define OMAP4_GPIO_DR3_MB_SHIFT 28
>>> -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
>>> -#define OMAP4_GPIO_DR4_MB_SHIFT 26
>>> -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
>>> -#define OMAP4_GPIO_DR5_MB_SHIFT 24
>>> -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
>>> -#define OMAP4_GPIO_DR6_MB_SHIFT 22
>>> -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
>>> -#define OMAP4_HSI_DR1_MB_SHIFT 20
>>> -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
>>> -#define OMAP4_HSI_DR2_MB_SHIFT 18
>>> -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
>>> -#define OMAP4_HSI_DR3_MB_SHIFT 16
>>> -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
>>> -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
>>> -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
>>> -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
>>> -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
>>> -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
>>> -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
>>> -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
>>> -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
>>> -#define OMAP4_SPI2_DR0_MB_SHIFT 0
>>> -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
>>> -
>>> -/* CONTROL_SMART3IO_PADCONF_1 */
>>> -#define OMAP4_SPI2_DR1_MB_SHIFT 30
>>> -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
>>> -#define OMAP4_SPI2_DR2_MB_SHIFT 28
>>> -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
>>> -#define OMAP4_UART2_DR0_MB_SHIFT 26
>>> -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
>>> -#define OMAP4_UART2_DR1_MB_SHIFT 24
>>> -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
>>> -#define OMAP4_UART4_DR0_MB_SHIFT 22
>>> -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
>>> -#define OMAP4_HSI_DR0_MB_SHIFT 20
>>> -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
>>> -
>>> -/* CONTROL_SMART3IO_PADCONF_2 */
>>> -#define OMAP4_DMIC_DR0_LB_SHIFT 31
>>> -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
>>> -#define OMAP4_GPIO_DR3_LB_SHIFT 30
>>> -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
>>> -#define OMAP4_GPIO_DR4_LB_SHIFT 29
>>> -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
>>> -#define OMAP4_GPIO_DR5_LB_SHIFT 28
>>> -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
>>> -#define OMAP4_GPIO_DR6_LB_SHIFT 27
>>> -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
>>> -#define OMAP4_HSI_DR1_LB_SHIFT 26
>>> -#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
>>> -#define OMAP4_HSI_DR2_LB_SHIFT 25
>>> -#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
>>> -#define OMAP4_HSI_DR3_LB_SHIFT 24
>>> -#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
>>> -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
>>> -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
>>> -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
>>> -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
>>> -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
>>> -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
>>> -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
>>> -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
>>> -#define OMAP4_SPI2_DR0_LB_SHIFT 16
>>> -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
>>> -#define OMAP4_SPI2_DR1_LB_SHIFT 15
>>> -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
>>> -#define OMAP4_SPI2_DR2_LB_SHIFT 14
>>> -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
>>> -#define OMAP4_UART2_DR0_LB_SHIFT 13
>>> -#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
>>> -#define OMAP4_UART2_DR1_LB_SHIFT 12
>>> -#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
>>> -#define OMAP4_UART4_DR0_LB_SHIFT 11
>>> -#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
>>> -#define OMAP4_HSI_DR0_LB_SHIFT 10
>>> -#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
>>> -
>>> -/* CONTROL_USBB_HSIC */
>>> -#define OMAP4_USBB2_DR1_SR_SHIFT 30
>>> -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
>>> -#define OMAP4_USBB2_DR1_I_SHIFT 27
>>> -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
>>> -#define OMAP4_USBB1_DR1_SR_SHIFT 25
>>> -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
>>> -#define OMAP4_USBB1_DR1_I_SHIFT 22
>>> -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
>>> -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
>>> -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
>>> -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
>>> -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
>>> -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
>>> -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
>>> -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
>>> -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
>>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
>>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
>>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
>>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
>>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
>>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
>>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
>>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
>>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
>>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
>>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
>>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
>>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
>>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
>>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
>>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
>>> -
>>> -/* CONTROL_SLIMBUS */
>>> -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
>>> -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
>>> -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
>>> -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
>>> -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
>>> -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
>>> -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
>>> -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
>>> -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
>>> -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
>>> -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
>>> -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
>>> -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
>>> -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
>>> -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
>>> -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
>>> -
>>> -/* CONTROL_PBIASLITE */
>>> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
>>> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
>>> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
>>> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
>>> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
>>> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
>>> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
>>> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
>>> -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
>>> -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
>>> -#define OMAP4_MMC1_PWRDNZ_SHIFT 26
>>> -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
>>> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
>>> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
>>> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
>>> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
>>> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
>>> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
>>> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
>>> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
>>> -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
>>> -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
>>> -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
>>> -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
>>> -
>>> -/* CONTROL_I2C_0 */
>>> -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
>>> -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
>>> -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
>>> -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
>>> -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
>>> -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
>>> -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
>>> -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
>>> -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
>>> -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
>>> -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
>>> -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
>>> -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
>>> -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
>>> -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
>>> -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
>>> -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
>>> -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
>>> -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
>>> -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
>>> -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
>>> -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
>>> -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
>>> -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
>>> -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
>>> -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
>>> -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
>>> -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
>>> -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
>>> -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
>>> -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
>>> -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
>>> -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
>>> -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
>>> -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
>>> -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
>>> -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
>>> -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
>>> -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
>>> -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
>>> -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
>>> -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
>>> -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
>>> -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
>>> -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
>>> -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
>>> -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
>>> -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
>>> -
>>> -/* CONTROL_CAMERA_RX */
>>> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
>>> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
>>> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
>>> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
>>> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
>>> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
>>> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
>>> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
>>> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
>>> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
>>> -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
>>> -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
>>> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
>>> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
>>> -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
>>> -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
>>> -
>>> -/* CONTROL_AVDAC */
>>> -#define OMAP4_AVDAC_ACEN_SHIFT 31
>>> -#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
>>> -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
>>> -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
>>> -#define OMAP4_AVDAC_INPUTINV_SHIFT 29
>>> -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
>>> -#define OMAP4_AVDAC_CTL_SHIFT 13
>>> -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
>>> -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
>>> -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
>>> -
>>> -/* CONTROL_HDMI_TX_PHY */
>>> -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
>>> -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
>>> -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
>>> -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
>>> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
>>> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
>>> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
>>> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
>>> -
>>> -/* CONTROL_MMC2 */
>>> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
>>> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
>>> -
>>> -/* CONTROL_DSIPHY */
>>> -#define OMAP4_DSI2_LANEENABLE_SHIFT 29
>>> -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
>>> -#define OMAP4_DSI1_LANEENABLE_SHIFT 24
>>> -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
>>> -#define OMAP4_DSI1_PIPD_SHIFT 19
>>> -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
>>> -#define OMAP4_DSI2_PIPD_SHIFT 14
>>> -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
>>> -
>>> -/* CONTROL_MCBSPLP */
>>> -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
>>> -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
>>> -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
>>> -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
>>> -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
>>> -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
>>> -
>>> -/* CONTROL_USB2PHYCORE */
>>> -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
>>> -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
>>> -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
>>> -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
>>> -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
>>> -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
>>> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
>>> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
>>> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
>>> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
>>> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
>>> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
>>> -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
>>> -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
>>> -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
>>> -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
>>> -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
>>> -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
>>> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
>>> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
>>> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
>>> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
>>> -#define OMAP4_USB2PHY_DATADET_SHIFT 18
>>> -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
>>> -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
>>> -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
>>> -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
>>> -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
>>> -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
>>> -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
>>> -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
>>> -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
>>> -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
>>> -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
>>> -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
>>> -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
>>> -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
>>> -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
>>> -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
>>> -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
>>> -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
>>> -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
>>> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
>>> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
>>> -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
>>> -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
>>> -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
>>> -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
>>> -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
>>> -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
>>> -
>>> -/* CONTROL_I2C_1 */
>>> -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
>>> -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
>>> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
>>> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
>>> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
>>> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
>>> -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
>>> -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
>>> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
>>> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
>>> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
>>> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
>>> -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
>>> -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
>>> -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
>>> -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
>>> -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
>>> -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
>>> -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
>>> -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
>>> -
>>> -/* CONTROL_MMC1 */
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
>>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
>>> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
>>> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
>>> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
>>> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
>>> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
>>> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
>>> -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
>>> -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
>>> -#define OMAP4_USB_FD_CDEN_SHIFT 23
>>> -#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
>>> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
>>> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
>>> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
>>> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
>>> -
>>> -/* CONTROL_HSI */
>>> -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
>>> -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
>>> -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
>>> -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
>>> -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
>>> -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
>>> -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
>>> -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
>>> -
>>> -/* CONTROL_USB */
>>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
>>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
>>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
>>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
>>> -
>>> -/* CONTROL_HDQ */
>>> -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
>>> -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
>>> -
>>> -/* CONTROL_LPDDR2IO1_0 */
>>> -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
>>> -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
>>> -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
>>> -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
>>> -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
>>> -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
>>> -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
>>> -
>>> -/* CONTROL_LPDDR2IO1_1 */
>>> -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
>>> -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
>>> -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
>>> -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
>>> -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
>>> -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
>>> -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
>>> -
>>> -/* CONTROL_LPDDR2IO1_2 */
>>> -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
>>> -
>>> -/* CONTROL_LPDDR2IO1_3 */
>>> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
>>> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
>>> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
>>> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
>>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
>>> -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
>>> -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
>>> -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
>>> -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
>>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
>>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
>>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
>>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
>>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
>>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
>>> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
>>> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
>>> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
>>> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
>>> -
>>> -/* CONTROL_LPDDR2IO2_0 */
>>> -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
>>> -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
>>> -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
>>> -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
>>> -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
>>> -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
>>> -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
>>> -
>>> -/* CONTROL_LPDDR2IO2_1 */
>>> -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
>>> -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
>>> -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
>>> -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
>>> -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
>>> -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
>>> -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
>>> -
>>> -/* CONTROL_LPDDR2IO2_2 */
>>> -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
>>> -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
>>> -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
>>> -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
>>> -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
>>> -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
>>> -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
>>> -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
>>> -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
>>> -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
>>> -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
>>> -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
>>> -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
>>> -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
>>> -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
>>> -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
>>> -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
>>> -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
>>> -
>>> -/* CONTROL_LPDDR2IO2_3 */
>>> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
>>> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
>>> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
>>> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
>>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
>>> -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
>>> -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
>>> -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
>>> -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
>>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
>>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
>>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
>>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
>>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
>>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
>>> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
>>> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
>>> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
>>> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
>>> -
>>> -/* CONTROL_BUS_HOLD */
>>> -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
>>> -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
>>> -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
>>> -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
>>> -
>>> -/* CONTROL_C2C */
>>> -#define OMAP4_MIRROR_MODE_EN_SHIFT 31
>>> -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
>>> -#define OMAP4_C2C_SPARE_SHIFT 24
>>> -#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
>>> -
>>> -/* CORE_CONTROL_SPARE_RW */
>>> -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
>>> -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
>>> -
>>> -/* CORE_CONTROL_SPARE_R */
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
>>> -
>>> -/* CORE_CONTROL_SPARE_R_C0 */
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
>>> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
>>> -
>>> -/* CONTROL_EFUSE_1 */
>>> -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
>>> -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
>>> -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
>>> -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
>>> -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
>>> -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
>>> -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
>>> -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
>>> -
>>> -/* CONTROL_EFUSE_2 */
>>> -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
>>> -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
>>> -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
>>> -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
>>> -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
>>> -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
>>> -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
>>> -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
>>> -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
>>> -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
>>> -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
>>> -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
>>> -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
>>> -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
>>> -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
>>> -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
>>> -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
>>> -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
>>> -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
>>> -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
>>> -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
>>> -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
>>> -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
>>> -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
>>> -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
>>> -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
>>> -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
>>> -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
>>> -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
>>> -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
>>> -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
>>> -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
>>> -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
>>> -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
>>> -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
>>> -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
>>> -
>>> -/* CONTROL_EFUSE_3 */
>>> -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
>>> -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
>>> -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
>>> -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
>>> -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
>>> -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
>>> -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
>>> -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
>>> -
>>> -/* CONTROL_EFUSE_4 */
>>> -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
>>> -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
>>> -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
>>> -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
>>> -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
>>> -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
>>> -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
>>> -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
>>> -
>>> -#endif
>>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>>> deleted file mode 100644
>>> index 17c9b37..0000000
>>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>>> +++ /dev/null
>>> @@ -1,236 +0,0 @@
>>> -/*
>>> - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
>>> - *
>>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>>> - *
>>> - * Benoit Cousson (b-cousson@ti.com)
>>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>>> - *
>>> - * This file is automatically generated from the OMAP hardware databases.
>>> - * We respectfully ask that any modifications to this file be coordinated
>>> - * with the public linux-omap@vger.kernel.org mailing list and the
>>> - * authors above to ensure that the autogeneration scripts are kept
>>> - * up-to-date with the file contents.
>>> - *
>>> - * This program is free software; you can redistribute it and/or modify
>>> - * it under the terms of the GNU General Public License version 2 as
>>> - * published by the Free Software Foundation.
>>> - */
>>> -
>>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
>>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
>>> -
>>> -
>>> -/* Base address */
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
>>> -
>>> -/* Registers offset */
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
>>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
>>> -
>>> -/* Registers shifts and masks */
>>> -
>>> -/* IP_REVISION */
>>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>>> -
>>> -/* IP_HWINFO */
>>> -#define OMAP4_IP_HWINFO_SHIFT 0
>>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>>> -
>>> -/* IP_SYSCONFIG */
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>>> -
>>> -/* PADCONF_WAKEUPEVENT_0 */
>>> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
>>> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>>> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
>>> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>>> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
>>> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>>> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
>>> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>>> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
>>> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>>> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
>>> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>>> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
>>> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>>> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
>>> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>>> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
>>> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>>> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
>>> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>>> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
>>> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>>> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
>>> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>>> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
>>> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>>> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
>>> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>>> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
>>> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>>> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
>>> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>>> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
>>> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>>> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
>>> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>>> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
>>> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>>> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
>>> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>>> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
>>> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>>> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
>>> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>>> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
>>> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>>> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
>>> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>>> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
>>> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>>> -
>>> -/* CONTROL_SMART1NOPMIO_PADCONF_0 */
>>> -#define OMAP4_FREF_DR0_SC_SHIFT 30
>>> -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
>>> -#define OMAP4_FREF_DR1_SC_SHIFT 28
>>> -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
>>> -#define OMAP4_FREF_DR4_SC_SHIFT 26
>>> -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
>>> -#define OMAP4_FREF_DR5_SC_SHIFT 24
>>> -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
>>> -#define OMAP4_FREF_DR6_SC_SHIFT 22
>>> -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
>>> -#define OMAP4_FREF_DR7_SC_SHIFT 20
>>> -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
>>> -#define OMAP4_GPIO_DR7_SC_SHIFT 18
>>> -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
>>> -#define OMAP4_DPM_DR0_SC_SHIFT 14
>>> -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
>>> -#define OMAP4_SIM_DR0_SC_SHIFT 12
>>> -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
>>> -
>>> -/* CONTROL_SMART1NOPMIO_PADCONF_1 */
>>> -#define OMAP4_FREF_DR0_LB_SHIFT 30
>>> -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
>>> -#define OMAP4_FREF_DR1_LB_SHIFT 28
>>> -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
>>> -#define OMAP4_FREF_DR4_LB_SHIFT 26
>>> -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
>>> -#define OMAP4_FREF_DR5_LB_SHIFT 24
>>> -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
>>> -#define OMAP4_FREF_DR6_LB_SHIFT 22
>>> -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
>>> -#define OMAP4_FREF_DR7_LB_SHIFT 20
>>> -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
>>> -#define OMAP4_GPIO_DR7_LB_SHIFT 18
>>> -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
>>> -#define OMAP4_DPM_DR0_LB_SHIFT 14
>>> -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
>>> -#define OMAP4_SIM_DR0_LB_SHIFT 12
>>> -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
>>> -
>>> -/* CONTROL_PADCONF_MODE */
>>> -#define OMAP4_VDDS_DV_FREF_SHIFT 31
>>> -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
>>> -#define OMAP4_VDDS_DV_BANK2_SHIFT 30
>>> -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
>>> -
>>> -/* CONTROL_XTAL_OSCILLATOR */
>>> -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
>>> -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
>>> -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
>>> -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
>>> -
>>> -/* CONTROL_USIMIO */
>>> -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
>>> -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
>>> -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
>>> -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
>>> -#define OMAP4_USIM_PWRDNZ_SHIFT 28
>>> -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
>>> -
>>> -/* CONTROL_I2C_2 */
>>> -#define OMAP4_SR_SDA_GLFENB_SHIFT 31
>>> -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
>>> -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
>>> -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
>>> -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
>>> -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
>>> -#define OMAP4_SR_SCL_GLFENB_SHIFT 27
>>> -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
>>> -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
>>> -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
>>> -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
>>> -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
>>> -
>>> -/* CONTROL_JTAG */
>>> -#define OMAP4_JTAG_NTRST_EN_SHIFT 31
>>> -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
>>> -#define OMAP4_JTAG_TCK_EN_SHIFT 30
>>> -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
>>> -#define OMAP4_JTAG_RTCK_EN_SHIFT 29
>>> -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
>>> -#define OMAP4_JTAG_TDI_EN_SHIFT 28
>>> -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
>>> -#define OMAP4_JTAG_TDO_EN_SHIFT 27
>>> -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
>>> -
>>> -/* CONTROL_SYS */
>>> -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
>>> -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
>>> -
>>> -/* WKUP_CONTROL_SPARE_RW */
>>> -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
>>> -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
>>> -
>>> -/* WKUP_CONTROL_SPARE_R */
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
>>> -
>>> -/* WKUP_CONTROL_SPARE_R_C0 */
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
>>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
>>> -
>>> -#endif
>>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>>> deleted file mode 100644
>>> index a0af9ba..0000000
>>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>>> +++ /dev/null
>>> @@ -1,92 +0,0 @@
>>> -/*
>>> - * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
>>> - *
>>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>>> - *
>>> - * Benoit Cousson (b-cousson@ti.com)
>>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>>> - *
>>> - * This file is automatically generated from the OMAP hardware databases.
>>> - * We respectfully ask that any modifications to this file be coordinated
>>> - * with the public linux-omap@vger.kernel.org mailing list and the
>>> - * authors above to ensure that the autogeneration scripts are kept
>>> - * up-to-date with the file contents.
>>> - *
>>> - * This program is free software; you can redistribute it and/or modify
>>> - * it under the terms of the GNU General Public License version 2 as
>>> - * published by the Free Software Foundation.
>>> - */
>>> -
>>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
>>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
>>> -
>>> -
>>> -/* Base address */
>>> -#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
>>> -
>>> -/* Registers offset */
>>> -#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
>>> -#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
>>> -#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
>>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
>>> -
>>> -/* Registers shifts and masks */
>>> -
>>> -/* IP_REVISION */
>>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>>> -
>>> -/* IP_HWINFO */
>>> -#define OMAP4_IP_HWINFO_SHIFT 0
>>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>>> -
>>> -/* IP_SYSCONFIG */
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>>> -
>>> -/* CONF_DEBUG_SEL_TST_0 */
>>> -#define OMAP4_WKUP_MODE_SHIFT 0
>>> -#define OMAP4_WKUP_MODE_MASK (1 << 0)
>>> -
>>> -#endif
>>> --
>>> 1.7.7.6
>>>
>>>
>
--
Eduardo Valentin
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Konstantin Baydarov @ 2012-06-28 9:37 UTC (permalink / raw)
To: eduardo.valentin
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap
In-Reply-To: <20120628045028.GC2471@besouro>
Hi.
On 06/28/2012 08:50 AM, Eduardo Valentin wrote:
> Hello,
>
> On Wed, Jun 27, 2012 at 10:04:54PM +0400, Konstantin Baydarov wrote:
>> This patch introduces a MFD core device driver for OMAP system control module.
>>
>> The control module allows software control of various static modes supported by the device.
>> It is composed of two control submodules: general control module and device (padconfiguration) control module.
>>
>> Changes since previous version:
>> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
>> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
>> Probably, no configuration option is required!
>> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
>> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
>> module device.
>> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
>> - omap-control-core: added omap_control_status_read that is used early in omap_type
>>
>> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
>> Signed-off-by: J Keerthy <j-keerthy@ti.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
>> ---
>> .../devicetree/bindings/mfd/omap_control.txt | 44 +++++++
>> arch/arm/mach-omap2/Kconfig | 1 +
>> arch/arm/plat-omap/Kconfig | 4 +
>> drivers/mfd/Kconfig | 9 ++
>> drivers/mfd/Makefile | 1 +
>> drivers/mfd/omap-control-core.c | 131 ++++++++++++++++++++
>> include/linux/mfd/omap_control.h | 52 ++++++++
>> 7 files changed, 242 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/mfd/omap_control.txt
>> create mode 100644 drivers/mfd/omap-control-core.c
>> create mode 100644 include/linux/mfd/omap_control.h
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/omap_control.txt b/Documentation/devicetree/bindings/mfd/omap_control.txt
>> new file mode 100644
>> index 0000000..46d5e7e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/omap_control.txt
>> @@ -0,0 +1,44 @@
>> +* Texas Instrument OMAP System Control Module (SCM) bindings
>> +
>> +The control module allows software control of various static modes supported by
>> +the device. The control module controls the settings of various device modules
>> +through register configuration and internal signals. It also controls the pad
>> +configuration, pin functional multiplexing, and the routing of internal signals
>> +(such as PRCM signals or DMA requests) to output pins configured for hardware
>> +observability.
>> +
>> +Required properties:
>> +- compatible : Should be:
>> + - "ti,omap3-control" for OMAP3 support
>> + - "ti,omap4-control" for OMAP4 support
>> + - "ti,omap5-control" for OMAP5 support
>> +
>> +OMAP specific properties:
>> +- ti,hwmods: Name of the hwmod associated to the control module:
>> + Should be "ctrl_module_core";
>> +
>> +Sub-nodes:
>> +- bandgap : contains the bandgap node
>> +
>> + The bindings details of individual bandgap device can be found in:
>> + Documentation/devicetree/bindings/thermal/omap_bandgap.txt
>> +
>> +- usb : contains the usb phy pin control node
>> +
>> + The only required property for this child is:
>> + - compatible = "ti,omap4-control-usb";
>> +
>> +Examples:
>> +
>> +ctrl_module_core: ctrl_module_core@4a002000 {
>> + compatible = "ti,omap4-control";
>> + ti,hwmods = "ctrl_module_core";
>> + bandgap {
>> + compatible = "ti,omap4460-bandgap";
> You need to update the documentation if change the DT structure.
Ok.
>
>> + interrupts = <0 126 4>; /* talert */
>> + ti,tshut-gpio = <86>; /* tshut */
>> + };
>> + usb {
>> + compatible = "ti,omap4-usb-phy";
>> + };
>> +};
>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>> index 4cf5142..c2ef07c 100644
>> --- a/arch/arm/mach-omap2/Kconfig
>> +++ b/arch/arm/mach-omap2/Kconfig
>> @@ -52,6 +52,7 @@ config ARCH_OMAP4
>> select PL310_ERRATA_727915
>> select ARM_ERRATA_720789
>> select ARCH_HAS_OPP
>> + select ARCH_HAS_CONTROL_MODULE
>> select PM_OPP if PM
>> select USB_ARCH_HAS_EHCI if USB_SUPPORT
>> select ARM_CPU_SUSPEND if PM
>> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
>> index ad95c7a..0f9b575 100644
>> --- a/arch/arm/plat-omap/Kconfig
>> +++ b/arch/arm/plat-omap/Kconfig
>> @@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
>> config ARCH_OMAP_OTG
>> bool
>>
>> +config ARCH_HAS_CONTROL_MODULE
>> + bool
>> + select MFD_OMAP_CONTROL
>> +
> OK now I got what you meant in patch 0. Fine for me.
>
>> choice
>> prompt "OMAP System Type"
>> default ARCH_OMAP2PLUS
>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>> index e129c82..d0c5456 100644
>> --- a/drivers/mfd/Kconfig
>> +++ b/drivers/mfd/Kconfig
>> @@ -822,6 +822,15 @@ config MFD_WL1273_CORE
>> driver connects the radio-wl1273 V4L2 module and the wl1273
>> audio codec.
>>
>> +config MFD_OMAP_CONTROL
>> + bool "Texas Instruments OMAP System control module"
>> + depends on ARCH_HAS_CONTROL_MODULE
>> + help
>> + This is the core driver for system control module. This driver
>> + is responsible for creating the control module mfd child,
>> + like USB-pin control, pin muxing, MMC-pbias and DDR IO dynamic
>> + change for off mode.
>> +
>> config MFD_OMAP_USB_HOST
>> bool "Support OMAP USBHS core driver"
>> depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>> index 75f6ed6..b037443 100644
>> --- a/drivers/mfd/Makefile
>> +++ b/drivers/mfd/Makefile
>> @@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
>> obj-$(CONFIG_MFD_VX855) += vx855.o
>> obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
>> obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
>> +obj-$(CONFIG_MFD_OMAP_CONTROL) += omap-control-core.o
>> obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
>> obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
>> obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
>> diff --git a/drivers/mfd/omap-control-core.c b/drivers/mfd/omap-control-core.c
>> new file mode 100644
>> index 0000000..724c51b
>> --- /dev/null
>> +++ b/drivers/mfd/omap-control-core.c
>> @@ -0,0 +1,131 @@
>> +/*
>> + * OMAP system control module driver file
>> + *
>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>> + * Contacts:
>> + * Based on original code written by:
>> + * J Keerthy <j-keerthy@ti.com>
>> + * Moiz Sonasath <m-sonasath@ti.com>
>> + * MFD clean up and re-factoring:
>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * General Public License for more details.
>> + *
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/export.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_address.h>
>> +#include <linux/mfd/core.h>
>> +#include <linux/mfd/omap_control.h>
>> +
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +
>> +void __iomem *omap_control_base;
>> +
>> +u32 omap_control_status_read(u16 offset)
>> +{
>> + return __raw_readl(omap_control_base + (offset));
>> +}
>> +
>> +static const struct of_device_id of_omap_control_match[] = {
>> + { .compatible = "ti,omap3-control", },
>> + { .compatible = "ti,omap4-control", },
>> + { .compatible = "ti,omap5-control", },
>> + { },
>> +};
>> +
>> +static int __devinit omap_control_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> +
>> + /*
>> + * Build child defvices of ctrl_module_core
>> + */
>> + return of_platform_populate(np, of_omap_control_match, NULL, dev);
>> +}
>> +
>> +
>> +static struct platform_driver omap_control_driver = {
>> + .probe = omap_control_probe,
>> + .driver = {
>> + .name = "omap-control-core",
>> + .owner = THIS_MODULE,
>> + .of_match_table = of_omap_control_match,
>> + },
>> +};
>> +
>> +int __init omap_control_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> + struct resource res;
>> +
>> + if (WARN_ON(!node))
>> + return -ENODEV;
>> +
>> + if (of_address_to_resource(node, 0, &res)) {
>> + WARN(1, "unable to get intc registers\n");
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
> The above function is used nowhere.
Agree.
>
>> +
>> +void __init of_omap_control_init(const struct of_device_id *matches)
>> +{
>> + struct device_node *np;
>> + struct property *pp = 0;
>> + unsigned long phys_base = 0;
>> + size_t mapsize = 0;
>> +
>> + for_each_matching_node(np, matches) {
>> +
>> + pp = of_find_property(np, "reg", NULL);
>> + if(pp) {
>> + phys_base = (unsigned long)be32_to_cpup(pp->value);
>> + mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
>> + omap_control_base = ioremap(phys_base, mapsize);
> How the reservation is going to work?
This can be done following way:
- omap-control-core.c ioremaps and reserves SCM IOMEM window
- omap-control-core.c exports omap_control_get_base(virtual base address is returned) to use in bandgap and usb_phy driver.
IIUC, this way was suggested by Tony.
>
>> + }
>> + }
>> +}
>> +
>> +static int __init
>> +omap_control_early_initcall(void)
>> +{
>> + of_omap_control_init(of_omap_control_match);
>> +
>> + return 0;
>> +}
>> +early_initcall(omap_control_early_initcall);
>> +
>> +static int __init omap_control_init(void)
>> +{
>> + return platform_driver_register(&omap_control_driver);
>> +}
>> +postcore_initcall_sync(omap_control_init);
>> +
>> +static void __exit omap_control_exit(void)
>> +{
>> + platform_driver_unregister(&omap_control_driver);
>> +}
>> +module_exit(omap_control_exit);
>> +early_platform_init("early_omap_control", &omap_control_driver);
> early_platform_init is not needed as you are implementing the early reads in a different way.
Right.
>
>> +
>> +MODULE_DESCRIPTION("OMAP system control module driver");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:omap-control-core");
>> +MODULE_AUTHOR("Texas Instruments Inc.");
>> diff --git a/include/linux/mfd/omap_control.h b/include/linux/mfd/omap_control.h
>> new file mode 100644
>> index 0000000..1795403
>> --- /dev/null
>> +++ b/include/linux/mfd/omap_control.h
>> @@ -0,0 +1,52 @@
>> +/*
>> + * OMAP system control module header file
>> + *
>> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
>> + * Contact:
>> + * J Keerthy <j-keerthy@ti.com>
>> + * Moiz Sonasath <m-sonasath@ti.com>
>> + * Abraham, Kishon Vijay <kishon@ti.com>
>> + * Eduardo Valentin <eduardo.valentin@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * General Public License for more details.
>> + *
>> + */
>> +
>> +#ifndef __DRIVERS_OMAP_CONTROL_H
>> +#define __DRIVERS_OMAP_CONTROL_H
>> +
>> +#include <linux/err.h>
>> +
>> +/**
>> + * struct system control module - scm device structure
>> + * @dev: device pointer
>> + * @base: Base of the temp I/O
>> + * @reg_lock: protect omap_control structure
>> + * @use_count: track API users
>> + */
>> +struct omap_control {
>> + struct device *dev;
>> + void __iomem *base;
>> + /* protect this data structure and register access */
>> + spinlock_t reg_lock;
>> + int use_count;
> I suppose the reg_lock and the use_count are not needed in this design?
Right.
>
>> +};
>> +
>> +/* TODO: Add helpers for 16bit and byte access */
>> +#ifdef CONFIG_MFD_OMAP_CONTROL
>> +u32 omap_control_status_read(u16 offset);
>> +#else
>> +static inline u32 omap_control_status_read(u16 offset)
>> +{
>> + return 0;
>> +}
>> +#endif
>> +
>> +#endif /* __DRIVERS_OMAP_CONTROL_H */
>> --
>> 1.7.7.6
>>
>>
> --
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* Re: [PATCH v3 1/7] ARM: OMAP4: Remove un-used control module headers and defines.
From: Konstantin Baydarov @ 2012-06-28 9:25 UTC (permalink / raw)
To: eduardo.valentin
Cc: paul, b-cousson, tony, balbi, kishon, santosh.shilimkar,
amit.kucheria, linux-pm, linux-omap, linux-arm-kernel,
amit.kachhap
In-Reply-To: <20120628044525.GB2471@besouro>
Hi, Eduardo.
On 06/28/2012 08:45 AM, Eduardo Valentin wrote:
> Why the authorship of these patches is changing?
Did I change Signed-off-by field? Could you clarify.
>
> For instance this patch, from Santosh, I believe it is the same...
>
> On Wed, Jun 27, 2012 at 10:04:47PM +0400, Konstantin Baydarov wrote:
>> Most of the OMAP4 control module register defines are not used and
>> can be removed. Keep only needed defines and move them to common
>> control module header just like other OMAP versions.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
>> ---
>> arch/arm/mach-omap2/control.h | 45 +-
>> .../include/mach/ctrl_module_core_44xx.h | 391 ------
>> .../include/mach/ctrl_module_pad_core_44xx.h | 1409 --------------------
>> .../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ----
>> .../include/mach/ctrl_module_wkup_44xx.h | 92 --
>> 5 files changed, 40 insertions(+), 2133 deletions(-)
>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>>
>> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
>> index a406fd0..dad2903 100644
>> --- a/arch/arm/mach-omap2/control.h
>> +++ b/arch/arm/mach-omap2/control.h
>> @@ -16,11 +16,6 @@
>> #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
>> #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
>>
>> -#include <mach/ctrl_module_core_44xx.h>
>> -#include <mach/ctrl_module_wkup_44xx.h>
>> -#include <mach/ctrl_module_pad_core_44xx.h>
>> -#include <mach/ctrl_module_pad_wkup_44xx.h>
>> -
>> #ifndef __ASSEMBLY__
>> #define OMAP242X_CTRL_REGADDR(reg) \
>> OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
>> @@ -183,6 +178,43 @@
>> #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
>> #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
>>
>> +/* OMAP4 IDCODE CONTROL */
>> +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
>> +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
>> +
>> +/* CONTROL_I2C_1 */
>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
>> +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
>> +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
>> +
>> +/* DSI CONTROL_DSIPHY */
>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
>> +#define OMAP4_DSI2_LANEENABLE_SHIFT 29
>> +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
>> +#define OMAP4_DSI1_LANEENABLE_SHIFT 24
>> +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
>> +#define OMAP4_DSI1_PIPD_SHIFT 19
>> +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
>> +#define OMAP4_DSI2_PIPD_SHIFT 14
>> +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
>> +
>> +/* CONTROL_PBIASLITE */
>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
>> +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
>> +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
>> +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
>> +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
>> +
>> +/* CONTROL_MMC1 */
>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
>> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
>> +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
>> +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
>> +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
>> +
>> /* OMAP44xx control efuse offsets */
>> #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
>> #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
>> @@ -195,6 +227,9 @@
>> #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
>> #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
>>
>> +/* OMAP44xx control McBSP padconf */
>> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
>> +
>> /* AM35XX only CONTROL_GENERAL register offsets */
>> #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
>> #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>> deleted file mode 100644
>> index 2f7ac70..0000000
>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
>> +++ /dev/null
>> @@ -1,391 +0,0 @@
>> -/*
>> - * OMAP44xx CTRL_MODULE_CORE registers and bitfields
>> - *
>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>> - *
>> - * Benoit Cousson (b-cousson@ti.com)
>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>> - *
>> - * This file is automatically generated from the OMAP hardware databases.
>> - * We respectfully ask that any modifications to this file be coordinated
>> - * with the public linux-omap@vger.kernel.org mailing list and the
>> - * authors above to ensure that the autogeneration scripts are kept
>> - * up-to-date with the file contents.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> - */
>> -
>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
>> -
>> -
>> -/* Base address */
>> -#define OMAP4_CTRL_MODULE_CORE 0x4a002000
>> -
>> -/* Registers offset */
>> -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
>> -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
>> -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
>> -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
>> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
>> -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
>> -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
>> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
>> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
>> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
>> -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
>> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
>> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
>> -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
>> -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
>> -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
>> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
>> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
>> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
>> -
>> -/* Registers shifts and masks */
>> -
>> -/* IP_REVISION */
>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>> -
>> -/* IP_HWINFO */
>> -#define OMAP4_IP_HWINFO_SHIFT 0
>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>> -
>> -/* IP_SYSCONFIG */
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>> -
>> -/* STD_FUSE_DIE_ID_0 */
>> -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
>> -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
>> -
>> -/* ID_CODE */
>> -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
>> -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_DIE_ID_1 */
>> -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
>> -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_DIE_ID_2 */
>> -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
>> -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_DIE_ID_3 */
>> -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
>> -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_PROD_ID_0 */
>> -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
>> -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_PROD_ID_1 */
>> -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
>> -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_USB_CONF */
>> -#define OMAP4_USB_PROD_ID_SHIFT 16
>> -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
>> -#define OMAP4_USB_VENDOR_ID_SHIFT 0
>> -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
>> -
>> -/* STD_FUSE_OPP_VDD_WKUP */
>> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
>> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_OPP_BGAP */
>> -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
>> -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_OPP_DPLL_0 */
>> -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
>> -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
>> -
>> -/* STD_FUSE_OPP_DPLL_1 */
>> -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
>> -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
>> -
>> -/* STATUS */
>> -#define OMAP4_ATTILA_CONF_SHIFT 11
>> -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
>> -#define OMAP4_DEVICE_TYPE_SHIFT 8
>> -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
>> -#define OMAP4_SYS_BOOT_SHIFT 0
>> -#define OMAP4_SYS_BOOT_MASK (0xff << 0)
>> -
>> -/* DEV_CONF */
>> -#define OMAP4_DEV_CONF_SHIFT 1
>> -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
>> -#define OMAP4_USBPHY_PD_SHIFT 0
>> -#define OMAP4_USBPHY_PD_MASK (1 << 0)
>> -
>> -/* LDOVBB_IVA_VOLTAGE_CTRL */
>> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
>> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
>> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
>> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
>> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
>> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
>> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
>> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
>> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
>> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
>> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
>> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
>> -
>> -/* LDOVBB_MPU_VOLTAGE_CTRL */
>> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
>> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
>> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
>> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
>> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
>> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
>> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
>> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
>> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
>> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
>> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
>> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
>> -
>> -/* LDOSRAM_IVA_VOLTAGE_CTRL */
>> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
>> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
>> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
>> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>> -
>> -/* LDOSRAM_MPU_VOLTAGE_CTRL */
>> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
>> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
>> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
>> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>> -
>> -/* LDOSRAM_CORE_VOLTAGE_CTRL */
>> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
>> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
>> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
>> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
>> -
>> -/* TEMP_SENSOR */
>> -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
>> -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
>> -#define OMAP4_BGAP_TSHUT_SHIFT 11
>> -#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
>> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
>> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
>> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
>> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
>> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
>> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
>> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
>> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
>> -
>> -/* DPLL_NWELL_TRIM_0 */
>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
>> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
>> -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
>> -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
>> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
>> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
>> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
>> -
>> -/* DPLL_NWELL_TRIM_1 */
>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
>> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
>> -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
>> -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
>> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
>> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
>> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
>> -
>> -/* USBOTGHS_CONTROL */
>> -#define OMAP4_DISCHRGVBUS_SHIFT 8
>> -#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
>> -#define OMAP4_CHRGVBUS_SHIFT 7
>> -#define OMAP4_CHRGVBUS_MASK (1 << 7)
>> -#define OMAP4_DRVVBUS_SHIFT 6
>> -#define OMAP4_DRVVBUS_MASK (1 << 6)
>> -#define OMAP4_IDPULLUP_SHIFT 5
>> -#define OMAP4_IDPULLUP_MASK (1 << 5)
>> -#define OMAP4_IDDIG_SHIFT 4
>> -#define OMAP4_IDDIG_MASK (1 << 4)
>> -#define OMAP4_SESSEND_SHIFT 3
>> -#define OMAP4_SESSEND_MASK (1 << 3)
>> -#define OMAP4_VBUSVALID_SHIFT 2
>> -#define OMAP4_VBUSVALID_MASK (1 << 2)
>> -#define OMAP4_BVALID_SHIFT 1
>> -#define OMAP4_BVALID_MASK (1 << 1)
>> -#define OMAP4_AVALID_SHIFT 0
>> -#define OMAP4_AVALID_MASK (1 << 0)
>> -
>> -/* DSS_CONTROL */
>> -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
>> -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
>> -
>> -/* HWOBS_CONTROL */
>> -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
>> -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
>> -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
>> -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
>> -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
>> -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
>> -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
>> -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
>> -
>> -/* DEBOBS_FINAL_MUX_SEL */
>> -#define OMAP4_SELECT_SHIFT 0
>> -#define OMAP4_SELECT_MASK (0xffffffff << 0)
>> -
>> -/* DEBOBS_MMR_MPU */
>> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
>> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
>> -
>> -/* CONF_SDMA_REQ_SEL0 */
>> -#define OMAP4_MULT_SHIFT 0
>> -#define OMAP4_MULT_MASK (0x7f << 0)
>> -
>> -/* CONF_CLK_SEL0 */
>> -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
>> -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
>> -
>> -/* CONF_CLK_SEL1 */
>> -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
>> -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
>> -
>> -/* CONF_CLK_SEL2 */
>> -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
>> -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
>> -
>> -/* CONF_DPLL_FREQLOCK_SEL */
>> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
>> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
>> -
>> -/* CONF_DPLL_TINITZ_SEL */
>> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
>> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
>> -
>> -/* CONF_DPLL_PHASELOCK_SEL */
>> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
>> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
>> -
>> -/* CONF_DEBUG_SEL_TST_0 */
>> -#define OMAP4_MODE_SHIFT 0
>> -#define OMAP4_MODE_MASK (0xf << 0)
>> -
>> -#endif
>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> deleted file mode 100644
>> index c88420d..0000000
>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> +++ /dev/null
>> @@ -1,1409 +0,0 @@
>> -/*
>> - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
>> - *
>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>> - *
>> - * Benoit Cousson (b-cousson@ti.com)
>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>> - *
>> - * This file is automatically generated from the OMAP hardware databases.
>> - * We respectfully ask that any modifications to this file be coordinated
>> - * with the public linux-omap@vger.kernel.org mailing list and the
>> - * authors above to ensure that the autogeneration scripts are kept
>> - * up-to-date with the file contents.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> - */
>> -
>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
>> -
>> -
>> -/* Base address */
>> -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
>> -
>> -/* Registers offset */
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
>> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
>> -
>> -/* Registers shifts and masks */
>> -
>> -/* IP_REVISION */
>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>> -
>> -/* IP_HWINFO */
>> -#define OMAP4_IP_HWINFO_SHIFT 0
>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>> -
>> -/* IP_SYSCONFIG */
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>> -
>> -/* PADCONF_WAKEUPEVENT_0 */
>> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_1 */
>> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_2 */
>> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_3 */
>> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_4 */
>> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_5 */
>> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
>> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
>> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
>> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
>> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
>> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
>> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
>> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
>> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
>> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
>> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
>> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
>> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
>> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
>> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* PADCONF_WAKEUPEVENT_6 */
>> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* CONTROL_PADCONF_GLOBAL */
>> -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
>> -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
>> -
>> -/* CONTROL_PADCONF_MODE */
>> -#define OMAP4_VDDS_DV_BANK0_SHIFT 31
>> -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
>> -#define OMAP4_VDDS_DV_BANK1_SHIFT 30
>> -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
>> -#define OMAP4_VDDS_DV_BANK3_SHIFT 29
>> -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
>> -#define OMAP4_VDDS_DV_BANK4_SHIFT 28
>> -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
>> -#define OMAP4_VDDS_DV_BANK5_SHIFT 27
>> -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
>> -#define OMAP4_VDDS_DV_BANK6_SHIFT 26
>> -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
>> -#define OMAP4_VDDS_DV_C2C_SHIFT 25
>> -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
>> -#define OMAP4_VDDS_DV_CAM_SHIFT 24
>> -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
>> -#define OMAP4_VDDS_DV_GPMC_SHIFT 23
>> -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
>> -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
>> -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
>> -
>> -/* CONTROL_SMART1IO_PADCONF_0 */
>> -#define OMAP4_ABE_DR0_SC_SHIFT 30
>> -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
>> -#define OMAP4_CAM_DR0_SC_SHIFT 28
>> -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
>> -#define OMAP4_FREF_DR2_SC_SHIFT 26
>> -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
>> -#define OMAP4_FREF_DR3_SC_SHIFT 24
>> -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
>> -#define OMAP4_GPIO_DR8_SC_SHIFT 22
>> -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
>> -#define OMAP4_GPIO_DR9_SC_SHIFT 20
>> -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
>> -#define OMAP4_GPMC_DR2_SC_SHIFT 18
>> -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
>> -#define OMAP4_GPMC_DR3_SC_SHIFT 16
>> -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
>> -#define OMAP4_GPMC_DR6_SC_SHIFT 14
>> -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
>> -#define OMAP4_HDMI_DR0_SC_SHIFT 12
>> -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
>> -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
>> -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
>> -#define OMAP4_UART1_DR0_SC_SHIFT 8
>> -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
>> -#define OMAP4_UART3_DR0_SC_SHIFT 6
>> -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
>> -#define OMAP4_UART3_DR1_SC_SHIFT 4
>> -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
>> -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
>> -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
>> -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
>> -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
>> -
>> -/* CONTROL_SMART1IO_PADCONF_1 */
>> -#define OMAP4_ABE_DR0_LB_SHIFT 30
>> -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
>> -#define OMAP4_CAM_DR0_LB_SHIFT 28
>> -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
>> -#define OMAP4_FREF_DR2_LB_SHIFT 26
>> -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
>> -#define OMAP4_FREF_DR3_LB_SHIFT 24
>> -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
>> -#define OMAP4_GPIO_DR8_LB_SHIFT 22
>> -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
>> -#define OMAP4_GPIO_DR9_LB_SHIFT 20
>> -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
>> -#define OMAP4_GPMC_DR2_LB_SHIFT 18
>> -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
>> -#define OMAP4_GPMC_DR3_LB_SHIFT 16
>> -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
>> -#define OMAP4_GPMC_DR6_LB_SHIFT 14
>> -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
>> -#define OMAP4_HDMI_DR0_LB_SHIFT 12
>> -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
>> -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
>> -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
>> -#define OMAP4_UART1_DR0_LB_SHIFT 8
>> -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
>> -#define OMAP4_UART3_DR0_LB_SHIFT 6
>> -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
>> -#define OMAP4_UART3_DR1_LB_SHIFT 4
>> -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
>> -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
>> -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
>> -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
>> -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
>> -
>> -/* CONTROL_SMART2IO_PADCONF_0 */
>> -#define OMAP4_C2C_DR0_LB_SHIFT 31
>> -#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
>> -#define OMAP4_DPM_DR1_LB_SHIFT 30
>> -#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
>> -#define OMAP4_DPM_DR2_LB_SHIFT 29
>> -#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
>> -#define OMAP4_DPM_DR3_LB_SHIFT 28
>> -#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
>> -#define OMAP4_GPIO_DR0_LB_SHIFT 27
>> -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
>> -#define OMAP4_GPIO_DR1_LB_SHIFT 26
>> -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
>> -#define OMAP4_GPIO_DR10_LB_SHIFT 25
>> -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
>> -#define OMAP4_GPIO_DR2_LB_SHIFT 24
>> -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
>> -#define OMAP4_GPMC_DR0_LB_SHIFT 23
>> -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
>> -#define OMAP4_GPMC_DR1_LB_SHIFT 22
>> -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
>> -#define OMAP4_GPMC_DR4_LB_SHIFT 21
>> -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
>> -#define OMAP4_GPMC_DR5_LB_SHIFT 20
>> -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
>> -#define OMAP4_GPMC_DR7_LB_SHIFT 19
>> -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
>> -#define OMAP4_HSI2_DR0_LB_SHIFT 18
>> -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
>> -#define OMAP4_HSI2_DR1_LB_SHIFT 17
>> -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
>> -#define OMAP4_HSI2_DR2_LB_SHIFT 16
>> -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
>> -#define OMAP4_KPD_DR0_LB_SHIFT 15
>> -#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
>> -#define OMAP4_KPD_DR1_LB_SHIFT 14
>> -#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
>> -#define OMAP4_PDM_DR0_LB_SHIFT 13
>> -#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
>> -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
>> -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
>> -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
>> -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
>> -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
>> -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
>> -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
>> -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
>> -#define OMAP4_SPI3_DR0_LB_SHIFT 8
>> -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
>> -#define OMAP4_SPI3_DR1_LB_SHIFT 7
>> -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
>> -#define OMAP4_UART3_DR2_LB_SHIFT 6
>> -#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
>> -#define OMAP4_UART3_DR3_LB_SHIFT 5
>> -#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
>> -#define OMAP4_UART3_DR4_LB_SHIFT 4
>> -#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
>> -#define OMAP4_UART3_DR5_LB_SHIFT 3
>> -#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
>> -#define OMAP4_USBA0_DR1_LB_SHIFT 2
>> -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
>> -#define OMAP4_USBA_DR2_LB_SHIFT 1
>> -#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
>> -
>> -/* CONTROL_SMART2IO_PADCONF_1 */
>> -#define OMAP4_USBB1_DR0_LB_SHIFT 31
>> -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
>> -#define OMAP4_USBB2_DR0_LB_SHIFT 30
>> -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
>> -#define OMAP4_USBA0_DR0_LB_SHIFT 29
>> -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
>> -
>> -/* CONTROL_SMART3IO_PADCONF_0 */
>> -#define OMAP4_DMIC_DR0_MB_SHIFT 30
>> -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
>> -#define OMAP4_GPIO_DR3_MB_SHIFT 28
>> -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
>> -#define OMAP4_GPIO_DR4_MB_SHIFT 26
>> -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
>> -#define OMAP4_GPIO_DR5_MB_SHIFT 24
>> -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
>> -#define OMAP4_GPIO_DR6_MB_SHIFT 22
>> -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
>> -#define OMAP4_HSI_DR1_MB_SHIFT 20
>> -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
>> -#define OMAP4_HSI_DR2_MB_SHIFT 18
>> -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
>> -#define OMAP4_HSI_DR3_MB_SHIFT 16
>> -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
>> -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
>> -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
>> -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
>> -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
>> -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
>> -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
>> -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
>> -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
>> -#define OMAP4_SPI2_DR0_MB_SHIFT 0
>> -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
>> -
>> -/* CONTROL_SMART3IO_PADCONF_1 */
>> -#define OMAP4_SPI2_DR1_MB_SHIFT 30
>> -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
>> -#define OMAP4_SPI2_DR2_MB_SHIFT 28
>> -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
>> -#define OMAP4_UART2_DR0_MB_SHIFT 26
>> -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
>> -#define OMAP4_UART2_DR1_MB_SHIFT 24
>> -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
>> -#define OMAP4_UART4_DR0_MB_SHIFT 22
>> -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
>> -#define OMAP4_HSI_DR0_MB_SHIFT 20
>> -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
>> -
>> -/* CONTROL_SMART3IO_PADCONF_2 */
>> -#define OMAP4_DMIC_DR0_LB_SHIFT 31
>> -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
>> -#define OMAP4_GPIO_DR3_LB_SHIFT 30
>> -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
>> -#define OMAP4_GPIO_DR4_LB_SHIFT 29
>> -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
>> -#define OMAP4_GPIO_DR5_LB_SHIFT 28
>> -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
>> -#define OMAP4_GPIO_DR6_LB_SHIFT 27
>> -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
>> -#define OMAP4_HSI_DR1_LB_SHIFT 26
>> -#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
>> -#define OMAP4_HSI_DR2_LB_SHIFT 25
>> -#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
>> -#define OMAP4_HSI_DR3_LB_SHIFT 24
>> -#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
>> -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
>> -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
>> -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
>> -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
>> -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
>> -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
>> -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
>> -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
>> -#define OMAP4_SPI2_DR0_LB_SHIFT 16
>> -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
>> -#define OMAP4_SPI2_DR1_LB_SHIFT 15
>> -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
>> -#define OMAP4_SPI2_DR2_LB_SHIFT 14
>> -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
>> -#define OMAP4_UART2_DR0_LB_SHIFT 13
>> -#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
>> -#define OMAP4_UART2_DR1_LB_SHIFT 12
>> -#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
>> -#define OMAP4_UART4_DR0_LB_SHIFT 11
>> -#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
>> -#define OMAP4_HSI_DR0_LB_SHIFT 10
>> -#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
>> -
>> -/* CONTROL_USBB_HSIC */
>> -#define OMAP4_USBB2_DR1_SR_SHIFT 30
>> -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
>> -#define OMAP4_USBB2_DR1_I_SHIFT 27
>> -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
>> -#define OMAP4_USBB1_DR1_SR_SHIFT 25
>> -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
>> -#define OMAP4_USBB1_DR1_I_SHIFT 22
>> -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
>> -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
>> -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
>> -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
>> -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
>> -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
>> -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
>> -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
>> -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
>> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
>> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
>> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
>> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
>> -
>> -/* CONTROL_SLIMBUS */
>> -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
>> -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
>> -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
>> -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
>> -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
>> -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
>> -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
>> -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
>> -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
>> -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
>> -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
>> -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
>> -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
>> -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
>> -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
>> -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
>> -
>> -/* CONTROL_PBIASLITE */
>> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
>> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
>> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
>> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
>> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
>> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
>> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
>> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
>> -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
>> -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
>> -#define OMAP4_MMC1_PWRDNZ_SHIFT 26
>> -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
>> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
>> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
>> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
>> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
>> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
>> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
>> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
>> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
>> -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
>> -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
>> -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
>> -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
>> -
>> -/* CONTROL_I2C_0 */
>> -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
>> -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
>> -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
>> -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
>> -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
>> -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
>> -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
>> -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
>> -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
>> -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
>> -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
>> -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
>> -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
>> -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
>> -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
>> -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
>> -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
>> -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
>> -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
>> -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
>> -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
>> -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
>> -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
>> -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
>> -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
>> -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
>> -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
>> -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
>> -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
>> -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
>> -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
>> -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
>> -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
>> -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
>> -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
>> -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
>> -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
>> -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
>> -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
>> -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
>> -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
>> -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
>> -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
>> -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
>> -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
>> -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
>> -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
>> -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
>> -
>> -/* CONTROL_CAMERA_RX */
>> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
>> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
>> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
>> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
>> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
>> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
>> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
>> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
>> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
>> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
>> -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
>> -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
>> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
>> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
>> -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
>> -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
>> -
>> -/* CONTROL_AVDAC */
>> -#define OMAP4_AVDAC_ACEN_SHIFT 31
>> -#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
>> -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
>> -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
>> -#define OMAP4_AVDAC_INPUTINV_SHIFT 29
>> -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
>> -#define OMAP4_AVDAC_CTL_SHIFT 13
>> -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
>> -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
>> -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
>> -
>> -/* CONTROL_HDMI_TX_PHY */
>> -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
>> -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
>> -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
>> -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
>> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
>> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
>> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
>> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
>> -
>> -/* CONTROL_MMC2 */
>> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
>> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
>> -
>> -/* CONTROL_DSIPHY */
>> -#define OMAP4_DSI2_LANEENABLE_SHIFT 29
>> -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
>> -#define OMAP4_DSI1_LANEENABLE_SHIFT 24
>> -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
>> -#define OMAP4_DSI1_PIPD_SHIFT 19
>> -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
>> -#define OMAP4_DSI2_PIPD_SHIFT 14
>> -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
>> -
>> -/* CONTROL_MCBSPLP */
>> -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
>> -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
>> -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
>> -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
>> -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
>> -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
>> -
>> -/* CONTROL_USB2PHYCORE */
>> -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
>> -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
>> -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
>> -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
>> -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
>> -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
>> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
>> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
>> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
>> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
>> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
>> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
>> -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
>> -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
>> -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
>> -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
>> -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
>> -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
>> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
>> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
>> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
>> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
>> -#define OMAP4_USB2PHY_DATADET_SHIFT 18
>> -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
>> -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
>> -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
>> -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
>> -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
>> -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
>> -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
>> -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
>> -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
>> -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
>> -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
>> -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
>> -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
>> -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
>> -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
>> -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
>> -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
>> -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
>> -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
>> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
>> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
>> -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
>> -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
>> -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
>> -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
>> -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
>> -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
>> -
>> -/* CONTROL_I2C_1 */
>> -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
>> -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
>> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
>> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
>> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
>> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
>> -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
>> -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
>> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
>> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
>> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
>> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
>> -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
>> -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
>> -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
>> -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
>> -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
>> -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
>> -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
>> -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
>> -
>> -/* CONTROL_MMC1 */
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
>> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
>> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
>> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
>> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
>> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
>> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
>> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
>> -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
>> -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
>> -#define OMAP4_USB_FD_CDEN_SHIFT 23
>> -#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
>> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
>> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
>> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
>> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
>> -
>> -/* CONTROL_HSI */
>> -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
>> -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
>> -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
>> -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
>> -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
>> -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
>> -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
>> -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
>> -
>> -/* CONTROL_USB */
>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
>> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
>> -
>> -/* CONTROL_HDQ */
>> -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
>> -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
>> -
>> -/* CONTROL_LPDDR2IO1_0 */
>> -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
>> -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
>> -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
>> -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
>> -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
>> -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
>> -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
>> -
>> -/* CONTROL_LPDDR2IO1_1 */
>> -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
>> -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
>> -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
>> -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
>> -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
>> -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
>> -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
>> -
>> -/* CONTROL_LPDDR2IO1_2 */
>> -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
>> -
>> -/* CONTROL_LPDDR2IO1_3 */
>> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
>> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
>> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
>> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
>> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
>> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
>> -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
>> -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
>> -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
>> -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
>> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
>> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
>> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
>> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
>> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
>> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
>> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
>> -
>> -/* CONTROL_LPDDR2IO2_0 */
>> -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
>> -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
>> -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
>> -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
>> -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
>> -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
>> -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
>> -
>> -/* CONTROL_LPDDR2IO2_1 */
>> -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
>> -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
>> -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
>> -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
>> -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
>> -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
>> -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
>> -
>> -/* CONTROL_LPDDR2IO2_2 */
>> -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
>> -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
>> -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
>> -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
>> -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
>> -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
>> -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
>> -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
>> -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
>> -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
>> -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
>> -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
>> -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
>> -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
>> -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
>> -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
>> -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
>> -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
>> -
>> -/* CONTROL_LPDDR2IO2_3 */
>> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
>> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
>> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
>> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
>> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
>> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
>> -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
>> -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
>> -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
>> -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
>> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
>> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
>> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
>> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
>> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
>> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
>> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
>> -
>> -/* CONTROL_BUS_HOLD */
>> -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
>> -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
>> -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
>> -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
>> -
>> -/* CONTROL_C2C */
>> -#define OMAP4_MIRROR_MODE_EN_SHIFT 31
>> -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
>> -#define OMAP4_C2C_SPARE_SHIFT 24
>> -#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
>> -
>> -/* CORE_CONTROL_SPARE_RW */
>> -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
>> -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
>> -
>> -/* CORE_CONTROL_SPARE_R */
>> -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
>> -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
>> -
>> -/* CORE_CONTROL_SPARE_R_C0 */
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
>> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
>> -
>> -/* CONTROL_EFUSE_1 */
>> -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
>> -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
>> -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
>> -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
>> -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
>> -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
>> -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
>> -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
>> -
>> -/* CONTROL_EFUSE_2 */
>> -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
>> -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
>> -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
>> -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
>> -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
>> -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
>> -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
>> -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
>> -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
>> -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
>> -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
>> -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
>> -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
>> -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
>> -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
>> -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
>> -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
>> -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
>> -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
>> -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
>> -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
>> -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
>> -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
>> -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
>> -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
>> -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
>> -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
>> -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
>> -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
>> -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
>> -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
>> -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
>> -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
>> -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
>> -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
>> -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
>> -
>> -/* CONTROL_EFUSE_3 */
>> -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
>> -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
>> -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
>> -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
>> -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
>> -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
>> -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
>> -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
>> -
>> -/* CONTROL_EFUSE_4 */
>> -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
>> -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
>> -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
>> -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
>> -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
>> -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
>> -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
>> -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
>> -
>> -#endif
>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>> deleted file mode 100644
>> index 17c9b37..0000000
>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
>> +++ /dev/null
>> @@ -1,236 +0,0 @@
>> -/*
>> - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
>> - *
>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>> - *
>> - * Benoit Cousson (b-cousson@ti.com)
>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>> - *
>> - * This file is automatically generated from the OMAP hardware databases.
>> - * We respectfully ask that any modifications to this file be coordinated
>> - * with the public linux-omap@vger.kernel.org mailing list and the
>> - * authors above to ensure that the autogeneration scripts are kept
>> - * up-to-date with the file contents.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> - */
>> -
>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
>> -
>> -
>> -/* Base address */
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
>> -
>> -/* Registers offset */
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
>> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
>> -
>> -/* Registers shifts and masks */
>> -
>> -/* IP_REVISION */
>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>> -
>> -/* IP_HWINFO */
>> -#define OMAP4_IP_HWINFO_SHIFT 0
>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>> -
>> -/* IP_SYSCONFIG */
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>> -
>> -/* PADCONF_WAKEUPEVENT_0 */
>> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
>> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
>> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
>> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
>> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
>> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
>> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
>> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
>> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
>> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
>> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
>> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
>> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
>> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
>> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
>> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
>> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
>> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
>> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
>> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
>> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
>> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
>> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
>> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
>> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
>> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
>> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
>> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
>> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
>> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
>> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
>> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
>> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
>> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
>> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
>> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
>> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
>> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
>> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
>> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
>> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
>> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
>> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
>> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
>> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
>> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
>> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
>> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
>> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
>> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
>> -
>> -/* CONTROL_SMART1NOPMIO_PADCONF_0 */
>> -#define OMAP4_FREF_DR0_SC_SHIFT 30
>> -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
>> -#define OMAP4_FREF_DR1_SC_SHIFT 28
>> -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
>> -#define OMAP4_FREF_DR4_SC_SHIFT 26
>> -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
>> -#define OMAP4_FREF_DR5_SC_SHIFT 24
>> -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
>> -#define OMAP4_FREF_DR6_SC_SHIFT 22
>> -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
>> -#define OMAP4_FREF_DR7_SC_SHIFT 20
>> -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
>> -#define OMAP4_GPIO_DR7_SC_SHIFT 18
>> -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
>> -#define OMAP4_DPM_DR0_SC_SHIFT 14
>> -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
>> -#define OMAP4_SIM_DR0_SC_SHIFT 12
>> -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
>> -
>> -/* CONTROL_SMART1NOPMIO_PADCONF_1 */
>> -#define OMAP4_FREF_DR0_LB_SHIFT 30
>> -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
>> -#define OMAP4_FREF_DR1_LB_SHIFT 28
>> -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
>> -#define OMAP4_FREF_DR4_LB_SHIFT 26
>> -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
>> -#define OMAP4_FREF_DR5_LB_SHIFT 24
>> -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
>> -#define OMAP4_FREF_DR6_LB_SHIFT 22
>> -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
>> -#define OMAP4_FREF_DR7_LB_SHIFT 20
>> -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
>> -#define OMAP4_GPIO_DR7_LB_SHIFT 18
>> -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
>> -#define OMAP4_DPM_DR0_LB_SHIFT 14
>> -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
>> -#define OMAP4_SIM_DR0_LB_SHIFT 12
>> -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
>> -
>> -/* CONTROL_PADCONF_MODE */
>> -#define OMAP4_VDDS_DV_FREF_SHIFT 31
>> -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
>> -#define OMAP4_VDDS_DV_BANK2_SHIFT 30
>> -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
>> -
>> -/* CONTROL_XTAL_OSCILLATOR */
>> -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
>> -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
>> -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
>> -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
>> -
>> -/* CONTROL_USIMIO */
>> -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
>> -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
>> -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
>> -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
>> -#define OMAP4_USIM_PWRDNZ_SHIFT 28
>> -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
>> -
>> -/* CONTROL_I2C_2 */
>> -#define OMAP4_SR_SDA_GLFENB_SHIFT 31
>> -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
>> -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
>> -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
>> -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
>> -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
>> -#define OMAP4_SR_SCL_GLFENB_SHIFT 27
>> -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
>> -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
>> -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
>> -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
>> -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
>> -
>> -/* CONTROL_JTAG */
>> -#define OMAP4_JTAG_NTRST_EN_SHIFT 31
>> -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
>> -#define OMAP4_JTAG_TCK_EN_SHIFT 30
>> -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
>> -#define OMAP4_JTAG_RTCK_EN_SHIFT 29
>> -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
>> -#define OMAP4_JTAG_TDI_EN_SHIFT 28
>> -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
>> -#define OMAP4_JTAG_TDO_EN_SHIFT 27
>> -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
>> -
>> -/* CONTROL_SYS */
>> -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
>> -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
>> -
>> -/* WKUP_CONTROL_SPARE_RW */
>> -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
>> -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
>> -
>> -/* WKUP_CONTROL_SPARE_R */
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
>> -
>> -/* WKUP_CONTROL_SPARE_R_C0 */
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
>> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
>> -
>> -#endif
>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>> deleted file mode 100644
>> index a0af9ba..0000000
>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>> +++ /dev/null
>> @@ -1,92 +0,0 @@
>> -/*
>> - * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
>> - *
>> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
>> - *
>> - * Benoit Cousson (b-cousson@ti.com)
>> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
>> - *
>> - * This file is automatically generated from the OMAP hardware databases.
>> - * We respectfully ask that any modifications to this file be coordinated
>> - * with the public linux-omap@vger.kernel.org mailing list and the
>> - * authors above to ensure that the autogeneration scripts are kept
>> - * up-to-date with the file contents.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> - */
>> -
>> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
>> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
>> -
>> -
>> -/* Base address */
>> -#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
>> -
>> -/* Registers offset */
>> -#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
>> -#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
>> -#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
>> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
>> -
>> -/* Registers shifts and masks */
>> -
>> -/* IP_REVISION */
>> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
>> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
>> -#define OMAP4_IP_REV_FUNC_SHIFT 16
>> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
>> -#define OMAP4_IP_REV_RTL_SHIFT 11
>> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
>> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
>> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
>> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
>> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
>> -#define OMAP4_IP_REV_MINOR_SHIFT 0
>> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
>> -
>> -/* IP_HWINFO */
>> -#define OMAP4_IP_HWINFO_SHIFT 0
>> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
>> -
>> -/* IP_SYSCONFIG */
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
>> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
>> -
>> -/* CONF_DEBUG_SEL_TST_0 */
>> -#define OMAP4_WKUP_MODE_SHIFT 0
>> -#define OMAP4_WKUP_MODE_MASK (1 << 0)
>> -
>> -#endif
>> --
>> 1.7.7.6
>>
>>
^ permalink raw reply
* Cpuidle drivers,Suspend : Fix suspend/resume hang with intel_idle driver
From: preeti @ 2012-06-28 9:16 UTC (permalink / raw)
To: Dave Hansen, Linux PM mailing list, linux-pm, linux-acpi,
Rafael .J. Wysocki
Cc: Srivatsa.S.Bhat, Deepthi Dharwar
From: Preeti U Murthy <preeti@linux.vnet.ibm.com>
Dave Hansen reported problems with suspend/resume when used
with intel_idle driver.More such problems were noticed.
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/674075.
The reason for this could not be suspected till he reported
resume hang issue when used with acpi idle driver on his Lenovo-S10-3
Atom netbook.
The patch-[PM / ACPI: Fix suspend/resume regression caused by cpuidle
cleanup],fixed this issue by ensuring that acpi idle drivers prevent
cpus from going into deeper sleep states during suspend to prevent
resume hang on certain bios.
http://marc.info/?l=linux-pm&m=133958534231884&w=2
Commit b04e7bdb984e3b7f62fb7f44146a529f88cc7639
(ACPI: disable lower idle C-states across suspend/resume) throws
light on the resume hang issue on certain specific bios.
Also the following lines in drivers/idle/intel_idle.c suggest intel_idle
drivers should also ensure cpus are prevented from entering idle states
during suspend to avoid a resume hang.
/*
* Known limitations
* [..]
*
* ACPI has a .suspend hack to turn off deep c-states during suspend
* to avoid complications with the lapic timer workaround.
* Have not seen issues with suspend, but may need same workaround here.
*
*/
This patch aims at having this fix in a place common to both the idle
drivers.
Suspend is enabled only if ACPI is active on x86.Thus the setting of
acpi_idle_suspend during suspend is moved up to ACPI specific code with
both acpi and intel idle drivers checking if it is valid to enter deeper
idle states.The setting of acpi_idle_suspend is done via PM_SUSPEND_PREPARE
notifiers to avoid race conditions between processors entering idle states
and the ongoing process of suspend.
The check on acpi_idle_suspend is included in the most appropriate header
so as to be visible to both the idle drivers irrespective of the
different configurations.Even if ACPI is disabled intel idle drivers can
still carry out the acpi_idle_suspend check.
Reported-by: Dave Hansen <dave@linux.vnet.ibm.com>
Reviewed-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Reviewed-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
Signed-off-by: Preeti U Murthy <preeti@linux.vnet.ibm.com>
---
Dave, does this patch ensure suspend/resume works
fine on your netbook if intel_idle driver is enabled?
drivers/acpi/processor_idle.c | 46 +++++++++++++++++++----------------------
drivers/acpi/sleep.c | 38 ++++++++++++++++++++++++++++++++++
drivers/idle/intel_idle.c | 10 +++++++++
include/linux/suspend.h | 24 +++++++++++++++++++++
4 files changed, 93 insertions(+), 25 deletions(-)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index c2ffd84..3ab0963 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -41,7 +41,7 @@
#include <linux/clockchips.h>
#include <linux/cpuidle.h>
#include <linux/irqflags.h>
-
+#include <linux/suspend.h>
/*
* Include the apic definitions for x86 to have the APIC timer related defines
* available also for UP (on SMP it gets magically included via linux/smp.h).
@@ -221,10 +221,6 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
#endif
-/*
- * Suspend / resume control
- */
-static int acpi_idle_suspend;
static u32 saved_bm_rld;
static void acpi_idle_bm_rld_save(void)
@@ -243,21 +239,13 @@ static void acpi_idle_bm_rld_restore(void)
int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
{
- if (acpi_idle_suspend == 1)
- return 0;
-
acpi_idle_bm_rld_save();
- acpi_idle_suspend = 1;
return 0;
}
int acpi_processor_resume(struct acpi_device * device)
{
- if (acpi_idle_suspend == 0)
- return 0;
-
acpi_idle_bm_rld_restore();
- acpi_idle_suspend = 0;
return 0;
}
@@ -762,11 +750,13 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
return -EINVAL;
local_irq_disable();
-
- if (acpi_idle_suspend) {
+ /*
+ * Do not enter idle states if you are in suspend path
+ */
+ if (in_suspend_path()) {
local_irq_enable();
cpu_relax();
- return -EINVAL;
+ return -EBUSY;
}
lapic_timer_state_broadcast(pr, cx, 1);
@@ -838,10 +828,13 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
local_irq_disable();
- if (acpi_idle_suspend) {
+ /*
+ * Do not enter idle states if you are in suspend path
+ */
+ if (in_suspend_path()) {
local_irq_enable();
cpu_relax();
- return -EINVAL;
+ return -EBUSY;
}
if (cx->entry_method != ACPI_CSTATE_FFH) {
@@ -922,12 +915,6 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
if (unlikely(!pr))
return -EINVAL;
- if (acpi_idle_suspend) {
- if (irqs_disabled())
- local_irq_enable();
- cpu_relax();
- return -EINVAL;
- }
if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
if (drv->safe_state_index >= 0) {
@@ -935,13 +922,22 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
drv, drv->safe_state_index);
} else {
local_irq_disable();
- acpi_safe_halt();
+ if (!(in_suspend_path()))
+ acpi_safe_halt();
local_irq_enable();
return -EINVAL;
}
}
local_irq_disable();
+ /*
+ * Do not enter idle states if you are in suspend path
+ */
+ if (in_suspend_path()) {
+ local_irq_enable();
+ cpu_relax();
+ return -EBUSY;
+ }
if (cx->entry_method != ACPI_CSTATE_FFH) {
current_thread_info()->status &= ~TS_POLLING;
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 8856102..4ec77db 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -28,6 +28,11 @@
#include "internal.h"
#include "sleep.h"
+/*
+ * Suspend/Resume control
+ */
+int acpi_idle_suspend;
+
u8 wake_sleep_flags = ACPI_NO_OPTIONAL_METHODS;
static unsigned int gts, bfs;
static int set_param_wake_flag(const char *val, struct kernel_param *kp)
@@ -905,6 +910,36 @@ static void __init acpi_gts_bfs_check(void)
}
}
+/**
+ * cpuidle_pm_callback - On some bios, resume hangs
+ * if idle states are entered during suspend.
+ *
+ * acpi_idle_suspend is used by the x86 idle drivers
+ * to decide whether to go into idle states or not.
+ */
+static int
+cpuidle_pm_callback(struct notifier_block *nb,
+ unsigned long action, void *ptr)
+{
+ switch (action) {
+
+ case PM_SUSPEND_PREPARE:
+ if (acpi_idle_suspend == 0)
+ acpi_idle_suspend = 1;
+ break;
+
+ case PM_POST_SUSPEND:
+ if (acpi_idle_suspend == 1)
+ acpi_idle_suspend = 0;
+ break;
+
+ default:
+ return NOTIFY_DONE;
+ }
+
+ return NOTIFY_OK;
+}
+
int __init acpi_sleep_init(void)
{
acpi_status status;
@@ -932,6 +967,9 @@ int __init acpi_sleep_init(void)
suspend_set_ops(old_suspend_ordering ?
&acpi_suspend_ops_old : &acpi_suspend_ops);
+
+ pm_notifier(cpuidle_pm_callback, 0);
+
#endif
#ifdef CONFIG_HIBERNATION
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index d0f59c3..a595207 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -65,6 +65,7 @@
#include <asm/cpu_device_id.h>
#include <asm/mwait.h>
#include <asm/msr.h>
+#include <linux/suspend.h>
#define INTEL_IDLE_VERSION "0.4"
#define PREFIX "intel_idle: "
@@ -255,6 +256,15 @@ static int intel_idle(struct cpuidle_device *dev,
cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
/*
+ * Do not enter idle states if you are in suspend path
+ */
+ if (in_suspend_path()) {
+ local_irq_enable();
+ cpu_relax();
+ return -EBUSY;
+ }
+
+ /*
* leave_mm() to avoid costly and often unnecessary wakeups
* for flushing the user TLB's associated with the active mm.
*/
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 0c808d7..eb96670 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -38,6 +38,30 @@ typedef int __bitwise suspend_state_t;
#define PM_SUSPEND_MEM ((__force suspend_state_t) 3)
#define PM_SUSPEND_MAX ((__force suspend_state_t) 4)
+extern int acpi_idle_suspend;
+
+/**
+ * in_suspend_path - X86 idle drivers make a call
+ * to this function before entering idle states.
+ *
+ * Entering idle states is prevented if it is in suspend
+ * path.
+ */
+#ifdef CONFIG_ACPI
+static inline int in_suspend_path(void)
+{
+ if (acpi_idle_suspend == 1)
+ return 1;
+ else
+ return 0;
+}
+#else
+static inline int in_suspend_path(void)
+{
+ return 0;
+}
+#endif
+
enum suspend_stat_step {
SUSPEND_FREEZE = 1,
SUSPEND_PREPARE,
Regards,
Preeti U Murthy
^ permalink raw reply related
* [PATCH v2] acpi: intel_idle : break dependency between modules
From: Daniel Lezcano @ 2012-06-28 8:46 UTC (permalink / raw)
To: trenn
Cc: linaro-dev, linux-pm, x86, linux-kernel, linux-acpi,
srivatsa.bhat, linux-pm
In-Reply-To: <201206271506.29034.trenn@suse.de>
When the system is booted with some cpus offline, the idle
driver is not initialized. When a cpu is set online, the
acpi code call the intel idle init function. Unfortunately
this code introduce a dependency between intel_idle and acpi.
This patch is intended to remove this dependency by using the
notifier of intel_idle. This patch has the benefit of
encapsulating the intel_idle driver and remove some exported
functions.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/acpi/processor_driver.c | 7 ------
drivers/idle/intel_idle.c | 41 +++++++++++++++++++++++++-------------
include/linux/cpuidle.h | 7 ------
3 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index 0734086..8648b29 100644
--- a/drivers/acpi/processor_driver.c
+++ b/drivers/acpi/processor_driver.c
@@ -427,18 +427,11 @@ static int acpi_cpu_soft_notify(struct notifier_block *nfb,
* Initialize missing things
*/
if (pr->flags.need_hotplug_init) {
- struct cpuidle_driver *idle_driver =
- cpuidle_get_driver();
-
printk(KERN_INFO "Will online and init hotplugged "
"CPU: %d\n", pr->id);
WARN(acpi_processor_start(pr), "Failed to start CPU:"
" %d\n", pr->id);
pr->flags.need_hotplug_init = 0;
- if (idle_driver && !strcmp(idle_driver->name,
- "intel_idle")) {
- intel_idle_cpu_init(pr->id);
- }
/* Normal CPU soft online event */
} else {
acpi_processor_ppc_has_changed(pr, 0);
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index d0f59c3..fe95d54 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -96,6 +96,7 @@ static const struct idle_cpu *icpu;
static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
static int intel_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
+static int intel_idle_cpu_init(int cpu);
static struct cpuidle_state *cpuidle_state_table;
@@ -302,22 +303,35 @@ static void __setup_broadcast_timer(void *arg)
clockevents_notify(reason, &cpu);
}
-static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
- unsigned long action, void *hcpu)
+static int cpu_hotplug_notify(struct notifier_block *n,
+ unsigned long action, void *hcpu)
{
int hotcpu = (unsigned long)hcpu;
+ struct cpuidle_device *dev;
switch (action & 0xf) {
case CPU_ONLINE:
- smp_call_function_single(hotcpu, __setup_broadcast_timer,
- (void *)true, 1);
+
+ if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
+ smp_call_function_single(hotcpu, __setup_broadcast_timer,
+ (void *)true, 1);
+
+ /*
+ * Some systems can hotplug a cpu at runtime after
+ * the kernel has booted, we have to initialize the
+ * driver in this case
+ */
+ dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
+ if (!dev->registered)
+ intel_idle_cpu_init(hotcpu);
+
break;
}
return NOTIFY_OK;
}
-static struct notifier_block setup_broadcast_notifier = {
- .notifier_call = setup_broadcast_cpuhp_notify,
+static struct notifier_block cpu_hotplug_notifier = {
+ .notifier_call = cpu_hotplug_notify,
};
static void auto_demotion_disable(void *dummy)
@@ -405,10 +419,10 @@ static int intel_idle_probe(void)
if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
- else {
+ else
on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
- register_cpu_notifier(&setup_broadcast_notifier);
- }
+
+ register_cpu_notifier(&cpu_hotplug_notifier);
pr_debug(PREFIX "v" INTEL_IDLE_VERSION
" model 0x%X\n", boot_cpu_data.x86_model);
@@ -494,7 +508,7 @@ static int intel_idle_cpuidle_driver_init(void)
* allocate, initialize, register cpuidle_devices
* @cpu: cpu/core to initialize
*/
-int intel_idle_cpu_init(int cpu)
+static int intel_idle_cpu_init(int cpu)
{
int cstate;
struct cpuidle_device *dev;
@@ -539,7 +553,6 @@ int intel_idle_cpu_init(int cpu)
return 0;
}
-EXPORT_SYMBOL_GPL(intel_idle_cpu_init);
static int __init intel_idle_init(void)
{
@@ -581,10 +594,10 @@ static void __exit intel_idle_exit(void)
intel_idle_cpuidle_devices_uninit();
cpuidle_unregister_driver(&intel_idle_driver);
- if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
+
+ if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
- unregister_cpu_notifier(&setup_broadcast_notifier);
- }
+ unregister_cpu_notifier(&cpu_hotplug_notifier);
return;
}
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 5ab7183..66d7e0d 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -213,14 +213,7 @@ struct cpuidle_governor {
extern int cpuidle_register_governor(struct cpuidle_governor *gov);
extern void cpuidle_unregister_governor(struct cpuidle_governor *gov);
-#ifdef CONFIG_INTEL_IDLE
-extern int intel_idle_cpu_init(int cpu);
#else
-static inline int intel_idle_cpu_init(int cpu) { return -1; }
-#endif
-
-#else
-static inline int intel_idle_cpu_init(int cpu) { return -1; }
static inline int cpuidle_register_governor(struct cpuidle_governor *gov)
{return 0;}
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH] acpi: intel_idle : break dependency between modules
From: Daniel Lezcano @ 2012-06-28 8:03 UTC (permalink / raw)
To: Thomas Renninger
Cc: deepthi-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
linaro-dev-cunTk1MwBs8s++Sfvej+rw,
linux-pm-u79uwXL29TY76Z2rM5mHXA, x86-DgEjT+Ai2ygdnm+yROfE0A,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, rjw-KKrjLPT3xs0,
linux-acpi-u79uwXL29TY76Z2rM5mHXA,
srivatsa.bhat-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8,
linux-pm-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
lenb-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <201206271506.29034.trenn-l3A5Bk7waGM@public.gmane.org>
On 06/27/2012 03:06 PM, Thomas Renninger wrote:
> Hi,
>
> I agree that such a dependency between 2 modules is not
> nice. But your patch will have bad side-effects (see comments
> embedded below).
>
> On Wednesday, June 27, 2012 11:07:48 AM Daniel Lezcano wrote:
>> When the system is booted with some cpus offline, the idle
>> driver is not initialized. When a cpu is set online, the
>> acpi code call the intel idle init function. Unfortunately
>> this code introduce a dependency between intel_idle and acpi.
>>
>> This patch is intended to remove this dependency by using the
>> notifier of intel_idle. In order to make it work, the notifier
>> must be initialized in the right order, acpi then intel_idle.
>> This is done in the Makefile. This patch has the benefit of
>> encapsulating the intel_idle driver and remove some exported
>> functions.
>>
>> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>> ---
>> drivers/Makefile | 3 ++-
>> drivers/acpi/processor_driver.c | 7 -------
>> drivers/idle/intel_idle.c | 22 ++++++++++++++--------
>> include/linux/cpuidle.h | 7 -------
>> 4 files changed, 16 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index 2ba29ff..a2454b8 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -12,8 +12,9 @@ obj-$(CONFIG_PCI) += pci/
>> obj-$(CONFIG_PARISC) += parisc/
>> obj-$(CONFIG_RAPIDIO) += rapidio/
>> obj-y += video/
>> -obj-y += idle/
>> +# acpi must come before idle for initialization
>> obj-$(CONFIG_ACPI) += acpi/
>> +obj-y += idle/
> This breaks intel_idle.
> Loading order defines which one comes first and is used: intel_idle
> or ACPI processor cpuidle driver.
> With above, one would get acpi_idle cpuidle driver if both are
> compiled in, instead of the intel_idle one.
>
> Why exactly is this necessary, couldn't it just work?
[...]
I just wanted to keep same order. If it is not necessary, I won't invert
the compilation order in the next patch.
>> -static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
>> - unsigned long action, void *hcpu)
>> +static int cpu_hotplug_notify(struct notifier_block *n,
>> + unsigned long action, void *hcpu)
>> {
>> int hotcpu = (unsigned long)hcpu;
>> + struct cpuidle_device *dev;
>>
>> switch (action & 0xf) {
>> case CPU_ONLINE:
>> smp_call_function_single(hotcpu, __setup_broadcast_timer,
>> (void *)true, 1);
>> +
>> + dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
>> + if (!dev->registered)
>> + intel_idle_cpu_init(hotcpu);
>> +
> A small comment why this can happen and needs to be done
> (real hotplugged cpu case) might help here later.
Yes, that makes sense.
[...]
>> static void auto_demotion_disable(void *dummy)
>> @@ -407,7 +414,7 @@ static int intel_idle_probe(void)
>> lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
>> else {
>> on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
>> - register_cpu_notifier(&setup_broadcast_notifier);
>> + register_cpu_notifier(&cpu_hotplug_notifier);
>
> The notifier always has to be registered now, not only in:
> if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
> case.
Oops, right.
>> pr_debug(PREFIX "v" INTEL_IDLE_VERSION
>> @@ -494,7 +501,7 @@ static int intel_idle_cpuidle_driver_init(void)
>> * allocate, initialize, register cpuidle_devices
>> * @cpu: cpu/core to initialize
>> */
>> -int intel_idle_cpu_init(int cpu)
>> +static int intel_idle_cpu_init(int cpu)
>> {
>> int cstate;
>> struct cpuidle_device *dev;
>> @@ -539,7 +546,6 @@ int intel_idle_cpu_init(int cpu)
>>
>> return 0;
>> }
>> -EXPORT_SYMBOL_GPL(intel_idle_cpu_init);
>>
>> static int __init intel_idle_init(void)
>> {
>> @@ -583,7 +589,7 @@ static void __exit intel_idle_exit(void)
>>
>> if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
>> on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
>> - unregister_cpu_notifier(&setup_broadcast_notifier);
>> + unregister_cpu_notifier(&cpu_hotplug_notifier);
> Same.
Thanks for the review !
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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^ permalink raw reply
* Re: [linux-pm] [PATCH] acpi: intel_idle : break dependency between modules
From: Thomas Renninger @ 2012-06-28 7:34 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: Daniel Lezcano, linaro-dev, linux-pm, x86, linux-kernel,
linux-acpi, linux-pm
In-Reply-To: <4FEB31E1.2030209@linux.vnet.ibm.com>
On Wednesday, June 27, 2012 06:16:33 PM Srivatsa S. Bhat wrote:
> On 06/27/2012 02:37 PM, Daniel Lezcano wrote:
> > When the system is booted with some cpus offline, the idle
> > driver is not initialized. When a cpu is set online, the
> > acpi code call the intel idle init function. Unfortunately
> > this code introduce a dependency between intel_idle and acpi.
> >
> > This patch is intended to remove this dependency by using the
> > notifier of intel_idle. In order to make it work, the notifier
> > must be initialized in the right order, acpi then intel_idle.
> > This is done in the Makefile.
>
> There is a much better way of doing this. See below.
>
> > This patch has the benefit of
> > encapsulating the intel_idle driver and remove some exported
> > functions.
> >
>
> Nice :)
>
> > Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> > ---
> > drivers/Makefile | 3 ++-
> > drivers/acpi/processor_driver.c | 7 -------
> > drivers/idle/intel_idle.c | 22 ++++++++++++++--------
> > include/linux/cpuidle.h | 7 -------
> > 4 files changed, 16 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index 2ba29ff..a2454b8 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -12,8 +12,9 @@ obj-$(CONFIG_PCI) += pci/
> > obj-$(CONFIG_PARISC) += parisc/
> > obj-$(CONFIG_RAPIDIO) += rapidio/
> > obj-y += video/
> > -obj-y += idle/
> > +# acpi must come before idle for initialization
> > obj-$(CONFIG_ACPI) += acpi/
> > +obj-y += idle/
> > obj-$(CONFIG_SFI) += sfi/
> > # PnP must come after ACPI since it will eventually need to check if acpi
> > # was used and do nothing if so
>
> OK, so all you are trying to do here is ensure that the intel idle related
> notifier runs _after_ the acpi related one.
I might oversee something, if you have concerns, please point me to it.
If it's all about keeping the order of excuting these functions:
acpi_processor_start(pr)
and
intel_idle_cpu_init()
There should be no need for it. Intel idle is pretty separated.
Thomas
^ permalink raw reply
* Re: [PATCH v3 3/7] OMAP2+: use control module mfd driver in omap_type
From: Tony Lindgren @ 2012-06-28 6:32 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: amit.kucheria, kishon, balbi, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B4A.1040204@dev.rtsoft.ru>
Hi,
* Konstantin Baydarov <kbaidarov@dev.rtsoft.ru> [120627 11:09]:
> OMAP system control module can be probed early, then
> omap_type is safe to use its APIs.
>
> TODO: add support for other omap versions
>
> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
> ---
> arch/arm/mach-omap2/id.c | 9 +++++----
> 1 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 00486a8..1b0cec8 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -18,6 +18,7 @@
> #include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/io.h>
> +#include <linux/mfd/omap_control.h>
>
> #include <asm/cputype.h>
>
> @@ -43,13 +44,13 @@ int omap_type(void)
> u32 val = 0;
>
> if (cpu_is_omap24xx()) {
> - val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
> + val = omap_control_status_read(OMAP24XX_CONTROL_STATUS);
> } else if (cpu_is_am33xx()) {
> - val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
> + val = omap_control_status_read(AM33XX_CONTROL_STATUS);
> } else if (cpu_is_omap34xx()) {
> - val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> + val = omap_control_status_read(OMAP343X_CONTROL_STATUS);
> } else if (cpu_is_omap44xx()) {
> - val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> + val = omap_control_status_read(OMAP4_CTRL_MODULE_CORE_STATUS);
> } else {
> pr_err("Cannot detect omap type!\n");
> goto out;
I think you should keep the CONTROL_STATUS defines private to the
SCM core driver, there should be no need to pass it here. Just
make it int omap_control_status_read(void).
Of course that means that the SCM core is initialized to some extent
to know where to find the CONTROL_STATUS register. That should
probably be done as part of the set_globals calls done in init_early
in mach-omap2/io.c file.
Regards,
Tony
^ permalink raw reply
* Re: [PATCH v3 0/7] OMAP System Control Module
From: Valentin, Eduardo @ 2012-06-28 6:29 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
In-Reply-To: <20120628044343.GA2471@besouro>
Hello Konstantin,
On Thu, Jun 28, 2012 at 7:43 AM, Eduardo Valentin
<eduardo.valentin@ti.com> wrote:
> Hello,
>
> On Wed, Jun 27, 2012 at 10:04:32PM +0400, Konstantin Baydarov wrote:
>> Hello.
>>
>> This is a next version of series of patches(based on Eduardo Valentin's patch set) adding a basic support for system control module, on OMAP4+ context. It is a working in progress.
>>
>> Main changes since previous patch set version:
>> - Bandgap and usb phy: drivers are now independent from control module driver, they use their own functions to acess scm registers.
>
> Well, I believe the idea of having them with their own io resource was to avoid
> children drivers accessing each other io areas. Is this now working?
>
>> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
>> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
>> Probably, no configuration option is required!
>
> Why is this? I suppose the idea is to have the arch config selecting that flag.
>
>> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
>
> Is this going to be reserved as well? if yes, how children are going to have
> their own access functions?
>
>> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
>> module device.
>> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
>
> fine, assuming the io split works...
>
>> - omap-control-core: added omap_control_status_read that is used early in omap_type
>> - Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
>> - Bandgap: Check the type of bandgap dynamically in bandgap driver probe function by reading
>> omap core control module revision register CONTROL_GEN_CORE_REVISION.
>
> this has some issue... I will post comment on the patch
>
>> - Bandgap and usb phy: Parent SCM platform device IOMEM resources is used to get the base address of SCM window.
>
> Ohh.. Then what is the point of having them using their own io access functions,
> nothing is again protected as you have only 1 io resource which is shared.
> And now is even worse because you have several io access function..
> I think this is moving backwards.
>
>> - Bandgap masks defines were moved to drivers/thermal/omap-bandgap.c.
>>
>> TODO list for bandgap driver:
>> - Reserve omap-control-core IOMEM window.
>> - Improve thermal zone definition for OMAP4
>> - Introduce the thermal zones for OMAP5
>
> Based on the review comments on RFC patch series, there are more
> things to be done.
>
> I have the O4 and O5 zone definition ready. But that work depends
> on generic CPU cooling patches. I have also looked the driver support
> for 4430. But the probing and io resource split is still based on
> previous design. I have also a patch which does the remapping in the
> bandgap driver. But really, for this to work it would require to have
> several entries in the reg property. And that is going to change from
> BG version to BG version.
>
> I can prepare some patches for this.
You can find the updated patches here:
git@gitorious.org:thermal-framework/thermal-framework.git
thermal_work/omap/bandgap_clean
But, as I said they are based on the generic cpu cooling. And the zone
registration follows the API as in linux-next.
--
Eduardo Valentin
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^ permalink raw reply
* Re: [PATCH v3 6/7] omap4: thermal: add basic CPU thermal zone
From: Eduardo Valentin @ 2012-06-28 5:24 UTC (permalink / raw)
To: R, Durgadoss
Cc: Konstantin Baydarov, amit.kucheria@linaro.org, kishon@ti.com,
balbi@ti.com, linux-pm@lists.linux-foundation.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <4D68720C2E767A4AA6A8796D42C8EB59149DB0@BGSMSX101.gar.corp.intel.com>
Hello Durga,
On Thu, Jun 28, 2012 at 05:16:43AM +0000, R, Durgadoss wrote:
> Hi,
>
> > > +
> > > + data = devm_kzalloc(bg_ptr->dev, sizeof(*data), GFP_KERNEL);
> > > + if (!data) {
> > > + dev_err(bg_ptr->dev, "kzalloc fail\n");
> > > + return -ENOMEM;
> > > + }
> > > + data->sensor_id = id;
> > > + data->bg_ptr = bg_ptr;
> > > + data->omap4_thermal = thermal_zone_device_register(domain, 0,
> > > + data, &omap4_thermal_ops, 0, 0, 0, 0);
>
> Please watch out for changes on this API.
> The third argument is the flag for writeable trip points.
> This patch is in linux-next. So, kindly have a look at this API
> implementation in thermal_sys.c in linux-next, when you submit this patch
> next time.
Ok. Thanks for the heads up. I will have a look on linux-next.
>
> Thanks,
> Durga
^ permalink raw reply
* Re: [PATCH v3 6/7] omap4: thermal: add basic CPU thermal zone
From: R, Durgadoss @ 2012-06-28 5:16 UTC (permalink / raw)
To: eduardo.valentin@ti.com, Konstantin Baydarov
Cc: amit.kucheria@linaro.org, kishon@ti.com, balbi@ti.com,
linux-pm@lists.linux-foundation.org, linux-omap@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20120628051207.GF2471@besouro>
Hi,
> > +
> > + data = devm_kzalloc(bg_ptr->dev, sizeof(*data), GFP_KERNEL);
> > + if (!data) {
> > + dev_err(bg_ptr->dev, "kzalloc fail\n");
> > + return -ENOMEM;
> > + }
> > + data->sensor_id = id;
> > + data->bg_ptr = bg_ptr;
> > + data->omap4_thermal = thermal_zone_device_register(domain, 0,
> > + data, &omap4_thermal_ops, 0, 0, 0, 0);
Please watch out for changes on this API.
The third argument is the flag for writeable trip points.
This patch is in linux-next. So, kindly have a look at this API
implementation in thermal_sys.c in linux-next, when you submit this patch
next time.
Thanks,
Durga
^ permalink raw reply
* Re: [PATCH v3 6/7] omap4: thermal: add basic CPU thermal zone
From: Eduardo Valentin @ 2012-06-28 5:12 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B57.6030109@dev.rtsoft.ru>
On Wed, Jun 27, 2012 at 10:05:11PM +0400, Konstantin Baydarov wrote:
> omap4: thermal: add basic CPU thermal zone
>
> This patch exposes OMAP4 thermal sensor as a thermal zone
> named "cpu". Only thermal creation is done here.
>
> TODO:
>
> - Add cooling bindings
> - Add extrapolation rules
>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
You change the authorship and don't sign?
Anyway, this one has a lot to evolve still. I will send to you an improved version
of the BG driver.
> ---
> drivers/thermal/Kconfig | 12 ++++++
> drivers/thermal/Makefile | 1 +
> drivers/thermal/omap-bandgap.c | 1 +
> drivers/thermal/omap-bandgap.h | 12 ++++++
> drivers/thermal/omap4-thermal.c | 72 +++++++++++++++++++++++++++++++++++++++
> 5 files changed, 98 insertions(+), 0 deletions(-)
> create mode 100644 drivers/thermal/omap4-thermal.c
>
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index f9989e8..7d44b5c 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -38,3 +38,15 @@ config OMAP_BANDGAP
> This includes alert interrupts generation and also the TSHUT
> support.
>
> +config OMAP4_THERMAL
> + bool "Texas Instruments OMAP4 thermal support"
> + depends on OMAP_BANDGAP
> + depends on ARCH_OMAP4
> + help
> + If you say yes here you get thermal support for the Texas Instruments
> + OMAP4 SoC family. The current chip supported are:
> + - OMAP4460
> +
> + This includes alert interrupts generation and also the TSHUT
> + support.
> +
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index 5ff1af1..6397678 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_THERMAL) += thermal_sys.o
> obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o
> obj-$(CONFIG_OMAP_BANDGAP) += omap-thermal.o
> omap-thermal-y := omap-bandgap.o
> +omap-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal.o
> diff --git a/drivers/thermal/omap-bandgap.c b/drivers/thermal/omap-bandgap.c
> index c68fa1a..c80d879 100644
> --- a/drivers/thermal/omap-bandgap.c
> +++ b/drivers/thermal/omap-bandgap.c
> @@ -1328,6 +1328,7 @@ static const struct omap_bandgap_data omap4460_data = {
> .fclock_name = "bandgap_ts_fclk",
> .div_ck_name = "div_ts_ck",
> .conv_table = omap4460_adc_to_temp,
> + .expose_sensor = omap4_thermal_expose_sensor,
> .irq = 126,
> .sensors = {
> {
> diff --git a/drivers/thermal/omap-bandgap.h b/drivers/thermal/omap-bandgap.h
> index 41f25ff..3f4c192 100644
> --- a/drivers/thermal/omap-bandgap.h
> +++ b/drivers/thermal/omap-bandgap.h
> @@ -61,4 +61,16 @@ int omap_bandgap_write_update_interval(struct omap_bandgap *bg_ptr, int id,
> int omap_bandgap_read_temperature(struct omap_bandgap *bg_ptr, int id,
> int *temperature);
>
> +#ifdef CONFIG_OMAP4_THERMAL
> +int omap4_thermal_expose_sensor(struct omap_bandgap *bg_ptr, int id,
> + char *domain);
> +#else
> +static inline int omap4_thermal_expose_sensor(struct omap_bandgap *bg_ptr,
> + int id, char *domain)
> +{
> + return 0;
> +}
> +
> +#endif
> +
> #endif
> diff --git a/drivers/thermal/omap4-thermal.c b/drivers/thermal/omap4-thermal.c
> new file mode 100644
> index 0000000..fb11753
> --- /dev/null
> +++ b/drivers/thermal/omap4-thermal.c
> @@ -0,0 +1,72 @@
> +/*
> + * SPEAr thermal driver.
> + *
> + * Copyright (C) 2011-2012 Texas Instruments Inc.
> + * Contact:
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/thermal.h>
> +
> +#include "omap-bandgap.h"
> +
> +struct omap4_thermal_data {
> + struct thermal_zone_device *omap4_thermal;
> + struct omap_bandgap *bg_ptr;
> + int sensor_id;
> +};
> +
> +static inline int omap4_thermal_get_temp(struct thermal_zone_device *thermal,
> + unsigned long *temp)
> +{
> + struct omap4_thermal_data *data = thermal->devdata;
> + int ret, tmp;
> +
> + ret = omap_bandgap_read_temperature(data->bg_ptr, data->sensor_id,
> + &tmp);
> + if (!ret)
> + *temp = tmp;
> +
> + return ret;
> +}
> +
> +static struct thermal_zone_device_ops omap4_thermal_ops = {
> + .get_temp = omap4_thermal_get_temp,
> +};
> +
> +int omap4_thermal_expose_sensor(struct omap_bandgap *bg_ptr, int id,
> + char *domain)
> +{
> + struct omap4_thermal_data *data;
> +
> + data = devm_kzalloc(bg_ptr->dev, sizeof(*data), GFP_KERNEL);
> + if (!data) {
> + dev_err(bg_ptr->dev, "kzalloc fail\n");
> + return -ENOMEM;
> + }
> + data->sensor_id = id;
> + data->bg_ptr = bg_ptr;
> + data->omap4_thermal = thermal_zone_device_register(domain, 0,
> + data, &omap4_thermal_ops, 0, 0, 0, 0);
> + if (IS_ERR(data->omap4_thermal)) {
> + dev_err(bg_ptr->dev, "thermal zone device is NULL\n");
> + return PTR_ERR(data->omap4_thermal);
> + }
> +
> + return 0;
> +}
> --
> 1.7.7.6
>
>
^ permalink raw reply
* Re: [PATCH v3 5/7] ARM: OMAP4+: thermal: introduce bandgap temperature sensor
From: Eduardo Valentin @ 2012-06-28 5:09 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: b-cousson, kishon, santosh.shilimkar, tony, paul, balbi,
amit.kucheria, linux-pm, linux-arm-kernel, linux-omap,
amit.kachhap, Eduardo Valentin
In-Reply-To: <4FEB4B4F.9040709@dev.rtsoft.ru>
Hello,
On Wed, Jun 27, 2012 at 10:05:03PM +0400, Konstantin Baydarov wrote:
> In the System Control Module, OMAP supplies a voltage reference
> and a temperature sensor feature that are gathered in the band
> gap voltage and temperature sensor (VBGAPTS) module. The band
> gap provides current and voltage reference for its internal
> circuits and other analog IP blocks. The analog-to-digital
> converter (ADC) produces an output value that is proportional
> to the silicon temperature.
>
> This patch provides a platform driver which expose this feature.
> It is moduled as a MFD child of the System Control Module core
> MFD driver.
>
> This driver provides only APIs to access the device properties,
> like temperature, thresholds and update rate.
>
> Changes since previous version:
> - Bandgap and usb phy: drivers are now independent from control module driver,
> they use their own API functions.
> - Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
> - Bandgap: Check the type of bandgap dynamically in bandgap driver probe
> function by reading
> omap core control module revision register CONTROL_GEN_CORE_REVISION.
> - Parent SCM platform device IOMEM resources is used to get the base address
> of SCM window.
Same comment on USB-phy applies here. What do we gain by reusing same ioresource
from parent on all children for ioremapping?
> - SCM Dependency was removed from Kconfig.
> - Bandgap masks defines were moved to drivers/thermal/omap-bandgap.c.
>
> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> ---
> .../devicetree/bindings/thermal/omap_bandgap.txt | 27 +
> drivers/thermal/Kconfig | 12 +
> drivers/thermal/Makefile | 4 +-
> drivers/thermal/omap-bandgap.c | 1773 ++++++++++++++++++++
> drivers/thermal/omap-bandgap.h | 64 +
> 5 files changed, 1879 insertions(+), 1 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/thermal/omap_bandgap.txt
> create mode 100644 drivers/thermal/omap-bandgap.c
> create mode 100644 drivers/thermal/omap-bandgap.h
>
> diff --git a/Documentation/devicetree/bindings/thermal/omap_bandgap.txt b/Documentation/devicetree/bindings/thermal/omap_bandgap.txt
> new file mode 100644
> index 0000000..430bcf8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/omap_bandgap.txt
> @@ -0,0 +1,27 @@
> +* Texas Instrument OMAP SCM bandgap bindings
> +
> +In the System Control Module, OMAP supplies a voltage reference
> +and a temperature sensor feature that are gathered in the band
> +gap voltage and temperature sensor (VBGAPTS) module. The band
> +gap provides current and voltage reference for its internal
> +circuits and other analog IP blocks. The analog-to-digital
> +converter (ADC) produces an output value that is proportional
> +to the silicon temperature.
> +
> +Required properties:
> +- compatible : Should be:
> + - "ti,omap4460-control-bandgap" : for OMAP4460 bandgap
> + - "ti,omap5430-control-bandgap" : for OMAP5430 bandgap
Please update documentation.
> +- interrupts : this entry should indicate which interrupt line
> +the talert signal is routed to;
> +Specific:
> +- ti,tshut-gpio : this entry should be used to inform which GPIO
> +line the tshut signal is routed to;
> +
> +Example:
> +
> +bandgap {
> + compatible = "ti,omap4460-control-bandgap";
> + interrupts = <0 126 4>; /* talert */
> + ti,tshut-gpio = <86>;
> +};
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 514a691..f9989e8 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -26,3 +26,15 @@ config SPEAR_THERMAL
> help
> Enable this to plug the SPEAr thermal sensor driver into the Linux
> thermal framework
> +
> +config OMAP_BANDGAP
> + tristate "Texas Instruments OMAP4+ temperature sensor driver"
> + depends on THERMAL
> + help
> + If you say yes here you get support for the Texas Instruments
> + OMAP4460+ on die bandgap temperature sensor support. The register
> + set is part of system control module.
> +
> + This includes alert interrupts generation and also the TSHUT
> + support.
> +
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index a9fff0b..5ff1af1 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -3,4 +3,6 @@
> #
>
> obj-$(CONFIG_THERMAL) += thermal_sys.o
> -obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o
> \ No newline at end of file
> +obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o
> +obj-$(CONFIG_OMAP_BANDGAP) += omap-thermal.o
> +omap-thermal-y := omap-bandgap.o
> diff --git a/drivers/thermal/omap-bandgap.c b/drivers/thermal/omap-bandgap.c
> new file mode 100644
> index 0000000..c68fa1a
> --- /dev/null
> +++ b/drivers/thermal/omap-bandgap.c
> @@ -0,0 +1,1773 @@
> +/*
> + * OMAP4 Bandgap temperature sensor driver
> + *
> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Author: J Keerthy <j-keerthy@ti.com>
> + * Author: Moiz Sonasath <m-sonasath@ti.com>
> + * Couple of fixes, DT and MFD adaptation:
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> + * 02110-1301 USA
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/export.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/clk.h>
> +#include <linux/gpio.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/types.h>
> +#include <linux/mutex.h>
> +#include <linux/reboot.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_irq.h>
> +
> +#include "omap-bandgap.h"
> +
> +/* Offsets from the base of temperature sensor registers */
> +
> +#define OMAP4460_TEMP_SENSOR_CTRL_OFFSET 0x32C
> +#define OMAP4460_BGAP_CTRL_OFFSET 0x378
> +#define OMAP4460_BGAP_COUNTER_OFFSET 0x37C
> +#define OMAP4460_BGAP_THRESHOLD_OFFSET 0x380
> +#define OMAP4460_BGAP_TSHUT_OFFSET 0x384
> +#define OMAP4460_BGAP_STATUS_OFFSET 0x388
> +#define OMAP4460_FUSE_OPP_BGAP 0x260
> +
> +#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x32C
> +#define OMAP5430_BGAP_CTRL_OFFSET 0x380
> +#define OMAP5430_BGAP_COUNTER_MPU_OFFSET 0x39C
> +#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x384
> +#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x390
> +#define OMAP5430_BGAP_STATUS_OFFSET 0x3A8
> +#define OMAP5430_FUSE_OPP_BGAP_MPU 0x1E4
> +
> +#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x330
> +#define OMAP5430_BGAP_COUNTER_GPU_OFFSET 0x3A0
> +#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x388
> +#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x394
> +#define OMAP5430_FUSE_OPP_BGAP_GPU 0x1E0
> +
> +#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x334
> +#define OMAP5430_BGAP_COUNTER_CORE_OFFSET 0x3A4
> +#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x38C
> +#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x398
> +#define OMAP5430_FUSE_OPP_BGAP_CORE 0x1E8
> +
> +#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
> +#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
> +#define OMAP4460_T_HOT 800 /* 73 deg C */
> +#define OMAP4460_T_COLD 795 /* 71 deg C */
> +#define OMAP4460_MAX_FREQ 1500000
> +#define OMAP4460_MIN_FREQ 1000000
> +#define OMAP4460_MIN_TEMP -40000
> +#define OMAP4460_MAX_TEMP 123000
> +#define OMAP4460_HYST_VAL 5000
> +#define OMAP4460_ADC_START_VALUE 530
> +#define OMAP4460_ADC_END_VALUE 932
> +
> +#define OMAP5430_MPU_TSHUT_HOT 915
> +#define OMAP5430_MPU_TSHUT_COLD 900
> +#define OMAP5430_MPU_T_HOT 800
> +#define OMAP5430_MPU_T_COLD 795
> +#define OMAP5430_MPU_MAX_FREQ 1500000
> +#define OMAP5430_MPU_MIN_FREQ 1000000
> +#define OMAP5430_MPU_MIN_TEMP -40000
> +#define OMAP5430_MPU_MAX_TEMP 125000
> +#define OMAP5430_MPU_HYST_VAL 5000
> +#define OMAP5430_ADC_START_VALUE 532
> +#define OMAP5430_ADC_END_VALUE 934
> +
> +#define OMAP5430_GPU_TSHUT_HOT 915
> +#define OMAP5430_GPU_TSHUT_COLD 900
> +#define OMAP5430_GPU_T_HOT 800
> +#define OMAP5430_GPU_T_COLD 795
> +#define OMAP5430_GPU_MAX_FREQ 1500000
> +#define OMAP5430_GPU_MIN_FREQ 1000000
> +#define OMAP5430_GPU_MIN_TEMP -40000
> +#define OMAP5430_GPU_MAX_TEMP 125000
> +#define OMAP5430_GPU_HYST_VAL 5000
> +
> +#define OMAP5430_CORE_TSHUT_HOT 915
> +#define OMAP5430_CORE_TSHUT_COLD 900
> +#define OMAP5430_CORE_T_HOT 800
> +#define OMAP5430_CORE_T_COLD 795
> +#define OMAP5430_CORE_MAX_FREQ 1500000
> +#define OMAP5430_CORE_MIN_FREQ 1000000
> +#define OMAP5430_CORE_MIN_TEMP -40000
> +#define OMAP5430_CORE_MAX_TEMP 125000
> +#define OMAP5430_CORE_HYST_VAL 5000
> +
> +/* TEMP_SENSOR OMAP4430 */
> +#define OMAP4430_BGAP_TEMPSOFF_SHIFT 12
> +#define OMAP4430_BGAP_TEMPSOFF_MASK (1 << 12)
> +#define OMAP4430_BGAP_TSHUT_SHIFT 11
> +#define OMAP4430_BGAP_TSHUT_MASK (1 << 11)
> +#define OMAP4430_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
> +#define OMAP4430_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
> +#define OMAP4430_BGAP_TEMP_SENSOR_SOC_SHIFT 9
> +#define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
> +#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
> +#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
> +#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
> +#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
> +
> +/* TEMP_SENSOR OMAP4460 */
> +#define OMAP4460_BGAP_TEMPSOFF_SHIFT 13
> +#define OMAP4460_BGAP_TEMPSOFF_MASK (1 << 13)
> +#define OMAP4460_BGAP_TEMP_SENSOR_SOC_SHIFT 11
> +#define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK (1 << 11)
> +#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_SHIFT 10
> +#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 10)
> +#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
> +#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
> +
> +/* BANDGAP_CTRL */
> +#define OMAP4460_SINGLE_MODE_SHIFT 31
> +#define OMAP4460_SINGLE_MODE_MASK (1 << 31)
> +#define OMAP4460_MASK_HOT_SHIFT 1
> +#define OMAP4460_MASK_HOT_MASK (1 << 1)
> +#define OMAP4460_MASK_COLD_SHIFT 0
> +#define OMAP4460_MASK_COLD_MASK (1 << 0)
> +
> +/* BANDGAP_COUNTER */
> +#define OMAP4460_COUNTER_SHIFT 0
> +#define OMAP4460_COUNTER_MASK (0xffffff << 0)
> +
> +/* BANDGAP_THRESHOLD */
> +#define OMAP4460_T_HOT_SHIFT 16
> +#define OMAP4460_T_HOT_MASK (0x3ff << 16)
> +#define OMAP4460_T_COLD_SHIFT 0
> +#define OMAP4460_T_COLD_MASK (0x3ff << 0)
> +
> +/* TSHUT_THRESHOLD */
> +#define OMAP4460_TSHUT_HOT_SHIFT 16
> +#define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16)
> +#define OMAP4460_TSHUT_COLD_SHIFT 0
> +#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
> +
> +/* BANDGAP_STATUS */
> +#define OMAP4460_CLEAN_STOP_SHIFT 3
> +#define OMAP4460_CLEAN_STOP_MASK (1 << 3)
> +#define OMAP4460_BGAP_ALERT_SHIFT 2
> +#define OMAP4460_BGAP_ALERT_MASK (1 << 2)
> +#define OMAP4460_HOT_FLAG_SHIFT 1
> +#define OMAP4460_HOT_FLAG_MASK (1 << 1)
> +#define OMAP4460_COLD_FLAG_SHIFT 0
> +#define OMAP4460_COLD_FLAG_MASK (1 << 0)
> +
> +/* TEMP_SENSOR OMAP5430 */
> +#define OMAP5430_BGAP_TEMP_SENSOR_SOC_SHIFT 12
> +#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK (1 << 12)
> +#define OMAP5430_BGAP_TEMPSOFF_SHIFT 11
> +#define OMAP5430_BGAP_TEMPSOFF_MASK (1 << 11)
> +#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_SHIFT 10
> +#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 10)
> +#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
> +#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
> +
> +/* BANDGAP_CTRL */
> +#define OMAP5430_MASK_HOT_CORE_SHIFT 5
> +#define OMAP5430_MASK_HOT_CORE_MASK (1 << 5)
> +#define OMAP5430_MASK_COLD_CORE_SHIFT 4
> +#define OMAP5430_MASK_COLD_CORE_MASK (1 << 4)
> +#define OMAP5430_MASK_HOT_MM_SHIFT 3
> +#define OMAP5430_MASK_HOT_MM_MASK (1 << 3)
> +#define OMAP5430_MASK_COLD_MM_SHIFT 2
> +#define OMAP5430_MASK_COLD_MM_MASK (1 << 2)
> +#define OMAP5430_MASK_HOT_MPU_SHIFT 1
> +#define OMAP5430_MASK_HOT_MPU_MASK (1 << 1)
> +#define OMAP5430_MASK_COLD_MPU_SHIFT 0
> +#define OMAP5430_MASK_COLD_MPU_MASK (1 << 0)
> +
> +/* BANDGAP_COUNTER */
> +#define OMAP5430_REPEAT_MODE_SHIFT 31
> +#define OMAP5430_REPEAT_MODE_MASK (1 << 31)
> +#define OMAP5430_COUNTER_SHIFT 0
> +#define OMAP5430_COUNTER_MASK (0xffffff << 0)
> +
> +/* BANDGAP_THRESHOLD */
> +#define OMAP5430_T_HOT_SHIFT 16
> +#define OMAP5430_T_HOT_MASK (0x3ff << 16)
> +#define OMAP5430_T_COLD_SHIFT 0
> +#define OMAP5430_T_COLD_MASK (0x3ff << 0)
> +
> +/* TSHUT_THRESHOLD */
> +#define OMAP5430_TSHUT_HOT_SHIFT 16
> +#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
> +#define OMAP5430_TSHUT_COLD_SHIFT 0
> +#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
> +
> +/* BANDGAP_STATUS */
> +#define OMAP5430_BGAP_ALERT_SHIFT 31
> +#define OMAP5430_BGAP_ALERT_MASK (1 << 31)
> +#define OMAP5430_HOT_CORE_FLAG_SHIFT 5
> +#define OMAP5430_HOT_CORE_FLAG_MASK (1 << 5)
> +#define OMAP5430_COLD_CORE_FLAG_SHIFT 4
> +#define OMAP5430_COLD_CORE_FLAG_MASK (1 << 4)
> +#define OMAP5430_HOT_MM_FLAG_SHIFT 3
> +#define OMAP5430_HOT_MM_FLAG_MASK (1 << 3)
> +#define OMAP5430_COLD_MM_FLAG_SHIFT 2
> +#define OMAP5430_COLD_MM_FLAG_MASK (1 << 2)
> +#define OMAP5430_HOT_MPU_FLAG_SHIFT 1
> +#define OMAP5430_HOT_MPU_FLAG_MASK (1 << 1)
> +#define OMAP5430_COLD_MPU_FLAG_SHIFT 0
> +#define OMAP5430_COLD_MPU_FLAG_MASK (1 << 0)
> +
> +
> +/**
> + * The register offsets and bit fields might change across
> + * OMAP versions hence populating them in this structure.
> + */
> +
> +struct temp_sensor_registers {
> + u32 temp_sensor_ctrl;
> + u32 bgap_tempsoff_mask;
> + u32 bgap_soc_mask;
> + u32 bgap_eocz_mask;
> + u32 bgap_dtemp_mask;
> +
> + u32 bgap_mask_ctrl;
> + u32 mask_hot_mask;
> + u32 mask_cold_mask;
> +
> + u32 bgap_mode_ctrl;
> + u32 mode_ctrl_mask;
> +
> + u32 bgap_counter;
> + u32 counter_mask;
> +
> + u32 bgap_threshold;
> + u32 threshold_thot_mask;
> + u32 threshold_tcold_mask;
> +
> + u32 tshut_threshold;
> + u32 tshut_hot_mask;
> + u32 tshut_cold_mask;
> +
> + u32 bgap_status;
> + u32 status_clean_stop_mask;
> + u32 status_bgap_alert_mask;
> + u32 status_hot_mask;
> + u32 status_cold_mask;
> +
> + u32 bgap_efuse;
> + spinlock_t bg_reg_lock;
> +};
> +
> +/**
> + * The thresholds and limits for temperature sensors.
> + */
> +struct temp_sensor_data {
> + u32 tshut_hot;
> + u32 tshut_cold;
> + u32 t_hot;
> + u32 t_cold;
> + u32 min_freq;
> + u32 max_freq;
> + int max_temp;
> + int min_temp;
> + int hyst_val;
> + u32 adc_start_val;
> + u32 adc_end_val;
> + u32 update_int1;
> + u32 update_int2;
> +};
> +
> +/**
> + * struct temp_sensor_regval - temperature sensor register values
> + * @bg_mode_ctrl: temp sensor control register value
> + * @bg_ctrl: bandgap ctrl register value
> + * @bg_counter: bandgap counter value
> + * @bg_threshold: bandgap threshold register value
> + * @tshut_threshold: bandgap tshut register value
> + */
> +struct temp_sensor_regval {
> + u32 bg_mode_ctrl;
> + u32 bg_ctrl;
> + u32 bg_counter;
> + u32 bg_threshold;
> + u32 tshut_threshold;
> +};
> +
> +/**
> + * struct omap_temp_sensor - bandgap temperature sensor platform data
> + * @ts_data: pointer to struct with thresholds, limits of temperature sensor
> + * @registers: pointer to the list of register offsets and bitfields
> + * @regval: temperature sensor register values
> + * @domain: the name of the domain where the sensor is located
> + */
> +struct omap_temp_sensor {
> + struct temp_sensor_data *ts_data;
> + struct temp_sensor_registers *registers;
> + struct temp_sensor_regval *regval;
> + char *domain;
> +};
> +
> +/**
> + * struct omap_bandgap_data - bandgap platform data structure
> + * @has_talert: indicates if the chip has talert output line
> + * @has_tshut: indicates if the chip has tshut output line
> + * @conv_table: Pointer to adc to temperature conversion table
> + * @fclock_name: clock name of the functional clock
> + * @div_ck_nme: clock name of the clock divisor
> + * @sensor_count: count of temperature sensor device in scm
> + * @sensors: array of sensors present in this bandgap instance
> + * @expose_sensor: callback to export sensor to thermal API
> + */
> +struct omap_bandgap_data {
> + bool has_talert;
> + bool has_tshut;
> + int tshut_gpio;
> + const int *conv_table;
> + char *fclock_name;
> + char *div_ck_name;
> + int sensor_count;
> + int (*report_temperature)(struct omap_bandgap *bg_ptr, int id);
> + int (*expose_sensor)(struct omap_bandgap *bg_ptr, int id, char *domain);
> + int irq;
> +
> + /* this needs to be at the end */
> + struct omap_temp_sensor sensors[];
> +};
> +
> +/* TODO: provide data structures for 4430 */
> +
> +/*
> + * OMAP4460 has one instance of thermal sensor for MPU
> + * need to describe the individual bit fields
> + */
> +static struct temp_sensor_registers
> +omap4460_mpu_temp_sensor_registers = {
> + .temp_sensor_ctrl = OMAP4460_TEMP_SENSOR_CTRL_OFFSET,
> + .bgap_tempsoff_mask = OMAP4460_BGAP_TEMPSOFF_MASK,
> + .bgap_soc_mask = OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK,
> + .bgap_eocz_mask = OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK,
> + .bgap_dtemp_mask = OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK,
> +
> + .bgap_mask_ctrl = OMAP4460_BGAP_CTRL_OFFSET,
> + .mask_hot_mask = OMAP4460_MASK_HOT_MASK,
> + .mask_cold_mask = OMAP4460_MASK_COLD_MASK,
> +
> + .bgap_mode_ctrl = OMAP4460_BGAP_CTRL_OFFSET,
> + .mode_ctrl_mask = OMAP4460_SINGLE_MODE_MASK,
> +
> + .bgap_counter = OMAP4460_BGAP_COUNTER_OFFSET,
> + .counter_mask = OMAP4460_COUNTER_MASK,
> +
> + .bgap_threshold = OMAP4460_BGAP_THRESHOLD_OFFSET,
> + .threshold_thot_mask = OMAP4460_T_HOT_MASK,
> + .threshold_tcold_mask = OMAP4460_T_COLD_MASK,
> +
> + .tshut_threshold = OMAP4460_BGAP_TSHUT_OFFSET,
> + .tshut_hot_mask = OMAP4460_TSHUT_HOT_MASK,
> + .tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK,
> +
> + .bgap_status = OMAP4460_BGAP_STATUS_OFFSET,
> + .status_clean_stop_mask = OMAP4460_CLEAN_STOP_MASK,
> + .status_bgap_alert_mask = OMAP4460_BGAP_ALERT_MASK,
> + .status_hot_mask = OMAP4460_HOT_FLAG_MASK,
> + .status_cold_mask = OMAP4460_COLD_FLAG_MASK,
> +
> + .bgap_efuse = OMAP4460_FUSE_OPP_BGAP,
> +};
> +
> +/*
> + * OMAP4460 has one instance of thermal sensor for MPU
> + * need to describe the individual bit fields
> + */
> +static struct temp_sensor_registers
> +omap5430_mpu_temp_sensor_registers = {
> + .temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_MPU_OFFSET,
> + .bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
> + .bgap_soc_mask = OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK,
> + .bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
> + .bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
> +
> + .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
> + .mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK,
> + .mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK,
> +
> + .bgap_mode_ctrl = OMAP5430_BGAP_COUNTER_MPU_OFFSET,
> + .mode_ctrl_mask = OMAP5430_REPEAT_MODE_MASK,
> +
> + .bgap_counter = OMAP5430_BGAP_COUNTER_MPU_OFFSET,
> + .counter_mask = OMAP5430_COUNTER_MASK,
> +
> + .bgap_threshold = OMAP5430_BGAP_THRESHOLD_MPU_OFFSET,
> + .threshold_thot_mask = OMAP5430_T_HOT_MASK,
> + .threshold_tcold_mask = OMAP5430_T_COLD_MASK,
> +
> + .tshut_threshold = OMAP5430_BGAP_TSHUT_MPU_OFFSET,
> + .tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
> + .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
> +
> + .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
> + .status_clean_stop_mask = 0x0,
> + .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
> + .status_hot_mask = OMAP5430_HOT_MPU_FLAG_MASK,
> + .status_cold_mask = OMAP5430_COLD_MPU_FLAG_MASK,
> +
> + .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_MPU,
> +};
> +
> +/*
> + * OMAP4460 has one instance of thermal sensor for MPU
> + * need to describe the individual bit fields
> + */
> +static struct temp_sensor_registers
> +omap5430_gpu_temp_sensor_registers = {
> + .temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_GPU_OFFSET,
> + .bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
> + .bgap_soc_mask = OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK,
> + .bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
> + .bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
> +
> + .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
> + .mask_hot_mask = OMAP5430_MASK_HOT_MM_MASK,
> + .mask_cold_mask = OMAP5430_MASK_COLD_MM_MASK,
> +
> + .bgap_mode_ctrl = OMAP5430_BGAP_COUNTER_GPU_OFFSET,
> + .mode_ctrl_mask = OMAP5430_REPEAT_MODE_MASK,
> +
> + .bgap_counter = OMAP5430_BGAP_COUNTER_GPU_OFFSET,
> + .counter_mask = OMAP5430_COUNTER_MASK,
> +
> + .bgap_threshold = OMAP5430_BGAP_THRESHOLD_GPU_OFFSET,
> + .threshold_thot_mask = OMAP5430_T_HOT_MASK,
> + .threshold_tcold_mask = OMAP5430_T_COLD_MASK,
> +
> + .tshut_threshold = OMAP5430_BGAP_TSHUT_GPU_OFFSET,
> + .tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
> + .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
> +
> + .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
> + .status_clean_stop_mask = 0x0,
> + .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
> + .status_hot_mask = OMAP5430_HOT_MM_FLAG_MASK,
> + .status_cold_mask = OMAP5430_COLD_MM_FLAG_MASK,
> +
> + .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_GPU,
> +};
> +
> +/*
> + * OMAP4460 has one instance of thermal sensor for MPU
> + * need to describe the individual bit fields
> + */
> +static struct temp_sensor_registers
> +omap5430_core_temp_sensor_registers = {
> + .temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_CORE_OFFSET,
> + .bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
> + .bgap_soc_mask = OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK,
> + .bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
> + .bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
> +
> + .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
> + .mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK,
> + .mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK,
> +
> + .bgap_mode_ctrl = OMAP5430_BGAP_COUNTER_CORE_OFFSET,
> + .mode_ctrl_mask = OMAP5430_REPEAT_MODE_MASK,
> +
> + .bgap_counter = OMAP5430_BGAP_COUNTER_CORE_OFFSET,
> + .counter_mask = OMAP5430_COUNTER_MASK,
> +
> + .bgap_threshold = OMAP5430_BGAP_THRESHOLD_CORE_OFFSET,
> + .threshold_thot_mask = OMAP5430_T_HOT_MASK,
> + .threshold_tcold_mask = OMAP5430_T_COLD_MASK,
> +
> + .tshut_threshold = OMAP5430_BGAP_TSHUT_CORE_OFFSET,
> + .tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
> + .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
> +
> + .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
> + .status_clean_stop_mask = 0x0,
> + .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
> + .status_hot_mask = OMAP5430_HOT_CORE_FLAG_MASK,
> + .status_cold_mask = OMAP5430_COLD_CORE_FLAG_MASK,
> +
> + .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_CORE,
> +};
> +
> +/* Thresholds and limits for OMAP4460 MPU temperature sensor */
> +static struct temp_sensor_data omap4460_mpu_temp_sensor_data = {
> + .tshut_hot = OMAP4460_TSHUT_HOT,
> + .tshut_cold = OMAP4460_TSHUT_COLD,
> + .t_hot = OMAP4460_T_HOT,
> + .t_cold = OMAP4460_T_COLD,
> + .min_freq = OMAP4460_MIN_FREQ,
> + .max_freq = OMAP4460_MAX_FREQ,
> + .max_temp = OMAP4460_MAX_TEMP,
> + .min_temp = OMAP4460_MIN_TEMP,
> + .hyst_val = OMAP4460_HYST_VAL,
> + .adc_start_val = OMAP4460_ADC_START_VALUE,
> + .adc_end_val = OMAP4460_ADC_END_VALUE,
> + .update_int1 = 1000,
> + .update_int2 = 2000,
> +};
> +
> +/* Thresholds and limits for OMAP5430 MPU temperature sensor */
> +static struct temp_sensor_data omap5430_mpu_temp_sensor_data = {
> + .tshut_hot = OMAP5430_MPU_TSHUT_HOT,
> + .tshut_cold = OMAP5430_MPU_TSHUT_COLD,
> + .t_hot = OMAP5430_MPU_T_HOT,
> + .t_cold = OMAP5430_MPU_T_COLD,
> + .min_freq = OMAP5430_MPU_MIN_FREQ,
> + .max_freq = OMAP5430_MPU_MAX_FREQ,
> + .max_temp = OMAP5430_MPU_MAX_TEMP,
> + .min_temp = OMAP5430_MPU_MIN_TEMP,
> + .hyst_val = OMAP5430_MPU_HYST_VAL,
> + .adc_start_val = OMAP5430_ADC_START_VALUE,
> + .adc_end_val = OMAP5430_ADC_END_VALUE,
> + .update_int1 = 1000,
> + .update_int2 = 2000,
> +};
> +
> +/* Thresholds and limits for OMAP5430 GPU temperature sensor */
> +static struct temp_sensor_data omap5430_gpu_temp_sensor_data = {
> + .tshut_hot = OMAP5430_GPU_TSHUT_HOT,
> + .tshut_cold = OMAP5430_GPU_TSHUT_COLD,
> + .t_hot = OMAP5430_GPU_T_HOT,
> + .t_cold = OMAP5430_GPU_T_COLD,
> + .min_freq = OMAP5430_GPU_MIN_FREQ,
> + .max_freq = OMAP5430_GPU_MAX_FREQ,
> + .max_temp = OMAP5430_GPU_MAX_TEMP,
> + .min_temp = OMAP5430_GPU_MIN_TEMP,
> + .hyst_val = OMAP5430_GPU_HYST_VAL,
> + .adc_start_val = OMAP5430_ADC_START_VALUE,
> + .adc_end_val = OMAP5430_ADC_END_VALUE,
> + .update_int1 = 1000,
> + .update_int2 = 2000,
> +};
> +
> +/* Thresholds and limits for OMAP5430 CORE temperature sensor */
> +static struct temp_sensor_data omap5430_core_temp_sensor_data = {
> + .tshut_hot = OMAP5430_CORE_TSHUT_HOT,
> + .tshut_cold = OMAP5430_CORE_TSHUT_COLD,
> + .t_hot = OMAP5430_CORE_T_HOT,
> + .t_cold = OMAP5430_CORE_T_COLD,
> + .min_freq = OMAP5430_CORE_MIN_FREQ,
> + .max_freq = OMAP5430_CORE_MAX_FREQ,
> + .max_temp = OMAP5430_CORE_MAX_TEMP,
> + .min_temp = OMAP5430_CORE_MIN_TEMP,
> + .hyst_val = OMAP5430_CORE_HYST_VAL,
> + .adc_start_val = OMAP5430_ADC_START_VALUE,
> + .adc_end_val = OMAP5430_ADC_END_VALUE,
> + .update_int1 = 1000,
> + .update_int2 = 2000,
> +};
> +
> +/*
> + * Temperature values in milli degree celsius
> + * ADC code values from 530 to 923
> + */
> +static const int
> +omap4460_adc_to_temp[OMAP4460_ADC_END_VALUE - OMAP4460_ADC_START_VALUE + 1] = {
> + -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
> + -37800, -37300, -36800, -36400, -36000, -35600, -35200, -34800,
> + -34300, -33800, -33400, -33000, -32600, -32200, -31800, -31300,
> + -30800, -30400, -30000, -29600, -29200, -28700, -28200, -27800,
> + -27400, -27000, -26600, -26200, -25700, -25200, -24800, -24400,
> + -24000, -23600, -23200, -22700, -22200, -21800, -21400, -21000,
> + -20600, -20200, -19700, -19200, -18800, -18400, -18000, -17600,
> + -17200, -16700, -16200, -15800, -15400, -15000, -14600, -14200,
> + -13700, -13200, -12800, -12400, -12000, -11600, -11200, -10700,
> + -10200, -9800, -9400, -9000, -8600, -8200, -7700, -7200, -6800,
> + -6400, -6000, -5600, -5200, -4800, -4300, -3800, -3400, -3000,
> + -2600, -2200, -1800, -1300, -800, -400, 0, 400, 800, 1200, 1600,
> + 2100, 2600, 3000, 3400, 3800, 4200, 4600, 5100, 5600, 6000, 6400,
> + 6800, 7200, 7600, 8000, 8500, 9000, 9400, 9800, 10200, 10600, 11000,
> + 11400, 11900, 12400, 12800, 13200, 13600, 14000, 14400, 14800,
> + 15300, 15800, 16200, 16600, 17000, 17400, 17800, 18200, 18700,
> + 19200, 19600, 20000, 20400, 20800, 21200, 21600, 22100, 22600,
> + 23000, 23400, 23800, 24200, 24600, 25000, 25400, 25900, 26400,
> + 26800, 27200, 27600, 28000, 28400, 28800, 29300, 29800, 30200,
> + 30600, 31000, 31400, 31800, 32200, 32600, 33100, 33600, 34000,
> + 34400, 34800, 35200, 35600, 36000, 36400, 36800, 37300, 37800,
> + 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41100, 41600,
> + 42000, 42400, 42800, 43200, 43600, 44000, 44400, 44800, 45300,
> + 45800, 46200, 46600, 47000, 47400, 47800, 48200, 48600, 49000,
> + 49500, 50000, 50400, 50800, 51200, 51600, 52000, 52400, 52800,
> + 53200, 53700, 54200, 54600, 55000, 55400, 55800, 56200, 56600,
> + 57000, 57400, 57800, 58200, 58700, 59200, 59600, 60000, 60400,
> + 60800, 61200, 61600, 62000, 62400, 62800, 63300, 63800, 64200,
> + 64600, 65000, 65400, 65800, 66200, 66600, 67000, 67400, 67800,
> + 68200, 68700, 69200, 69600, 70000, 70400, 70800, 71200, 71600,
> + 72000, 72400, 72800, 73200, 73600, 74100, 74600, 75000, 75400,
> + 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, 79000,
> + 79400, 79800, 80300, 80800, 81200, 81600, 82000, 82400, 82800,
> + 83200, 83600, 84000, 84400, 84800, 85200, 85600, 86000, 86400,
> + 86800, 87300, 87800, 88200, 88600, 89000, 89400, 89800, 90200,
> + 90600, 91000, 91400, 91800, 92200, 92600, 93000, 93400, 93800,
> + 94200, 94600, 95000, 95500, 96000, 96400, 96800, 97200, 97600,
> + 98000, 98400, 98800, 99200, 99600, 100000, 100400, 100800, 101200,
> + 101600, 102000, 102400, 102800, 103200, 103600, 104000, 104400,
> + 104800, 105200, 105600, 106100, 106600, 107000, 107400, 107800,
> + 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
> + 111400, 111800, 112200, 112600, 113000, 113400, 113800, 114200,
> + 114600, 115000, 115400, 115800, 116200, 116600, 117000, 117400,
> + 117800, 118200, 118600, 119000, 119400, 119800, 120200, 120600,
> + 121000, 121400, 121800, 122200, 122600, 123000, 123400, 123800, 124200,
> + 124600, 124900, 125000, 125000, 125000, 125000
> +};
> +
> +static const int
> +omap5430_adc_to_temp[OMAP5430_ADC_END_VALUE - OMAP5430_ADC_START_VALUE + 1] = {
> + -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600,
> + -38200, -37800, -37300, -36800,
> + -36400, -36000, -35600, -35200, -34800, -34300, -33800, -33400, -33000,
> + -32600,
> + -32200, -31800, -31300, -30800, -30400, -30000, -29600, -29200, -28700,
> + -28200, -27800, -27400, -27000, -26600, -26200, -25700, -25200, -24800,
> + -24400, -24000, -23600, -23200, -22700, -22200, -21800, -21400, -21000,
> + -20600, -20200, -19700, -19200, -9300, -18400, -18000, -17600, -17200,
> + -16700, -16200, -15800, -15400, -15000, -14600, -14200, -13700, -13200,
> + -12800, -12400, -12000, -11600, -11200, -10700, -10200, -9800, -9400,
> + -9000,
> + -8600, -8200, -7700, -7200, -6800, -6400, -6000, -5600, -5200, -4800,
> + -4300,
> + -3800, -3400, -3000, -2600, -2200, -1800, -1300, -800, -400, 0, 400,
> + 800,
> + 1200, 1600, 2100, 2600, 3000, 3400, 3800, 4200, 4600, 5100, 5600, 6000,
> + 6400, 6800, 7200, 7600, 8000, 8500, 9000, 9400, 9800, 10200, 10800,
> + 11100,
> + 11400, 11900, 12400, 12800, 13200, 13600, 14000, 14400, 14800, 15300,
> + 15800,
> + 16200, 16600, 17000, 17400, 17800, 18200, 18700, 19200, 19600, 20000,
> + 20400,
> + 20800, 21200, 21600, 22100, 22600, 23000, 23400, 23800, 24200, 24600,
> + 25000,
> + 25400, 25900, 26400, 26800, 27200, 27600, 28000, 28400, 28800, 29300,
> + 29800,
> + 30200, 30600, 31000, 31400, 31800, 32200, 32600, 33100, 33600, 34000,
> + 34400,
> + 34800, 35200, 35600, 36000, 36400, 36800, 37300, 37800, 38200, 38600,
> + 39000,
> + 39400, 39800, 40200, 40600, 41100, 41600, 42000, 42400, 42800, 43200,
> + 43600,
> + 44000, 44400, 44800, 45300, 45800, 46200, 46600, 47000, 47400, 47800,
> + 48200,
> + 48600, 49000, 49500, 50000, 50400, 50800, 51200, 51600, 52000, 52400,
> + 52800,
> + 53200, 53700, 54200, 54600, 55000, 55400, 55800, 56200, 56600, 57000,
> + 57400,
> + 57800, 58200, 58700, 59200, 59600, 60000, 60400, 60800, 61200, 61600,
> + 62000,
> + 62400, 62800, 63300, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
> + 66600,
> + 67000, 67400, 67800, 68200, 68700, 69200, 69600, 70000, 70400, 70800,
> + 71200,
> + 71600, 72000, 72400, 72800, 73200, 73600, 74100, 74600, 75000, 75400,
> + 75800,
> + 76200, 76600, 77000, 77400, 77800, 78200, 78600, 79000, 79400, 79800,
> + 80300,
> + 80800, 81200, 81600, 82000, 82400, 82800, 83200, 83600, 84000, 84400,
> + 84800,
> + 85200, 85600, 86000, 86400, 86800, 87300, 87800, 88200, 88600, 89000,
> + 89400,
> + 89800, 90200, 90600, 91000, 91400, 91800, 92200, 92600, 93000, 93400,
> + 93800,
> + 94200, 94600, 95000, 95500, 96000, 96400, 96800, 97200, 97600, 98000,
> + 98400,
> + 98800, 99200, 99600, 100000, 100400, 100800, 101200, 101600, 102000,
> + 102400,
> + 102800, 103200, 103600, 104000, 104400, 104800, 105200, 105600, 106100,
> + 106600, 107000, 107400, 107800, 108200, 108600, 109000, 109400, 109800,
> + 110200, 110600, 111000, 111400, 111800, 112200, 112600, 113000, 113400,
> + 113800, 114200, 114600, 115000, 115400, 115800, 116200, 116600, 117000,
> + 117400, 117800, 118200, 118600, 119000, 119400, 119800, 120200, 120600,
> + 121000, 121400, 121800, 122200, 122600, 123000, 123400, 123800, 124200,
> + 124600, 124900, 125000, 125000, 125000, 125000,
> +};
I suppose not all comments on RFC were considered.. Anyways, I have another version
of this driver which has the data structures in separated files.
> +
> +/*
> + * TODO: Get rid from bg_readl() return value -
> + * It's useless.
> + */
> +
> +static int bg_readl(struct omap_bandgap *bg_ptr, u32 reg, u32 *val)
> +{
> + if (!bg_ptr)
> + return -EINVAL;
> +
> + *val = __raw_readl(bg_ptr->bg_base + reg);
> + return 0;
> +}
> +
> +/*
> + * TODO: Get rid from bg_writel() return value -
> + * It's useless.
Same thing as in usb-phy. when removing the return value, remember to leave a WARN_ON at least.
> + */
> +static int bg_writel(struct omap_bandgap *bg_ptr, u32 val, u32 reg, spinlock_t *lock)
> +{
> + unsigned long flags;
> +
> + if (!bg_ptr)
> + return -EINVAL;
> +
> + spin_lock_irqsave(lock, flags);
> + __raw_writel(val, bg_ptr->bg_base + reg);
> + spin_unlock_irqrestore(lock, flags);
> + return 0;
> +}
Please use omap_bandgap_[read/write]l. Otherwise this driver starts to have several prefix patterns (or no prefix pattern)
> +
> +static irqreturn_t talert_irq_handler(int irq, void *data)
> +{
> + struct omap_bandgap *bg_ptr = data;
> + struct temp_sensor_registers *tsr;
> + u32 t_hot = 0, t_cold = 0, temp, ctrl = 0;
> + int i, r;
> +
> + bg_ptr = data;
> + /* Read the status of t_hot */
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + tsr = bg_ptr->pdata->sensors[i].registers;
> + r = bg_readl(bg_ptr, tsr->bgap_status, &t_hot);
> + t_hot &= tsr->status_hot_mask;
> +
> + /* Read the status of t_cold */
> + r |= bg_readl(bg_ptr, tsr->bgap_status, &t_cold);
> + t_cold &= tsr->status_cold_mask;
> +
> + if (!t_cold && !t_hot)
> + continue;
> +
> + r |= bg_readl(bg_ptr, tsr->bgap_mask_ctrl, &ctrl);
> + /*
> + * One TALERT interrupt: Two sources
> + * If the interrupt is due to t_hot then mask t_hot and
> + * and unmask t_cold else mask t_cold and unmask t_hot
> + */
> + if (t_hot) {
> + ctrl &= ~tsr->mask_hot_mask;
> + ctrl |= tsr->mask_cold_mask;
> + } else if (t_cold) {
> + ctrl &= ~tsr->mask_cold_mask;
> + ctrl |= tsr->mask_hot_mask;
> + }
> +
> + r |= bg_writel(bg_ptr, ctrl, tsr->bgap_mask_ctrl, &tsr->bg_reg_lock);
> +
> + if (r) {
> + dev_err(bg_ptr->dev, "failed to ack talert interrupt\n");
> + return IRQ_NONE;
> + }
> +
> + /* read temperature */
> + r = bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= tsr->bgap_dtemp_mask;
> +
> + /* report temperature to whom may concern */
> + if (bg_ptr->pdata->report_temperature)
> + bg_ptr->pdata->report_temperature(bg_ptr, i);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t omap_bandgap_tshut_irq_handler(int irq, void *data)
> +{
> + orderly_poweroff(true);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static
> +int adc_to_temp_conversion(struct omap_bandgap *bg_ptr, int id, int adc_val,
> + int *t)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[id].ts_data;
> +
> + /* look up for temperature in the table and return the temperature */
> + if (adc_val < ts_data->adc_start_val || adc_val > ts_data->adc_end_val)
> + return -ERANGE;
> +
> + *t = bg_ptr->conv_table[adc_val - ts_data->adc_start_val];
> +
> + return 0;
> +}
> +
> +static int temp_to_adc_conversion(long temp, struct omap_bandgap *bg_ptr, int i,
> + int *adc)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[i].ts_data;
> + int high, low, mid;
> +
> + low = 0;
> + high = ts_data->adc_end_val - ts_data->adc_start_val;
> + mid = (high + low) / 2;
> +
> + if (temp < bg_ptr->conv_table[high] || temp > bg_ptr->conv_table[high])
> + return -EINVAL;
> +
> + while (low < high) {
> + if (temp < bg_ptr->conv_table[mid])
> + high = mid - 1;
> + else
> + low = mid + 1;
> + mid = (low + high) / 2;
> + }
> +
> + *adc = ts_data->adc_start_val + low;
> +
> + return 0;
> +}
> +
> +static int temp_sensor_unmask_interrupts(struct omap_bandgap *bg_ptr, int id,
> + u32 t_hot, u32 t_cold)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 temp = 0, reg_val = 0;
> + int err;
> +
> + /* Read the current on die temperature */
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + err = bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= tsr->bgap_dtemp_mask;
> +
> + err |= bg_readl(bg_ptr, tsr->bgap_mask_ctrl, ®_val);
> + if (temp < t_hot)
> + reg_val |= tsr->mask_hot_mask;
> + else
> + reg_val &= ~tsr->mask_hot_mask;
> +
> + if (t_cold < temp)
> + reg_val |= tsr->mask_cold_mask;
> + else
> + reg_val &= ~tsr->mask_cold_mask;
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_mask_ctrl, &tsr->bg_reg_lock);
> +
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to unmask interrupts\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static
> +int add_hyst(int adc_val, int hyst_val, struct omap_bandgap *bg_ptr, int i,
> + u32 *sum)
> +{
> + int temp, ret;
> +
> + ret = adc_to_temp_conversion(bg_ptr, i, adc_val, &temp);
> + if (ret < 0)
> + return ret;
> +
> + temp += hyst_val;
> +
> + return temp_to_adc_conversion(temp, bg_ptr, i, sum);
> +}
> +
> +static
> +int temp_sensor_configure_thot(struct omap_bandgap *bg_ptr, int id, int t_hot)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[id].ts_data;
> + struct temp_sensor_registers *tsr;
> + u32 thresh_val = 0, reg_val;
> + int cold, err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> +
> + /* obtain the T cold value */
> + err = bg_readl(bg_ptr, tsr->bgap_threshold, &thresh_val);
> + cold = (thresh_val & tsr->threshold_tcold_mask) >>
> + __ffs(tsr->threshold_tcold_mask);
> + if (t_hot <= cold) {
> + /* change the t_cold to t_hot - 5000 millidegrees */
> + err |= add_hyst(t_hot, -ts_data->hyst_val, bg_ptr, id, &cold);
> + /* write the new t_cold value */
> + reg_val = thresh_val & (~tsr->threshold_tcold_mask);
> + reg_val |= cold << __ffs(tsr->threshold_tcold_mask);
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + thresh_val = reg_val;
> + }
> +
> + /* write the new t_hot value */
> + reg_val = thresh_val & ~tsr->threshold_thot_mask;
> + reg_val |= (t_hot << __ffs(tsr->threshold_thot_mask));
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram thot threshold\n");
> + return -EIO;
> + }
> +
> + return temp_sensor_unmask_interrupts(bg_ptr, id, t_hot, cold);
> +}
> +
> +static
> +int temp_sensor_init_talert_thresholds(struct omap_bandgap *bg_ptr, int id,
> + int t_hot, int t_cold)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 reg_val, thresh_val;
> + int err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + err = bg_readl(bg_ptr, tsr->bgap_threshold, &thresh_val);
> +
> + /* write the new t_cold value */
> + reg_val = thresh_val & ~tsr->threshold_tcold_mask;
> + reg_val |= (t_cold << __ffs(tsr->threshold_tcold_mask));
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram tcold threshold\n");
> + return -EIO;
> + }
> +
> + err = bg_readl(bg_ptr, tsr->bgap_threshold, &thresh_val);
> +
> + /* write the new t_hot value */
> + reg_val = thresh_val & ~tsr->threshold_thot_mask;
> + reg_val |= (t_hot << __ffs(tsr->threshold_thot_mask));
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram thot threshold\n");
> + return -EIO;
> + }
> +
> + err = bg_readl(bg_ptr, tsr->bgap_mask_ctrl, ®_val);
> + reg_val |= tsr->mask_hot_mask;
> + reg_val |= tsr->mask_cold_mask;
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_mask_ctrl, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram thot threshold\n");
> + return -EIO;
> + }
> +
> + return err;
> +}
> +
> +static
> +int temp_sensor_configure_tcold(struct omap_bandgap *bg_ptr, int id,
> + int t_cold)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[id].ts_data;
> + struct temp_sensor_registers *tsr;
> + u32 thresh_val = 0, reg_val;
> + int hot, err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + /* obtain the T cold value */
> + err = bg_readl(bg_ptr, tsr->bgap_threshold, &thresh_val);
> + hot = (thresh_val & tsr->threshold_thot_mask) >>
> + __ffs(tsr->threshold_thot_mask);
> +
> + if (t_cold >= hot) {
> + /* change the t_hot to t_cold + 5000 millidegrees */
> + err |= add_hyst(t_cold, ts_data->hyst_val, bg_ptr, id, &hot);
> + /* write the new t_hot value */
> + reg_val = thresh_val & (~tsr->threshold_thot_mask);
> + reg_val |= hot << __ffs(tsr->threshold_thot_mask);
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + thresh_val = reg_val;
> + }
> +
> + /* write the new t_cold value */
> + reg_val = thresh_val & ~tsr->threshold_tcold_mask;
> + reg_val |= (t_cold << __ffs(tsr->threshold_tcold_mask));
> + err |= bg_writel(bg_ptr, reg_val, tsr->bgap_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram tcold threshold\n");
> + return -EIO;
> + }
> +
> + return temp_sensor_unmask_interrupts(bg_ptr, id, hot, t_cold);
> +}
> +
> +static int temp_sensor_configure_tshut_hot(struct omap_bandgap *bg_ptr,
> + int id, int tshut_hot)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 reg_val;
> + int err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + err = bg_readl(bg_ptr, tsr->tshut_threshold, ®_val);
> + reg_val &= ~tsr->tshut_hot_mask;
> + reg_val |= tshut_hot << __ffs(tsr->tshut_hot_mask);
> + err |= bg_writel(bg_ptr, reg_val, tsr->tshut_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram tshut thot\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int temp_sensor_configure_tshut_cold(struct omap_bandgap *bg_ptr,
> + int id, int tshut_cold)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 reg_val;
> + int err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + err = bg_readl(bg_ptr, tsr->tshut_threshold, ®_val);
> + reg_val &= ~tsr->tshut_cold_mask;
> + reg_val |= tshut_cold << __ffs(tsr->tshut_cold_mask);
> + err |= bg_writel(bg_ptr, reg_val, tsr->tshut_threshold, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram tshut tcold\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int configure_temp_sensor_counter(struct omap_bandgap *bg_ptr, int id,
> + u32 counter)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 val = 0;
> + int err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + err = bg_readl(bg_ptr, tsr->bgap_counter, &val);
> + val &= ~tsr->counter_mask;
> + val |= counter << __ffs(tsr->counter_mask);
> + err |= bg_writel(bg_ptr, val, tsr->bgap_counter, &tsr->bg_reg_lock);
> + if (err) {
> + dev_err(bg_ptr->dev, "failed to reprogram tshut tcold\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/* Exposed APIs */
> +/**
> + * omap_bandgap_read_thot() - reads sensor current thot
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @thot - resulting current thot value
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_read_thot(struct omap_bandgap *bg_ptr, int id,
> + int *thot)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 temp;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + ret = bg_readl(bg_ptr, tsr->bgap_threshold, &temp);
> + temp = (temp & tsr->threshold_thot_mask) >>
> + __ffs(tsr->threshold_thot_mask);
> + ret |= adc_to_temp_conversion(bg_ptr, id, temp, &temp);
> + if (ret) {
> + dev_err(bg_ptr->dev, "failed to read thot\n");
> + return -EIO;
> + }
> +
> + *thot = temp;
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_write_thot() - sets sensor current thot
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @val - desired thot value
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_write_thot(struct omap_bandgap *bg_ptr, int id, int val)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[id].ts_data;
> + struct temp_sensor_registers *tsr;
> + u32 t_hot;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> +
> + if (val < ts_data->min_temp + ts_data->hyst_val)
> + return -EINVAL;
> + ret = temp_to_adc_conversion(val, bg_ptr, id, &t_hot);
> + if (ret < 0)
> + return ret;
> +
> + mutex_lock(&bg_ptr->bg_mutex);
> + temp_sensor_configure_thot(bg_ptr, id, t_hot);
> + mutex_unlock(&bg_ptr->bg_mutex);
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_read_tcold() - reads sensor current tcold
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @tcold - resulting current tcold value
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_read_tcold(struct omap_bandgap *bg_ptr, int id,
> + int *tcold)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 temp;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + ret = bg_readl(bg_ptr, tsr->bgap_threshold, &temp);
> + temp = (temp & tsr->threshold_tcold_mask)
> + >> __ffs(tsr->threshold_tcold_mask);
> + ret |= adc_to_temp_conversion(bg_ptr, id, temp, &temp);
> + if (ret)
> + return -EIO;
> +
> + *tcold = temp;
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_write_tcold() - sets the sensor tcold
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @val - desired tcold value
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_write_tcold(struct omap_bandgap *bg_ptr, int id, int val)
> +{
> + struct temp_sensor_data *ts_data = bg_ptr->pdata->sensors[id].ts_data;
> + struct temp_sensor_registers *tsr;
> + u32 t_cold;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + if (val > ts_data->max_temp + ts_data->hyst_val)
> + return -EINVAL;
> +
> + ret = temp_to_adc_conversion(val, bg_ptr, id, &t_cold);
> + if (ret < 0)
> + return ret;
> +
> + mutex_lock(&bg_ptr->bg_mutex);
> + temp_sensor_configure_tcold(bg_ptr, id, t_cold);
> + mutex_unlock(&bg_ptr->bg_mutex);
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_read_update_interval() - read the sensor update interval
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @interval - resulting update interval in miliseconds
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_read_update_interval(struct omap_bandgap *bg_ptr, int id,
> + int *interval)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 time;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + ret = bg_readl(bg_ptr, tsr->bgap_counter, &time);
> + if (ret)
> + return ret;
> + time = (time & tsr->counter_mask) >> __ffs(tsr->counter_mask);
> + time = time * 1000 / bg_ptr->clk_rate;
> +
> + *interval = time;
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_write_update_interval() - set the update interval
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @interval - desired update interval in miliseconds
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_write_update_interval(struct omap_bandgap *bg_ptr,
> + int id, u32 interval)
> +{
> + interval = interval * bg_ptr->clk_rate / 1000;
> + mutex_lock(&bg_ptr->bg_mutex);
> + configure_temp_sensor_counter(bg_ptr, id, interval);
> + mutex_unlock(&bg_ptr->bg_mutex);
> +
> + return 0;
> +}
> +
> +/**
> + * omap_bandgap_read_temperature() - report current temperature
> + * @bg_ptr - pointer to bandgap instance
> + * @id - sensor id
> + * @temperature - resulting temperature
> + *
> + * returns 0 on success or the proper error code
> + */
> +int omap_bandgap_read_temperature(struct omap_bandgap *bg_ptr, int id,
> + int *temperature)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 temp;
> + int ret;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + ret = bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= tsr->bgap_dtemp_mask;
> +
> + ret |= adc_to_temp_conversion(bg_ptr, id, temp, &temp);
> + if (ret)
> + return -EIO;
> +
> + *temperature = temp;
> +
> + return 0;
> +}
> +
> +/**
> + * enable_continuous_mode() - One time enabling of continuous conversion mode
> + * @bg_ptr - pointer to scm instance
> + */
> +static int enable_continuous_mode(struct omap_bandgap *bg_ptr)
> +{
> + struct temp_sensor_registers *tsr;
> + int i, r;
> + u32 val;
> +
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + tsr = bg_ptr->pdata->sensors[i].registers;
> + r = bg_readl(bg_ptr, tsr->bgap_mode_ctrl, &val);
> + val |= 1 << __ffs(tsr->mode_ctrl_mask);
> + r |= bg_writel(bg_ptr, val, tsr->bgap_mode_ctrl, &tsr->bg_reg_lock);
> + if (r)
> + dev_err(bg_ptr->dev, "could not save sensor %d\n", i);
> + }
> +
> + return r ? -EIO : 0;
> +}
> +
> +static int omap_bandgap_tshut_init(struct omap_bandgap *bg_ptr,
> + struct platform_device *pdev)
> +{
> + int gpio_nr = bg_ptr->tshut_gpio;
> + int status;
> +
> + /* Request for gpio_86 line */
> + status = gpio_request(gpio_nr, "tshut");
> + if (status < 0) {
> + dev_err(bg_ptr->dev,
> + "Could not request for TSHUT GPIO:%i\n", 86);
> + return status;
> + }
> + status = gpio_direction_input(gpio_nr);
> + if (status) {
> + dev_err(bg_ptr->dev,
> + "Cannot set input TSHUT GPIO %d\n", gpio_nr);
> + return status;
> + }
> +
> + status = request_irq(gpio_to_irq(gpio_nr),
> + omap_bandgap_tshut_irq_handler,
> + IRQF_TRIGGER_RISING, "tshut",
> + NULL);
> + if (status) {
> + gpio_free(gpio_nr);
> + dev_err(bg_ptr->dev, "request irq failed for TSHUT");
> + }
> +
> + return 0;
> +}
> +
> +static int omap_bandgap_talert_init(struct omap_bandgap *bg_ptr,
> + struct platform_device *pdev)
> +{
> + int ret;
> +
> + bg_ptr->irq = platform_get_irq(pdev, 0);
> + if (bg_ptr->irq < 0) {
> + dev_err(&pdev->dev, "get_irq failed\n");
> + return bg_ptr->irq;
> + }
> + ret = request_threaded_irq(bg_ptr->irq, NULL,
> + talert_irq_handler,
> + IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> + "talert", bg_ptr);
> + if (ret) {
> + dev_err(&pdev->dev, "Request threaded irq failed.\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct omap_bandgap_data omap4460_data = {
> + .has_talert = true,
> + .has_tshut = true,
> + .tshut_gpio = 86,
> + .fclock_name = "bandgap_ts_fclk",
> + .div_ck_name = "div_ts_ck",
> + .conv_table = omap4460_adc_to_temp,
> + .irq = 126,
> + .sensors = {
> + {
> + .registers = &omap4460_mpu_temp_sensor_registers,
> + .ts_data = &omap4460_mpu_temp_sensor_data,
> + .domain = "cpu",
> + },
> + },
> + .sensor_count = 1,
> +};
> +
> +static const struct omap_bandgap_data omap5430_data = {
> + .has_talert = true,
> + .has_tshut = true,
> + .tshut_gpio = 0, /* TODO. Fill correct tshut_gpio */
> + .fclock_name = "ts_clk_div_ck",
> + .div_ck_name = "ts_clk_div_ck",
> + .conv_table = omap5430_adc_to_temp,
> + .irq = 0, /* TODO. Fill correct irq */
> + .sensors = {
> + {
> + .registers = &omap5430_mpu_temp_sensor_registers,
> + .ts_data = &omap5430_mpu_temp_sensor_data,
> + .domain = "cpu",
> + },
> + {
> + .registers = &omap5430_gpu_temp_sensor_registers,
> + .ts_data = &omap5430_gpu_temp_sensor_data,
> + .domain = "gpu",
> + },
> + {
> + .registers = &omap5430_core_temp_sensor_registers,
> + .ts_data = &omap5430_core_temp_sensor_data,
> + .domain = "core",
> + },
> + },
> + .sensor_count = 3,
> +};
> +
> +static const struct of_device_id of_omap_bandgap_match[] = {
> + /*
> + * TODO: Add support to 4430
> + * { .compatible = "ti,omap4430-bandgap", .data = , },
> + */
> + {
> + .compatible = "ti,omap4-bandgap",
You didnt update the doc.
> + },
> + /* Sentinel */
> + { },
> +};
> +
> +static struct omap_bandgap *omap_bandgap_build(struct platform_device *pdev)
> +{
> + struct device_node *node = pdev->dev.of_node;
> + struct omap_bandgap *bg_ptr;
> + u32 val;
> + struct resource *io_res;
> + struct platform_device *pparent;
> +
> + /* just for the sake */
> + if (!node) {
> + dev_err(&pdev->dev, "No platform information available\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + bg_ptr = devm_kzalloc(&pdev->dev, sizeof(struct omap_bandgap),
> + GFP_KERNEL);
> + if (!bg_ptr) {
> + dev_err(&pdev->dev, "Unable to allocate mem for driver ref\n");
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + if (!pdev->dev.parent) {
> + dev_err(&pdev->dev, "No parent device!\n");
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + pparent = to_platform_device(pdev->dev.parent);
> + io_res = platform_get_resource(pparent, IORESOURCE_MEM, 0);
Same question on usbphy applies here. what do we want to achieve by doing this at children code?
> + if (!io_res) {
> + dev_err(&pdev->dev, "Failed to get IO resource\n");
> + return ERR_PTR(-ENOENT);
> + }
> +
> + bg_ptr->bg_base = ioremap(io_res->start, resource_size(io_res));
> + if (!bg_ptr->bg_base)
> + return 0;
> +
> + bg_readl(bg_ptr, 0x0, &val);
use a macro for the offset.
> +
> + /*
> + * Check omap control core module revision to find out
> + * bandgap type
> + */
> + switch ((val & 0x3ff) >> 8) {
> + case 1:
> + /* 4430 */
> + bg_ptr->pdata = &omap4460_data;
> + break;
> + case 2:
> + /* 4460 */
> + bg_ptr->pdata = &omap4460_data;
> + break;
3 would be 4470.
But O5 has exactly same register value as 4430.
So, I think this won't work just the way it is.
We can either go back to the previous "compatible" approach.
Or we can have a match function mixed with compatible and register value.
Meaning, when omap4- is passed in compatible, you match in the above way.
But when omap5- is passed in compatible, you match in a way which fits to
o5 register value.
This is getting overcomplicated though...
> + default:
> + /* Unknown omap control core module revision */
> + return 0;
> + }
> +
> + if (bg_ptr->pdata->has_tshut) {
> + bg_ptr->tshut_gpio = bg_ptr->pdata->tshut_gpio;
> + if (!gpio_is_valid(bg_ptr->tshut_gpio)) {
> + dev_err(&pdev->dev, "invalid gpio for tshut (%d)\n",
> + bg_ptr->tshut_gpio);
> + return ERR_PTR(-EINVAL);
> + }
> + }
> +
> + return bg_ptr;
> +}
> +
> +struct resource *platform_get_resource_dbg(struct platform_device *dev,
> + unsigned int type, unsigned int num);
> +
> +static
> +int __devinit omap_bandgap_probe(struct platform_device *pdev)
> +{
> + struct omap_bandgap *bg_ptr;
> + int clk_rate, ret = 0, i;
> +
> + bg_ptr = omap_bandgap_build(pdev);
> + if (IS_ERR_OR_NULL(bg_ptr)) {
> + dev_err(&pdev->dev, "failed to fetch platform data\n");
> + return PTR_ERR(bg_ptr);
> + }
> +
> + if (bg_ptr->pdata->has_talert) {
> + ret = omap_bandgap_talert_init(bg_ptr, pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to initialize Talert IRQ\n");
> + return ret;
> + }
> + }
> +
> + if (bg_ptr->pdata->has_tshut) {
> + ret = omap_bandgap_tshut_init(bg_ptr, pdev);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "failed to initialize system tshut IRQ\n");
> + goto free_talert;
> + }
> + }
> +
> + bg_ptr->fclock = clk_get(NULL, bg_ptr->pdata->fclock_name);
> + ret = IS_ERR_OR_NULL(bg_ptr->fclock);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request fclock reference\n");
> + goto free_irqs;
> + }
> +
> + bg_ptr->div_clk = clk_get(NULL, bg_ptr->pdata->div_ck_name);
> + ret = IS_ERR_OR_NULL(bg_ptr->div_clk);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "failed to request div_ts_ck clock ref\n");
> + goto free_irqs;
> + }
> +
> + bg_ptr->conv_table = bg_ptr->pdata->conv_table;
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + struct temp_sensor_registers *tsr;
> + u32 val;
> +
> + tsr = bg_ptr->pdata->sensors[i].registers;
> + /* Initialize register lock */
> + spin_lock_init(&tsr->bg_reg_lock);
> +
> + /*
> + * check if the efuse has a non-zero value if not
> + * it is an untrimmed sample and the temperatures
> + * may not be accurate
> + */
> + ret = bg_readl(bg_ptr, tsr->bgap_efuse, &val);
> + if (ret || !val)
> + dev_info(&pdev->dev,
> + "Non-trimmed BGAP, Temp not accurate\n");
> + }
> +
> + clk_rate = clk_round_rate(bg_ptr->div_clk,
> + bg_ptr->pdata->sensors[0].ts_data->max_freq);
> + if (clk_rate < bg_ptr->pdata->sensors[0].ts_data->min_freq ||
> + clk_rate == 0xffffffff) {
> + ret = -ENODEV;
> + goto put_clks;
> + }
> +
> + ret = clk_set_rate(bg_ptr->div_clk, clk_rate);
> + if (ret) {
> + dev_err(&pdev->dev, "Cannot set clock rate\n");
> + goto put_clks;
> + }
> +
> + bg_ptr->clk_rate = clk_rate;
> + clk_enable(bg_ptr->fclock);
> +
> + mutex_init(&bg_ptr->bg_mutex);
> + bg_ptr->dev = &pdev->dev;
> + platform_set_drvdata(pdev, bg_ptr);
> +
> + /* 1 clk cycle */
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++)
> + configure_temp_sensor_counter(bg_ptr, i, 1);
> +
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + struct temp_sensor_data *ts_data;
> +
> + ts_data = bg_ptr->pdata->sensors[i].ts_data;
> +
> + temp_sensor_init_talert_thresholds(bg_ptr, i,
> + ts_data->t_hot,
> + ts_data->t_cold);
> + temp_sensor_configure_tshut_hot(bg_ptr, i,
> + ts_data->tshut_hot);
> + temp_sensor_configure_tshut_cold(bg_ptr, i,
> + ts_data->tshut_cold);
> + }
> +
> + enable_continuous_mode(bg_ptr);
> +
> + /* Set .250 seconds time as default counter */
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++)
> + configure_temp_sensor_counter(bg_ptr, i,
> + bg_ptr->clk_rate / 4);
> +
> + /* Every thing is good? Then expose the sensors */
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + char *domain;
> +
> + domain = bg_ptr->pdata->sensors[i].domain;
> + if (bg_ptr->pdata->expose_sensor)
> + bg_ptr->pdata->expose_sensor(bg_ptr, i, domain);
> + }
> +
> + return 0;
> +
> +put_clks:
> + clk_disable(bg_ptr->fclock);
> + clk_put(bg_ptr->fclock);
> + clk_put(bg_ptr->div_clk);
> +free_irqs:
> + free_irq(gpio_to_irq(bg_ptr->tshut_gpio), NULL);
> + gpio_free(bg_ptr->tshut_gpio);
> +free_talert:
> + free_irq(bg_ptr->irq, bg_ptr);
> +
> + return ret;
> +}
> +
> +static
> +int __devexit omap_bandgap_remove(struct platform_device *pdev)
> +{
> + struct omap_bandgap *bg_ptr = platform_get_drvdata(pdev);
> +
> + clk_disable(bg_ptr->fclock);
> + clk_put(bg_ptr->fclock);
> + clk_put(bg_ptr->div_clk);
> + free_irq(bg_ptr->irq, bg_ptr);
> + free_irq(gpio_to_irq(bg_ptr->tshut_gpio), NULL);
> + gpio_free(bg_ptr->tshut_gpio);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int omap_bandgap_save_ctxt(struct omap_bandgap *bg_ptr)
> +{
> + int err = 0;
> + int i;
> +
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + struct temp_sensor_registers *tsr;
> + struct temp_sensor_regval *rval;
> +
> + rval = bg_ptr->pdata->sensors[i].regval;
> + tsr = bg_ptr->pdata->sensors[i].registers;
> +
> + err = bg_readl(bg_ptr, tsr->bgap_mode_ctrl,
> + &rval->bg_mode_ctrl);
> + err |= bg_readl(bg_ptr, tsr->bgap_mask_ctrl,
> + &rval->bg_ctrl);
> + err |= bg_readl(bg_ptr, tsr->bgap_counter,
> + &rval->bg_counter);
> + err |= bg_readl(bg_ptr, tsr->bgap_threshold,
> + &rval->bg_threshold);
> + err |= bg_readl(bg_ptr, tsr->tshut_threshold,
> + &rval->tshut_threshold);
> +
> + if (err)
> + dev_err(bg_ptr->dev, "could not save sensor %d\n", i);
> + }
> +
> + return err ? -EIO : 0;
> +}
> +
> +static int
> +omap_bandgap_force_single_read(struct omap_bandgap *bg_ptr, int id)
> +{
> + struct temp_sensor_registers *tsr;
> + u32 temp = 0, counter = 1000;
> + int err;
> +
> + tsr = bg_ptr->pdata->sensors[id].registers;
> + /* Select single conversion mode */
> + err = bg_readl(bg_ptr, tsr->bgap_mode_ctrl, &temp);
> + temp &= ~(1 << __ffs(tsr->mode_ctrl_mask));
> + bg_writel(bg_ptr, temp, tsr->bgap_mode_ctrl, &tsr->bg_reg_lock);
> +
> + /* Start of Conversion = 1 */
> + err |= bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp |= 1 << __ffs(tsr->bgap_soc_mask);
> + bg_writel(bg_ptr, temp, tsr->temp_sensor_ctrl, &tsr->bg_reg_lock);
> + /* Wait until DTEMP is updated */
> + err |= bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= (tsr->bgap_dtemp_mask);
> + while ((temp == 0) && --counter) {
> + err |= bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= (tsr->bgap_dtemp_mask);
> + }
> + /* Start of Conversion = 0 */
> + err |= bg_readl(bg_ptr, tsr->temp_sensor_ctrl, &temp);
> + temp &= ~(1 << __ffs(tsr->bgap_soc_mask));
> + err |= bg_writel(bg_ptr, temp, tsr->temp_sensor_ctrl, &tsr->bg_reg_lock);
> +
> + return err ? -EIO : 0;
> +}
> +
> +static int omap_bandgap_restore_ctxt(struct omap_bandgap *bg_ptr)
> +{
> + int i, err = 0;
> + u32 temp = 0;
> +
> + for (i = 0; i < bg_ptr->pdata->sensor_count; i++) {
> + struct temp_sensor_registers *tsr;
> + struct temp_sensor_regval *rval;
> + u32 val = 0;
> +
> + rval = bg_ptr->pdata->sensors[i].regval;
> + tsr = bg_ptr->pdata->sensors[i].registers;
> +
> + err = bg_readl(bg_ptr, tsr->bgap_counter, &val);
> + if (val == 0) {
> + err |= bg_writel(bg_ptr, rval->bg_threshold,
> + tsr->bgap_threshold, &tsr->bg_reg_lock);
> + err |= bg_writel(bg_ptr, rval->tshut_threshold,
> + tsr->tshut_threshold, &tsr->bg_reg_lock);
> + /* Force immediate temperature measurement and update
> + * of the DTEMP field
> + */
> + omap_bandgap_force_single_read(bg_ptr, i);
> + err |= bg_writel(bg_ptr, rval->bg_counter,
> + tsr->bgap_counter, &tsr->bg_reg_lock);
> + err |= bg_writel(bg_ptr, rval->bg_mode_ctrl,
> + tsr->bgap_mode_ctrl, &tsr->bg_reg_lock);
> + err |= bg_writel(bg_ptr, rval->bg_ctrl,
> + tsr->bgap_mask_ctrl, &tsr->bg_reg_lock);
> + } else {
> + err |= bg_readl(bg_ptr, tsr->temp_sensor_ctrl,
> + &temp);
> + temp &= (tsr->bgap_dtemp_mask);
> + if (temp == 0) {
> + omap_bandgap_force_single_read(bg_ptr, i);
> + err |= bg_readl(bg_ptr, tsr->bgap_mask_ctrl,
> + &temp);
> + temp |= 1 << __ffs(tsr->mode_ctrl_mask);
> + err |= bg_writel(bg_ptr, temp,
> + tsr->bgap_mask_ctrl, &tsr->bg_reg_lock);
> + }
> + }
> + if (err)
> + dev_err(bg_ptr->dev, "could not save sensor %d\n", i);
> + }
> +
> + return err ? -EIO : 0;
> +}
> +
> +static int omap_bandgap_suspend(struct device *dev)
> +{
> + struct omap_bandgap *bg_ptr = dev_get_drvdata(dev);
> + int err;
> +
> + err = omap_bandgap_save_ctxt(bg_ptr);
> + clk_disable(bg_ptr->fclock);
> +
> + return err;
> +}
> +
> +static int omap_bandgap_resume(struct device *dev)
> +{
> + struct omap_bandgap *bg_ptr = dev_get_drvdata(dev);
> +
> + clk_enable(bg_ptr->fclock);
> +
> + return omap_bandgap_restore_ctxt(bg_ptr);
> +}
> +static const struct dev_pm_ops omap_bandgap_dev_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(omap_bandgap_suspend,
> + omap_bandgap_resume)
> +};
> +
> +#define DEV_PM_OPS (&omap_bandgap_dev_pm_ops)
> +#else
> +#define DEV_PM_OPS NULL
> +#endif
> +
> +static struct platform_driver omap_bandgap_sensor_driver = {
> + .probe = omap_bandgap_probe,
> + .remove = omap_bandgap_remove,
> + .driver = {
> + .name = "omap-bandgap",
> + .pm = DEV_PM_OPS,
> + .of_match_table = of_omap_bandgap_match,
> + },
> +};
> +
> +module_platform_driver(omap_bandgap_sensor_driver);
> +early_platform_init("early_omap_temperature", &omap_bandgap_sensor_driver);
> +
> +static int __init bg_init(void)
> +{
> + return platform_driver_register(&omap_bandgap_sensor_driver);
> +}
> +
> +static void __exit bg_exit(void)
> +{
> + platform_driver_unregister(&omap_bandgap_sensor_driver);
> +}
> +
> +module_init(bg_init);
> +module_exit(bg_exit);
> +
> +MODULE_DESCRIPTION("OMAP4+ bandgap temperature sensor driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:omap-bandgap");
> +MODULE_AUTHOR("Texas Instrument Inc.");
> diff --git a/drivers/thermal/omap-bandgap.h b/drivers/thermal/omap-bandgap.h
> new file mode 100644
> index 0000000..41f25ff
> --- /dev/null
> +++ b/drivers/thermal/omap-bandgap.h
> @@ -0,0 +1,64 @@
> +/*
> + * OMAP4 Bandgap temperature sensor driver
> + *
> + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> + * Contact:
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> + * 02110-1301 USA
> + *
> + */
> +#ifndef __OMAP_BANDGAP_H
> +#define __OMAP_BANDGAP_H
> +
> +struct omap_bandgap_data;
> +
> +/**
> + * struct omap_bandgap - bandgap device structure
> + * @dev: device pointer
> + * @pdata: platform data with sensor data
> + * @fclock: pointer to functional clock of temperature sensor
> + * @div_clk: pointer to parent clock of temperature sensor fclk
> + * @conv_table: Pointer to adc to temperature conversion table
> + * @bg_mutex: Mutex for sysfs, irq and PM
> + * @irq: MPU Irq number for thermal alert
> + * @tshut_gpio: GPIO where Tshut signal is routed
> + * @clk_rate: Holds current clock rate
> + */
> +struct omap_bandgap {
> + struct device *dev;
> + const struct omap_bandgap_data *pdata;
> + struct clk *fclock;
> + struct clk *div_clk;
> + const int *conv_table;
> + struct mutex bg_mutex; /* Mutex for irq and PM */
> + int irq;
> + int tshut_gpio;
> + u32 clk_rate;
> + void __iomem *bg_base;
> +};
> +
> +int omap_bandgap_read_thot(struct omap_bandgap *bg_ptr, int id, int *thot);
> +int omap_bandgap_write_thot(struct omap_bandgap *bg_ptr, int id, int val);
> +int omap_bandgap_read_tcold(struct omap_bandgap *bg_ptr, int id, int *tcold);
> +int omap_bandgap_write_tcold(struct omap_bandgap *bg_ptr, int id, int val);
> +int omap_bandgap_read_update_interval(struct omap_bandgap *bg_ptr, int id,
> + int *interval);
> +int omap_bandgap_write_update_interval(struct omap_bandgap *bg_ptr, int id,
> + u32 interval);
> +int omap_bandgap_read_temperature(struct omap_bandgap *bg_ptr, int id,
> + int *temperature);
> +
> +#endif
> --
> 1.7.7.6
>
>
^ permalink raw reply
* Re: [PATCH v3 4/7] mfd: omap: control: usb-phy: introduce the ctrl-module usb driver
From: Eduardo Valentin @ 2012-06-28 4:58 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B4C.9040501@dev.rtsoft.ru>
Hello,
On Wed, Jun 27, 2012 at 10:05:00PM +0400, Konstantin Baydarov wrote:
> Created a new platform driver for the platform device created by the
> control module mfd core, wrt usb. This driver has API's to power on/off
> the phy and the API's to write to musb mailbox.
>
> Changes since previous version:
> - Bandgap and usb phy: drivers are now independent from control module driver, they use
> their own functions to acess scm registers.
> - Parent SCM platform device IOMEM resources is used to get the base address of SCM window.
> - SCM Dependency was removed from Kconfig.
> - Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
>
> (p.s. the mailbox for musb in omap4 is present in system control
> module)
>
> [kishon@ti.com: wrote the original API's related to USB functions]
> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
> ---
> drivers/usb/otg/Kconfig | 12 +++
> drivers/usb/otg/Makefile | 1 +
> drivers/usb/otg/omap4-usb-phy.c | 170 +++++++++++++++++++++++++++++++++++++
> include/linux/usb/omap4_usb_phy.h | 53 ++++++++++++
> 4 files changed, 236 insertions(+), 0 deletions(-)
> create mode 100644 drivers/usb/otg/omap4-usb-phy.c
> create mode 100644 include/linux/usb/omap4_usb_phy.h
>
> diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
> index 5c87db0..0ed691b 100644
> --- a/drivers/usb/otg/Kconfig
> +++ b/drivers/usb/otg/Kconfig
> @@ -78,6 +78,18 @@ config TWL6030_USB
> are hooked to this driver through platform_data structure.
> The definition of internal PHY APIs are in the mach-omap2 layer.
>
> +config OMAP4_USB_PHY
> + tristate "Texas Instruments OMAP4+ USB pin control driver"
> + help
> + If you say yes here you get support for the Texas Instruments
> + OMAP4+ USB pin control driver. The register set is part of system
> + control module.
> +
> + USB phy in OMAP configures control module register for powering on
> + the phy, configuring VBUSVALID, AVALID, IDDIG and SESSEND. For
> + performing the above mentioned configuration, API's are added in
> + by this children of the control module driver.
> +
> config NOP_USB_XCEIV
> tristate "NOP USB Transceiver Driver"
> select USB_OTG_UTILS
> diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
> index 41aa509..60c8c83 100644
> --- a/drivers/usb/otg/Makefile
> +++ b/drivers/usb/otg/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_USB_GPIO_VBUS) += gpio_vbus.o
> obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o
> obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
> obj-$(CONFIG_TWL6030_USB) += twl6030-usb.o
> +obj-$(CONFIG_OMAP4_USB_PHY) += omap4-usb-phy.o
> obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-xceiv.o
> obj-$(CONFIG_USB_ULPI) += ulpi.o
> obj-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi_viewport.o
> diff --git a/drivers/usb/otg/omap4-usb-phy.c b/drivers/usb/otg/omap4-usb-phy.c
> new file mode 100644
> index 0000000..cbea2ea
> --- /dev/null
> +++ b/drivers/usb/otg/omap4-usb-phy.c
> @@ -0,0 +1,170 @@
> +/*
> + * OMAP4 system control module driver, USB control children
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * Contact:
> + * Kishon Vijay Abraham I <kishon@ti.com>
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> + * 02110-1301 USA
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/gpio.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/usb/omap4_usb_phy.h>
> +
> +void __iomem *omap_usb_phy_base;
> +spinlock_t omap_usb_phy_lock;
> +
> +static int omap_usb_phy_readl(u32 reg, u32 *val)
> +{
> + if (!omap_usb_phy_base)
> + return -EINVAL;
> +
> + *val = __raw_readl(omap_usb_phy_base + reg);
> + return 0;
> +}
> +
> +/*
> + * TODO: Get rid from omap_usb_phy_writel() return value -
> + * It's useless.
if you do that remember to keep a WARN_ON in case the base address is not set.
> + */
> +static int omap_usb_phy_writel(u32 val, u32 reg)
> +{
> + unsigned long flags;
> +
> + if (!omap_usb_phy_base)
> + return -EINVAL;
> +
> + spin_lock_irqsave(&omap_usb_phy_lock, flags);
> + __raw_writel(val, omap_usb_phy_base + reg);
> + spin_unlock_irqrestore(&omap_usb_phy_lock, flags);
I think it is better to lock per operation than per write.
> + return 0;
> +}
> +
> +/**
> + * omap4_usb_phy_power - power on/off the phy using control module reg
> + * @dev: struct device *
> + * @on: 0 or 1, based on powering on or off the PHY
> + *
> + * omap_usb2 can call this API to power on or off the PHY.
> + */
> +int omap4_usb_phy_power(struct device *dev, int on)
> +{
> + u32 val;
> + int ret;
> +
> + if (on) {
> + ret = omap_usb_phy_readl(CONTROL_DEV_CONF, &val);
> + if (!ret && (val & PHY_PD)) {
> + ret = omap_usb_phy_writel(~PHY_PD,
> + CONTROL_DEV_CONF);
> + /* XXX: add proper documentation for this delay */
> + mdelay(200);
> + }
> + } else
> + ret = omap_usb_phy_writel(PHY_PD, CONTROL_DEV_CONF);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(omap4_usb_phy_power);
> +
> +/**
> + * omap4_usb_phy_mailbox - write to usb otg mailbox
> + * @dev: struct device *
> + * @val: the value to be written to the mailbox
> + *
> + * On detection of a device (ID pin is grounded), the phy should call this API
> + * to set AVALID, VBUSVALID and ID pin is grounded.
> + *
> + * When OMAP is connected to a host (OMAP in device mode), the phy should call
> + * this API to set AVALID, VBUSVALID and ID pin in high impedance.
> + *
> + * The phy should call this API, if OMAP is disconnected from host or device.
> + */
> +int omap4_usb_phy_mailbox(struct device *dev, u32 val)
> +{
> + return omap_usb_phy_writel(val, CONTROL_USBOTGHS_CONTROL);
> +}
> +EXPORT_SYMBOL_GPL(omap4_usb_phy_mailbox);
> +
> +static int __devinit omap_usb_phy_probe(struct platform_device *pdev)
> +{
> + struct resource *io_res;
> + struct platform_device *pparent;
> +
> + if (!pdev->dev.parent) {
> + dev_err(&pdev->dev, "No parent device!\n");
> + return -ENOMEM;
> + }
> +
> + pparent = to_platform_device(pdev->dev.parent);
> +
> + io_res = platform_get_resource(pparent, IORESOURCE_MEM, 0);
Can someone please explain me what do we gain by doing this at children code?
> + if (!io_res)
> + return -ENOENT;
> +
> + omap_usb_phy_base = ioremap(io_res->start, resource_size(io_res));
> + if (!omap_usb_phy_base)
> + return -ENOMEM;
> +
> + /* Initialize register lock */
> + spin_lock_init(&omap_usb_phy_lock);
> +
> + return 0;
> +}
> +
> +static int __devexit omap_usb_phy_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id of_omap_usb_phy_match[] = {
> + { .compatible = "ti,omap4-usb-phy", },
> + { },
> +};
> +
> +static struct platform_driver omap_usb_phy_driver = {
> + .probe = omap_usb_phy_probe,
> + .remove = __devexit_p(omap_usb_phy_remove),
> + .driver = {
> + .name = "omap4-usb-phy",
> + .owner = THIS_MODULE,
> + .of_match_table = of_omap_usb_phy_match,
> + },
> +};
> +
> +static int __init omap_usb_phy_init(void)
> +{
> + return platform_driver_register(&omap_usb_phy_driver);
> +}
> +postcore_initcall(omap_usb_phy_init);
> +
> +static void __exit omap_usb_phy_exit(void)
> +{
> + platform_driver_unregister(&omap_usb_phy_driver);
> +}
> +module_exit(omap_usb_phy_exit);
> +
> +MODULE_DESCRIPTION("OMAP4+ USB-phy driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform: omap4-usb-phy");
> +MODULE_AUTHOR("Texas Instrument Inc.");
> diff --git a/include/linux/usb/omap4_usb_phy.h b/include/linux/usb/omap4_usb_phy.h
> new file mode 100644
> index 0000000..b6a4701
> --- /dev/null
> +++ b/include/linux/usb/omap4_usb_phy.h
> @@ -0,0 +1,53 @@
> +/*
> + * OMAP4 USB-phy
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * Contact:
> + * Kishon Vijay Abraham I <kishon@ti.com>
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> + * 02110-1301 USA
> + *
> + */
> +
> +#ifndef __OMAP4_USB_PHY_H
> +#define __OMAP4_USB_PHY_H
> +
> +#define PHY_PD 0x1
> +#define AVALID BIT(0)
> +#define BVALID BIT(1)
> +#define VBUSVALID BIT(2)
> +#define SESSEND BIT(3)
> +#define IDDIG BIT(4)
> +#define CONTROL_DEV_CONF 0x00000300
> +#define CONTROL_USBOTGHS_CONTROL 0x0000033C
> +
> +/* USB-PHY helpers */
> +#if (defined(CONFIG_OMAP4_USB_PHY)) || (defined(CONFIG_OMAP4_USB_PHY_MODULE))
> +extern int omap4_usb_phy_mailbox(struct device *dev, u32 val);
> +extern int omap4_usb_phy_power(struct device *dev, int on);
> +#else
> +static inline int omap4_usb_phy_mailbox(struct device *dev, u32 val)
> +{
> + return 0;
> +}
> +static inline int omap4_usb_phy_power(struct device *dev, int on)
> +{
> + return 0;
> +}
> +#endif
> +
> +#endif
> --
> 1.7.7.6
>
>
^ permalink raw reply
* Re: [PATCH v3 2/7] mfd: omap: control: core system control driver
From: Eduardo Valentin @ 2012-06-28 4:50 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B46.9020904@dev.rtsoft.ru>
Hello,
On Wed, Jun 27, 2012 at 10:04:54PM +0400, Konstantin Baydarov wrote:
> This patch introduces a MFD core device driver for OMAP system control module.
>
> The control module allows software control of various static modes supported by the device.
> It is composed of two control submodules: general control module and device (padconfiguration) control module.
>
> Changes since previous version:
> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
> Probably, no configuration option is required!
> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
> module device.
> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
> - omap-control-core: added omap_control_status_read that is used early in omap_type
>
> Signed-off-by: Konstantin Baydarov <kbaidarov@dev.rtsoft.ru>
> Signed-off-by: J Keerthy <j-keerthy@ti.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
> ---
> .../devicetree/bindings/mfd/omap_control.txt | 44 +++++++
> arch/arm/mach-omap2/Kconfig | 1 +
> arch/arm/plat-omap/Kconfig | 4 +
> drivers/mfd/Kconfig | 9 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/omap-control-core.c | 131 ++++++++++++++++++++
> include/linux/mfd/omap_control.h | 52 ++++++++
> 7 files changed, 242 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/omap_control.txt
> create mode 100644 drivers/mfd/omap-control-core.c
> create mode 100644 include/linux/mfd/omap_control.h
>
> diff --git a/Documentation/devicetree/bindings/mfd/omap_control.txt b/Documentation/devicetree/bindings/mfd/omap_control.txt
> new file mode 100644
> index 0000000..46d5e7e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/omap_control.txt
> @@ -0,0 +1,44 @@
> +* Texas Instrument OMAP System Control Module (SCM) bindings
> +
> +The control module allows software control of various static modes supported by
> +the device. The control module controls the settings of various device modules
> +through register configuration and internal signals. It also controls the pad
> +configuration, pin functional multiplexing, and the routing of internal signals
> +(such as PRCM signals or DMA requests) to output pins configured for hardware
> +observability.
> +
> +Required properties:
> +- compatible : Should be:
> + - "ti,omap3-control" for OMAP3 support
> + - "ti,omap4-control" for OMAP4 support
> + - "ti,omap5-control" for OMAP5 support
> +
> +OMAP specific properties:
> +- ti,hwmods: Name of the hwmod associated to the control module:
> + Should be "ctrl_module_core";
> +
> +Sub-nodes:
> +- bandgap : contains the bandgap node
> +
> + The bindings details of individual bandgap device can be found in:
> + Documentation/devicetree/bindings/thermal/omap_bandgap.txt
> +
> +- usb : contains the usb phy pin control node
> +
> + The only required property for this child is:
> + - compatible = "ti,omap4-control-usb";
> +
> +Examples:
> +
> +ctrl_module_core: ctrl_module_core@4a002000 {
> + compatible = "ti,omap4-control";
> + ti,hwmods = "ctrl_module_core";
> + bandgap {
> + compatible = "ti,omap4460-bandgap";
You need to update the documentation if change the DT structure.
> + interrupts = <0 126 4>; /* talert */
> + ti,tshut-gpio = <86>; /* tshut */
> + };
> + usb {
> + compatible = "ti,omap4-usb-phy";
> + };
> +};
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 4cf5142..c2ef07c 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -52,6 +52,7 @@ config ARCH_OMAP4
> select PL310_ERRATA_727915
> select ARM_ERRATA_720789
> select ARCH_HAS_OPP
> + select ARCH_HAS_CONTROL_MODULE
> select PM_OPP if PM
> select USB_ARCH_HAS_EHCI if USB_SUPPORT
> select ARM_CPU_SUSPEND if PM
> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> index ad95c7a..0f9b575 100644
> --- a/arch/arm/plat-omap/Kconfig
> +++ b/arch/arm/plat-omap/Kconfig
> @@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
> config ARCH_OMAP_OTG
> bool
>
> +config ARCH_HAS_CONTROL_MODULE
> + bool
> + select MFD_OMAP_CONTROL
> +
OK now I got what you meant in patch 0. Fine for me.
> choice
> prompt "OMAP System Type"
> default ARCH_OMAP2PLUS
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index e129c82..d0c5456 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -822,6 +822,15 @@ config MFD_WL1273_CORE
> driver connects the radio-wl1273 V4L2 module and the wl1273
> audio codec.
>
> +config MFD_OMAP_CONTROL
> + bool "Texas Instruments OMAP System control module"
> + depends on ARCH_HAS_CONTROL_MODULE
> + help
> + This is the core driver for system control module. This driver
> + is responsible for creating the control module mfd child,
> + like USB-pin control, pin muxing, MMC-pbias and DDR IO dynamic
> + change for off mode.
> +
> config MFD_OMAP_USB_HOST
> bool "Support OMAP USBHS core driver"
> depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 75f6ed6..b037443 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
> obj-$(CONFIG_MFD_VX855) += vx855.o
> obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
> obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
> +obj-$(CONFIG_MFD_OMAP_CONTROL) += omap-control-core.o
> obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
> obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
> obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
> diff --git a/drivers/mfd/omap-control-core.c b/drivers/mfd/omap-control-core.c
> new file mode 100644
> index 0000000..724c51b
> --- /dev/null
> +++ b/drivers/mfd/omap-control-core.c
> @@ -0,0 +1,131 @@
> +/*
> + * OMAP system control module driver file
> + *
> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Contacts:
> + * Based on original code written by:
> + * J Keerthy <j-keerthy@ti.com>
> + * Moiz Sonasath <m-sonasath@ti.com>
> + * MFD clean up and re-factoring:
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/export.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/core.h>
> +#include <linux/mfd/omap_control.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +void __iomem *omap_control_base;
> +
> +u32 omap_control_status_read(u16 offset)
> +{
> + return __raw_readl(omap_control_base + (offset));
> +}
> +
> +static const struct of_device_id of_omap_control_match[] = {
> + { .compatible = "ti,omap3-control", },
> + { .compatible = "ti,omap4-control", },
> + { .compatible = "ti,omap5-control", },
> + { },
> +};
> +
> +static int __devinit omap_control_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> +
> + /*
> + * Build child defvices of ctrl_module_core
> + */
> + return of_platform_populate(np, of_omap_control_match, NULL, dev);
> +}
> +
> +
> +static struct platform_driver omap_control_driver = {
> + .probe = omap_control_probe,
> + .driver = {
> + .name = "omap-control-core",
> + .owner = THIS_MODULE,
> + .of_match_table = of_omap_control_match,
> + },
> +};
> +
> +int __init omap_control_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct resource res;
> +
> + if (WARN_ON(!node))
> + return -ENODEV;
> +
> + if (of_address_to_resource(node, 0, &res)) {
> + WARN(1, "unable to get intc registers\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
The above function is used nowhere.
> +
> +void __init of_omap_control_init(const struct of_device_id *matches)
> +{
> + struct device_node *np;
> + struct property *pp = 0;
> + unsigned long phys_base = 0;
> + size_t mapsize = 0;
> +
> + for_each_matching_node(np, matches) {
> +
> + pp = of_find_property(np, "reg", NULL);
> + if(pp) {
> + phys_base = (unsigned long)be32_to_cpup(pp->value);
> + mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
> + omap_control_base = ioremap(phys_base, mapsize);
How the reservation is going to work?
> + }
> + }
> +}
> +
> +static int __init
> +omap_control_early_initcall(void)
> +{
> + of_omap_control_init(of_omap_control_match);
> +
> + return 0;
> +}
> +early_initcall(omap_control_early_initcall);
> +
> +static int __init omap_control_init(void)
> +{
> + return platform_driver_register(&omap_control_driver);
> +}
> +postcore_initcall_sync(omap_control_init);
> +
> +static void __exit omap_control_exit(void)
> +{
> + platform_driver_unregister(&omap_control_driver);
> +}
> +module_exit(omap_control_exit);
> +early_platform_init("early_omap_control", &omap_control_driver);
early_platform_init is not needed as you are implementing the early reads in a different way.
> +
> +MODULE_DESCRIPTION("OMAP system control module driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:omap-control-core");
> +MODULE_AUTHOR("Texas Instruments Inc.");
> diff --git a/include/linux/mfd/omap_control.h b/include/linux/mfd/omap_control.h
> new file mode 100644
> index 0000000..1795403
> --- /dev/null
> +++ b/include/linux/mfd/omap_control.h
> @@ -0,0 +1,52 @@
> +/*
> + * OMAP system control module header file
> + *
> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Contact:
> + * J Keerthy <j-keerthy@ti.com>
> + * Moiz Sonasath <m-sonasath@ti.com>
> + * Abraham, Kishon Vijay <kishon@ti.com>
> + * Eduardo Valentin <eduardo.valentin@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + */
> +
> +#ifndef __DRIVERS_OMAP_CONTROL_H
> +#define __DRIVERS_OMAP_CONTROL_H
> +
> +#include <linux/err.h>
> +
> +/**
> + * struct system control module - scm device structure
> + * @dev: device pointer
> + * @base: Base of the temp I/O
> + * @reg_lock: protect omap_control structure
> + * @use_count: track API users
> + */
> +struct omap_control {
> + struct device *dev;
> + void __iomem *base;
> + /* protect this data structure and register access */
> + spinlock_t reg_lock;
> + int use_count;
I suppose the reg_lock and the use_count are not needed in this design?
> +};
> +
> +/* TODO: Add helpers for 16bit and byte access */
> +#ifdef CONFIG_MFD_OMAP_CONTROL
> +u32 omap_control_status_read(u16 offset);
> +#else
> +static inline u32 omap_control_status_read(u16 offset)
> +{
> + return 0;
> +}
> +#endif
> +
> +#endif /* __DRIVERS_OMAP_CONTROL_H */
> --
> 1.7.7.6
>
>
^ permalink raw reply
* Re: [PATCH v3 1/7] ARM: OMAP4: Remove un-used control module headers and defines.
From: Eduardo Valentin @ 2012-06-28 4:45 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B3F.1090608@dev.rtsoft.ru>
Why the authorship of these patches is changing?
For instance this patch, from Santosh, I believe it is the same...
On Wed, Jun 27, 2012 at 10:04:47PM +0400, Konstantin Baydarov wrote:
> Most of the OMAP4 control module register defines are not used and
> can be removed. Keep only needed defines and move them to common
> control module header just like other OMAP versions.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 45 +-
> .../include/mach/ctrl_module_core_44xx.h | 391 ------
> .../include/mach/ctrl_module_pad_core_44xx.h | 1409 --------------------
> .../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ----
> .../include/mach/ctrl_module_wkup_44xx.h | 92 --
> 5 files changed, 40 insertions(+), 2133 deletions(-)
> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
> delete mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a406fd0..dad2903 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -16,11 +16,6 @@
> #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
> #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
>
> -#include <mach/ctrl_module_core_44xx.h>
> -#include <mach/ctrl_module_wkup_44xx.h>
> -#include <mach/ctrl_module_pad_core_44xx.h>
> -#include <mach/ctrl_module_pad_wkup_44xx.h>
> -
> #ifndef __ASSEMBLY__
> #define OMAP242X_CTRL_REGADDR(reg) \
> OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
> @@ -183,6 +178,43 @@
> #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
> #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
>
> +/* OMAP4 IDCODE CONTROL */
> +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
> +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
> +
> +/* CONTROL_I2C_1 */
> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
> +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
> +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
> +
> +/* DSI CONTROL_DSIPHY */
> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
> +#define OMAP4_DSI2_LANEENABLE_SHIFT 29
> +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
> +#define OMAP4_DSI1_LANEENABLE_SHIFT 24
> +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
> +#define OMAP4_DSI1_PIPD_SHIFT 19
> +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
> +#define OMAP4_DSI2_PIPD_SHIFT 14
> +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
> +
> +/* CONTROL_PBIASLITE */
> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
> +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
> +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
> +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
> +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
> +
> +/* CONTROL_MMC1 */
> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
> +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
> +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
> +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
> +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
> +
> /* OMAP44xx control efuse offsets */
> #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
> #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
> @@ -195,6 +227,9 @@
> #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
> #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
>
> +/* OMAP44xx control McBSP padconf */
> +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
> +
> /* AM35XX only CONTROL_GENERAL register offsets */
> #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
> #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
> deleted file mode 100644
> index 2f7ac70..0000000
> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
> +++ /dev/null
> @@ -1,391 +0,0 @@
> -/*
> - * OMAP44xx CTRL_MODULE_CORE registers and bitfields
> - *
> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
> - *
> - * Benoit Cousson (b-cousson@ti.com)
> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
> - *
> - * This file is automatically generated from the OMAP hardware databases.
> - * We respectfully ask that any modifications to this file be coordinated
> - * with the public linux-omap@vger.kernel.org mailing list and the
> - * authors above to ensure that the autogeneration scripts are kept
> - * up-to-date with the file contents.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
> -
> -
> -/* Base address */
> -#define OMAP4_CTRL_MODULE_CORE 0x4a002000
> -
> -/* Registers offset */
> -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
> -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
> -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
> -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
> -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
> -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
> -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
> -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
> -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
> -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
> -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
> -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
> -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
> -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
> -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
> -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
> -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
> -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
> -
> -/* Registers shifts and masks */
> -
> -/* IP_REVISION */
> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
> -#define OMAP4_IP_REV_FUNC_SHIFT 16
> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
> -#define OMAP4_IP_REV_RTL_SHIFT 11
> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
> -#define OMAP4_IP_REV_MINOR_SHIFT 0
> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
> -
> -/* IP_HWINFO */
> -#define OMAP4_IP_HWINFO_SHIFT 0
> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
> -
> -/* IP_SYSCONFIG */
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
> -
> -/* STD_FUSE_DIE_ID_0 */
> -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
> -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
> -
> -/* ID_CODE */
> -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
> -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_DIE_ID_1 */
> -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
> -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_DIE_ID_2 */
> -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
> -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_DIE_ID_3 */
> -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
> -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_PROD_ID_0 */
> -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
> -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_PROD_ID_1 */
> -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
> -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_USB_CONF */
> -#define OMAP4_USB_PROD_ID_SHIFT 16
> -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
> -#define OMAP4_USB_VENDOR_ID_SHIFT 0
> -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
> -
> -/* STD_FUSE_OPP_VDD_WKUP */
> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
> -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_OPP_BGAP */
> -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
> -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_OPP_DPLL_0 */
> -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
> -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
> -
> -/* STD_FUSE_OPP_DPLL_1 */
> -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
> -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
> -
> -/* STATUS */
> -#define OMAP4_ATTILA_CONF_SHIFT 11
> -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
> -#define OMAP4_DEVICE_TYPE_SHIFT 8
> -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
> -#define OMAP4_SYS_BOOT_SHIFT 0
> -#define OMAP4_SYS_BOOT_MASK (0xff << 0)
> -
> -/* DEV_CONF */
> -#define OMAP4_DEV_CONF_SHIFT 1
> -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
> -#define OMAP4_USBPHY_PD_SHIFT 0
> -#define OMAP4_USBPHY_PD_MASK (1 << 0)
> -
> -/* LDOVBB_IVA_VOLTAGE_CTRL */
> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
> -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
> -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
> -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
> -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
> -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
> -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
> -
> -/* LDOVBB_MPU_VOLTAGE_CTRL */
> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
> -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
> -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
> -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
> -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
> -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
> -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
> -
> -/* LDOSRAM_IVA_VOLTAGE_CTRL */
> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
> -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
> -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
> -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
> -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
> -
> -/* LDOSRAM_MPU_VOLTAGE_CTRL */
> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
> -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
> -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
> -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
> -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
> -
> -/* LDOSRAM_CORE_VOLTAGE_CTRL */
> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
> -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
> -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
> -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
> -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
> -
> -/* TEMP_SENSOR */
> -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
> -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
> -#define OMAP4_BGAP_TSHUT_SHIFT 11
> -#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
> -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
> -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
> -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
> -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
> -
> -/* DPLL_NWELL_TRIM_0 */
> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
> -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
> -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
> -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
> -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
> -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
> -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
> -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
> -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
> -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
> -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
> -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
> -
> -/* DPLL_NWELL_TRIM_1 */
> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
> -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
> -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
> -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
> -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
> -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
> -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
> -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
> -
> -/* USBOTGHS_CONTROL */
> -#define OMAP4_DISCHRGVBUS_SHIFT 8
> -#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
> -#define OMAP4_CHRGVBUS_SHIFT 7
> -#define OMAP4_CHRGVBUS_MASK (1 << 7)
> -#define OMAP4_DRVVBUS_SHIFT 6
> -#define OMAP4_DRVVBUS_MASK (1 << 6)
> -#define OMAP4_IDPULLUP_SHIFT 5
> -#define OMAP4_IDPULLUP_MASK (1 << 5)
> -#define OMAP4_IDDIG_SHIFT 4
> -#define OMAP4_IDDIG_MASK (1 << 4)
> -#define OMAP4_SESSEND_SHIFT 3
> -#define OMAP4_SESSEND_MASK (1 << 3)
> -#define OMAP4_VBUSVALID_SHIFT 2
> -#define OMAP4_VBUSVALID_MASK (1 << 2)
> -#define OMAP4_BVALID_SHIFT 1
> -#define OMAP4_BVALID_MASK (1 << 1)
> -#define OMAP4_AVALID_SHIFT 0
> -#define OMAP4_AVALID_MASK (1 << 0)
> -
> -/* DSS_CONTROL */
> -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
> -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
> -
> -/* HWOBS_CONTROL */
> -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
> -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
> -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
> -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
> -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
> -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
> -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
> -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
> -
> -/* DEBOBS_FINAL_MUX_SEL */
> -#define OMAP4_SELECT_SHIFT 0
> -#define OMAP4_SELECT_MASK (0xffffffff << 0)
> -
> -/* DEBOBS_MMR_MPU */
> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
> -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
> -
> -/* CONF_SDMA_REQ_SEL0 */
> -#define OMAP4_MULT_SHIFT 0
> -#define OMAP4_MULT_MASK (0x7f << 0)
> -
> -/* CONF_CLK_SEL0 */
> -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
> -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
> -
> -/* CONF_CLK_SEL1 */
> -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
> -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
> -
> -/* CONF_CLK_SEL2 */
> -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
> -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
> -
> -/* CONF_DPLL_FREQLOCK_SEL */
> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
> -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
> -
> -/* CONF_DPLL_TINITZ_SEL */
> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
> -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
> -
> -/* CONF_DPLL_PHASELOCK_SEL */
> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
> -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
> -
> -/* CONF_DEBUG_SEL_TST_0 */
> -#define OMAP4_MODE_SHIFT 0
> -#define OMAP4_MODE_MASK (0xf << 0)
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
> deleted file mode 100644
> index c88420d..0000000
> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
> +++ /dev/null
> @@ -1,1409 +0,0 @@
> -/*
> - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
> - *
> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
> - *
> - * Benoit Cousson (b-cousson@ti.com)
> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
> - *
> - * This file is automatically generated from the OMAP hardware databases.
> - * We respectfully ask that any modifications to this file be coordinated
> - * with the public linux-omap@vger.kernel.org mailing list and the
> - * authors above to ensure that the autogeneration scripts are kept
> - * up-to-date with the file contents.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
> -
> -
> -/* Base address */
> -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
> -
> -/* Registers offset */
> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
> -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
> -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
> -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
> -
> -/* Registers shifts and masks */
> -
> -/* IP_REVISION */
> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
> -#define OMAP4_IP_REV_FUNC_SHIFT 16
> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
> -#define OMAP4_IP_REV_RTL_SHIFT 11
> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
> -#define OMAP4_IP_REV_MINOR_SHIFT 0
> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
> -
> -/* IP_HWINFO */
> -#define OMAP4_IP_HWINFO_SHIFT 0
> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
> -
> -/* IP_SYSCONFIG */
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
> -
> -/* PADCONF_WAKEUPEVENT_0 */
> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_1 */
> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_2 */
> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_3 */
> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_4 */
> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_5 */
> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
> -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
> -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
> -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
> -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
> -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
> -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
> -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* PADCONF_WAKEUPEVENT_6 */
> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* CONTROL_PADCONF_GLOBAL */
> -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
> -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
> -
> -/* CONTROL_PADCONF_MODE */
> -#define OMAP4_VDDS_DV_BANK0_SHIFT 31
> -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
> -#define OMAP4_VDDS_DV_BANK1_SHIFT 30
> -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
> -#define OMAP4_VDDS_DV_BANK3_SHIFT 29
> -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
> -#define OMAP4_VDDS_DV_BANK4_SHIFT 28
> -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
> -#define OMAP4_VDDS_DV_BANK5_SHIFT 27
> -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
> -#define OMAP4_VDDS_DV_BANK6_SHIFT 26
> -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
> -#define OMAP4_VDDS_DV_C2C_SHIFT 25
> -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
> -#define OMAP4_VDDS_DV_CAM_SHIFT 24
> -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
> -#define OMAP4_VDDS_DV_GPMC_SHIFT 23
> -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
> -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
> -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
> -
> -/* CONTROL_SMART1IO_PADCONF_0 */
> -#define OMAP4_ABE_DR0_SC_SHIFT 30
> -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
> -#define OMAP4_CAM_DR0_SC_SHIFT 28
> -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
> -#define OMAP4_FREF_DR2_SC_SHIFT 26
> -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
> -#define OMAP4_FREF_DR3_SC_SHIFT 24
> -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
> -#define OMAP4_GPIO_DR8_SC_SHIFT 22
> -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
> -#define OMAP4_GPIO_DR9_SC_SHIFT 20
> -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
> -#define OMAP4_GPMC_DR2_SC_SHIFT 18
> -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
> -#define OMAP4_GPMC_DR3_SC_SHIFT 16
> -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
> -#define OMAP4_GPMC_DR6_SC_SHIFT 14
> -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
> -#define OMAP4_HDMI_DR0_SC_SHIFT 12
> -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
> -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
> -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
> -#define OMAP4_UART1_DR0_SC_SHIFT 8
> -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
> -#define OMAP4_UART3_DR0_SC_SHIFT 6
> -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
> -#define OMAP4_UART3_DR1_SC_SHIFT 4
> -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
> -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
> -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
> -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
> -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
> -
> -/* CONTROL_SMART1IO_PADCONF_1 */
> -#define OMAP4_ABE_DR0_LB_SHIFT 30
> -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
> -#define OMAP4_CAM_DR0_LB_SHIFT 28
> -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
> -#define OMAP4_FREF_DR2_LB_SHIFT 26
> -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
> -#define OMAP4_FREF_DR3_LB_SHIFT 24
> -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
> -#define OMAP4_GPIO_DR8_LB_SHIFT 22
> -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
> -#define OMAP4_GPIO_DR9_LB_SHIFT 20
> -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
> -#define OMAP4_GPMC_DR2_LB_SHIFT 18
> -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
> -#define OMAP4_GPMC_DR3_LB_SHIFT 16
> -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
> -#define OMAP4_GPMC_DR6_LB_SHIFT 14
> -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
> -#define OMAP4_HDMI_DR0_LB_SHIFT 12
> -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
> -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
> -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
> -#define OMAP4_UART1_DR0_LB_SHIFT 8
> -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
> -#define OMAP4_UART3_DR0_LB_SHIFT 6
> -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
> -#define OMAP4_UART3_DR1_LB_SHIFT 4
> -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
> -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
> -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
> -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
> -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
> -
> -/* CONTROL_SMART2IO_PADCONF_0 */
> -#define OMAP4_C2C_DR0_LB_SHIFT 31
> -#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
> -#define OMAP4_DPM_DR1_LB_SHIFT 30
> -#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
> -#define OMAP4_DPM_DR2_LB_SHIFT 29
> -#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
> -#define OMAP4_DPM_DR3_LB_SHIFT 28
> -#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
> -#define OMAP4_GPIO_DR0_LB_SHIFT 27
> -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
> -#define OMAP4_GPIO_DR1_LB_SHIFT 26
> -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
> -#define OMAP4_GPIO_DR10_LB_SHIFT 25
> -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
> -#define OMAP4_GPIO_DR2_LB_SHIFT 24
> -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
> -#define OMAP4_GPMC_DR0_LB_SHIFT 23
> -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
> -#define OMAP4_GPMC_DR1_LB_SHIFT 22
> -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
> -#define OMAP4_GPMC_DR4_LB_SHIFT 21
> -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
> -#define OMAP4_GPMC_DR5_LB_SHIFT 20
> -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
> -#define OMAP4_GPMC_DR7_LB_SHIFT 19
> -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
> -#define OMAP4_HSI2_DR0_LB_SHIFT 18
> -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
> -#define OMAP4_HSI2_DR1_LB_SHIFT 17
> -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
> -#define OMAP4_HSI2_DR2_LB_SHIFT 16
> -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
> -#define OMAP4_KPD_DR0_LB_SHIFT 15
> -#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
> -#define OMAP4_KPD_DR1_LB_SHIFT 14
> -#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
> -#define OMAP4_PDM_DR0_LB_SHIFT 13
> -#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
> -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
> -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
> -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
> -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
> -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
> -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
> -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
> -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
> -#define OMAP4_SPI3_DR0_LB_SHIFT 8
> -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
> -#define OMAP4_SPI3_DR1_LB_SHIFT 7
> -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
> -#define OMAP4_UART3_DR2_LB_SHIFT 6
> -#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
> -#define OMAP4_UART3_DR3_LB_SHIFT 5
> -#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
> -#define OMAP4_UART3_DR4_LB_SHIFT 4
> -#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
> -#define OMAP4_UART3_DR5_LB_SHIFT 3
> -#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
> -#define OMAP4_USBA0_DR1_LB_SHIFT 2
> -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
> -#define OMAP4_USBA_DR2_LB_SHIFT 1
> -#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
> -
> -/* CONTROL_SMART2IO_PADCONF_1 */
> -#define OMAP4_USBB1_DR0_LB_SHIFT 31
> -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
> -#define OMAP4_USBB2_DR0_LB_SHIFT 30
> -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
> -#define OMAP4_USBA0_DR0_LB_SHIFT 29
> -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
> -
> -/* CONTROL_SMART3IO_PADCONF_0 */
> -#define OMAP4_DMIC_DR0_MB_SHIFT 30
> -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
> -#define OMAP4_GPIO_DR3_MB_SHIFT 28
> -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
> -#define OMAP4_GPIO_DR4_MB_SHIFT 26
> -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
> -#define OMAP4_GPIO_DR5_MB_SHIFT 24
> -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
> -#define OMAP4_GPIO_DR6_MB_SHIFT 22
> -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
> -#define OMAP4_HSI_DR1_MB_SHIFT 20
> -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
> -#define OMAP4_HSI_DR2_MB_SHIFT 18
> -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
> -#define OMAP4_HSI_DR3_MB_SHIFT 16
> -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
> -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
> -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
> -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
> -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
> -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
> -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
> -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
> -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
> -#define OMAP4_SPI2_DR0_MB_SHIFT 0
> -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
> -
> -/* CONTROL_SMART3IO_PADCONF_1 */
> -#define OMAP4_SPI2_DR1_MB_SHIFT 30
> -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
> -#define OMAP4_SPI2_DR2_MB_SHIFT 28
> -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
> -#define OMAP4_UART2_DR0_MB_SHIFT 26
> -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
> -#define OMAP4_UART2_DR1_MB_SHIFT 24
> -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
> -#define OMAP4_UART4_DR0_MB_SHIFT 22
> -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
> -#define OMAP4_HSI_DR0_MB_SHIFT 20
> -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
> -
> -/* CONTROL_SMART3IO_PADCONF_2 */
> -#define OMAP4_DMIC_DR0_LB_SHIFT 31
> -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
> -#define OMAP4_GPIO_DR3_LB_SHIFT 30
> -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
> -#define OMAP4_GPIO_DR4_LB_SHIFT 29
> -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
> -#define OMAP4_GPIO_DR5_LB_SHIFT 28
> -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
> -#define OMAP4_GPIO_DR6_LB_SHIFT 27
> -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
> -#define OMAP4_HSI_DR1_LB_SHIFT 26
> -#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
> -#define OMAP4_HSI_DR2_LB_SHIFT 25
> -#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
> -#define OMAP4_HSI_DR3_LB_SHIFT 24
> -#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
> -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
> -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
> -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
> -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
> -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
> -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
> -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
> -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
> -#define OMAP4_SPI2_DR0_LB_SHIFT 16
> -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
> -#define OMAP4_SPI2_DR1_LB_SHIFT 15
> -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
> -#define OMAP4_SPI2_DR2_LB_SHIFT 14
> -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
> -#define OMAP4_UART2_DR0_LB_SHIFT 13
> -#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
> -#define OMAP4_UART2_DR1_LB_SHIFT 12
> -#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
> -#define OMAP4_UART4_DR0_LB_SHIFT 11
> -#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
> -#define OMAP4_HSI_DR0_LB_SHIFT 10
> -#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
> -
> -/* CONTROL_USBB_HSIC */
> -#define OMAP4_USBB2_DR1_SR_SHIFT 30
> -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
> -#define OMAP4_USBB2_DR1_I_SHIFT 27
> -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
> -#define OMAP4_USBB1_DR1_SR_SHIFT 25
> -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
> -#define OMAP4_USBB1_DR1_I_SHIFT 22
> -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
> -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
> -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
> -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
> -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
> -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
> -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
> -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
> -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
> -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
> -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
> -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
> -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
> -
> -/* CONTROL_SLIMBUS */
> -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
> -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
> -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
> -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
> -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
> -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
> -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
> -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
> -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
> -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
> -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
> -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
> -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
> -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
> -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
> -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
> -
> -/* CONTROL_PBIASLITE */
> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
> -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
> -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
> -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
> -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
> -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
> -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
> -#define OMAP4_MMC1_PWRDNZ_SHIFT 26
> -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
> -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
> -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
> -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
> -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
> -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
> -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
> -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
> -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
> -
> -/* CONTROL_I2C_0 */
> -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
> -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
> -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
> -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
> -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
> -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
> -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
> -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
> -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
> -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
> -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
> -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
> -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
> -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
> -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
> -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
> -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
> -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
> -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
> -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
> -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
> -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
> -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
> -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
> -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
> -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
> -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
> -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
> -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
> -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
> -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
> -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
> -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
> -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
> -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
> -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
> -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
> -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
> -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
> -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
> -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
> -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
> -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
> -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
> -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
> -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
> -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
> -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
> -
> -/* CONTROL_CAMERA_RX */
> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
> -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
> -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
> -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
> -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
> -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
> -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
> -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
> -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
> -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
> -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
> -
> -/* CONTROL_AVDAC */
> -#define OMAP4_AVDAC_ACEN_SHIFT 31
> -#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
> -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
> -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
> -#define OMAP4_AVDAC_INPUTINV_SHIFT 29
> -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
> -#define OMAP4_AVDAC_CTL_SHIFT 13
> -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
> -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
> -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
> -
> -/* CONTROL_HDMI_TX_PHY */
> -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
> -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
> -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
> -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
> -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
> -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
> -
> -/* CONTROL_MMC2 */
> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
> -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
> -
> -/* CONTROL_DSIPHY */
> -#define OMAP4_DSI2_LANEENABLE_SHIFT 29
> -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
> -#define OMAP4_DSI1_LANEENABLE_SHIFT 24
> -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
> -#define OMAP4_DSI1_PIPD_SHIFT 19
> -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
> -#define OMAP4_DSI2_PIPD_SHIFT 14
> -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
> -
> -/* CONTROL_MCBSPLP */
> -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
> -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
> -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
> -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
> -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
> -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
> -
> -/* CONTROL_USB2PHYCORE */
> -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
> -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
> -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
> -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
> -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
> -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
> -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
> -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
> -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
> -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
> -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
> -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
> -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
> -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
> -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
> -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
> -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
> -#define OMAP4_USB2PHY_DATADET_SHIFT 18
> -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
> -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
> -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
> -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
> -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
> -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
> -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
> -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
> -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
> -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
> -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
> -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
> -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
> -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
> -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
> -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
> -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
> -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
> -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
> -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
> -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
> -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
> -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
> -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
> -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
> -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
> -
> -/* CONTROL_I2C_1 */
> -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
> -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
> -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
> -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
> -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
> -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
> -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
> -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
> -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
> -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
> -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
> -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
> -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
> -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
> -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
> -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
> -
> -/* CONTROL_MMC1 */
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
> -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
> -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
> -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
> -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
> -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
> -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
> -#define OMAP4_USB_FD_CDEN_SHIFT 23
> -#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
> -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
> -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
> -
> -/* CONTROL_HSI */
> -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
> -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
> -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
> -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
> -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
> -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
> -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
> -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
> -
> -/* CONTROL_USB */
> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
> -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
> -
> -/* CONTROL_HDQ */
> -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
> -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
> -
> -/* CONTROL_LPDDR2IO1_0 */
> -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
> -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
> -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
> -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
> -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
> -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
> -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
> -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
> -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
> -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
> -
> -/* CONTROL_LPDDR2IO1_1 */
> -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
> -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
> -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
> -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
> -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
> -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
> -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
> -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
> -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
> -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
> -
> -/* CONTROL_LPDDR2IO1_2 */
> -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
> -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
> -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
> -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
> -
> -/* CONTROL_LPDDR2IO1_3 */
> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
> -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
> -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
> -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
> -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
> -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
> -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
> -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
> -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
> -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
> -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
> -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
> -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
> -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
> -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
> -
> -/* CONTROL_LPDDR2IO2_0 */
> -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
> -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
> -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
> -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
> -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
> -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
> -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
> -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
> -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
> -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
> -
> -/* CONTROL_LPDDR2IO2_1 */
> -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
> -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
> -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
> -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
> -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
> -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
> -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
> -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
> -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
> -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
> -
> -/* CONTROL_LPDDR2IO2_2 */
> -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
> -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
> -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
> -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
> -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
> -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
> -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
> -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
> -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
> -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
> -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
> -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
> -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
> -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
> -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
> -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
> -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
> -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
> -
> -/* CONTROL_LPDDR2IO2_3 */
> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
> -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
> -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
> -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
> -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
> -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
> -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
> -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
> -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
> -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
> -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
> -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
> -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
> -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
> -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
> -
> -/* CONTROL_BUS_HOLD */
> -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
> -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
> -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
> -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
> -
> -/* CONTROL_C2C */
> -#define OMAP4_MIRROR_MODE_EN_SHIFT 31
> -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
> -#define OMAP4_C2C_SPARE_SHIFT 24
> -#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
> -
> -/* CORE_CONTROL_SPARE_RW */
> -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
> -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
> -
> -/* CORE_CONTROL_SPARE_R */
> -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
> -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
> -
> -/* CORE_CONTROL_SPARE_R_C0 */
> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
> -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
> -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
> -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
> -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
> -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
> -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
> -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
> -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
> -
> -/* CONTROL_EFUSE_1 */
> -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
> -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
> -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
> -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
> -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
> -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
> -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
> -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
> -
> -/* CONTROL_EFUSE_2 */
> -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
> -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
> -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
> -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
> -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
> -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
> -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
> -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
> -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
> -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
> -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
> -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
> -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
> -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
> -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
> -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
> -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
> -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
> -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
> -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
> -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
> -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
> -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
> -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
> -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
> -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
> -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
> -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
> -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
> -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
> -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
> -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
> -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
> -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
> -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
> -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
> -
> -/* CONTROL_EFUSE_3 */
> -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
> -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
> -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
> -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
> -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
> -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
> -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
> -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
> -
> -/* CONTROL_EFUSE_4 */
> -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
> -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
> -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
> -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
> -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
> -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
> -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
> -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
> deleted file mode 100644
> index 17c9b37..0000000
> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
> +++ /dev/null
> @@ -1,236 +0,0 @@
> -/*
> - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
> - *
> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
> - *
> - * Benoit Cousson (b-cousson@ti.com)
> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
> - *
> - * This file is automatically generated from the OMAP hardware databases.
> - * We respectfully ask that any modifications to this file be coordinated
> - * with the public linux-omap@vger.kernel.org mailing list and the
> - * authors above to ensure that the autogeneration scripts are kept
> - * up-to-date with the file contents.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
> -
> -
> -/* Base address */
> -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
> -
> -/* Registers offset */
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
> -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
> -
> -/* Registers shifts and masks */
> -
> -/* IP_REVISION */
> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
> -#define OMAP4_IP_REV_FUNC_SHIFT 16
> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
> -#define OMAP4_IP_REV_RTL_SHIFT 11
> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
> -#define OMAP4_IP_REV_MINOR_SHIFT 0
> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
> -
> -/* IP_HWINFO */
> -#define OMAP4_IP_HWINFO_SHIFT 0
> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
> -
> -/* IP_SYSCONFIG */
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
> -
> -/* PADCONF_WAKEUPEVENT_0 */
> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
> -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
> -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
> -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
> -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
> -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
> -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
> -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
> -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
> -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
> -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
> -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
> -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
> -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
> -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
> -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
> -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
> -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
> -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
> -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
> -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
> -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
> -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
> -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
> -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
> -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
> -
> -/* CONTROL_SMART1NOPMIO_PADCONF_0 */
> -#define OMAP4_FREF_DR0_SC_SHIFT 30
> -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
> -#define OMAP4_FREF_DR1_SC_SHIFT 28
> -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
> -#define OMAP4_FREF_DR4_SC_SHIFT 26
> -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
> -#define OMAP4_FREF_DR5_SC_SHIFT 24
> -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
> -#define OMAP4_FREF_DR6_SC_SHIFT 22
> -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
> -#define OMAP4_FREF_DR7_SC_SHIFT 20
> -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
> -#define OMAP4_GPIO_DR7_SC_SHIFT 18
> -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
> -#define OMAP4_DPM_DR0_SC_SHIFT 14
> -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
> -#define OMAP4_SIM_DR0_SC_SHIFT 12
> -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
> -
> -/* CONTROL_SMART1NOPMIO_PADCONF_1 */
> -#define OMAP4_FREF_DR0_LB_SHIFT 30
> -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
> -#define OMAP4_FREF_DR1_LB_SHIFT 28
> -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
> -#define OMAP4_FREF_DR4_LB_SHIFT 26
> -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
> -#define OMAP4_FREF_DR5_LB_SHIFT 24
> -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
> -#define OMAP4_FREF_DR6_LB_SHIFT 22
> -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
> -#define OMAP4_FREF_DR7_LB_SHIFT 20
> -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
> -#define OMAP4_GPIO_DR7_LB_SHIFT 18
> -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
> -#define OMAP4_DPM_DR0_LB_SHIFT 14
> -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
> -#define OMAP4_SIM_DR0_LB_SHIFT 12
> -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
> -
> -/* CONTROL_PADCONF_MODE */
> -#define OMAP4_VDDS_DV_FREF_SHIFT 31
> -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
> -#define OMAP4_VDDS_DV_BANK2_SHIFT 30
> -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
> -
> -/* CONTROL_XTAL_OSCILLATOR */
> -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
> -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
> -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
> -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
> -
> -/* CONTROL_USIMIO */
> -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
> -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
> -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
> -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
> -#define OMAP4_USIM_PWRDNZ_SHIFT 28
> -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
> -
> -/* CONTROL_I2C_2 */
> -#define OMAP4_SR_SDA_GLFENB_SHIFT 31
> -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
> -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
> -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
> -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
> -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
> -#define OMAP4_SR_SCL_GLFENB_SHIFT 27
> -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
> -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
> -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
> -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
> -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
> -
> -/* CONTROL_JTAG */
> -#define OMAP4_JTAG_NTRST_EN_SHIFT 31
> -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
> -#define OMAP4_JTAG_TCK_EN_SHIFT 30
> -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
> -#define OMAP4_JTAG_RTCK_EN_SHIFT 29
> -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
> -#define OMAP4_JTAG_TDI_EN_SHIFT 28
> -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
> -#define OMAP4_JTAG_TDO_EN_SHIFT 27
> -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
> -
> -/* CONTROL_SYS */
> -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
> -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
> -
> -/* WKUP_CONTROL_SPARE_RW */
> -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
> -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
> -
> -/* WKUP_CONTROL_SPARE_R */
> -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
> -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
> -
> -/* WKUP_CONTROL_SPARE_R_C0 */
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
> -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
> deleted file mode 100644
> index a0af9ba..0000000
> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -/*
> - * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
> - *
> - * Copyright (C) 2009-2010 Texas Instruments, Inc.
> - *
> - * Benoit Cousson (b-cousson@ti.com)
> - * Santosh Shilimkar (santosh.shilimkar@ti.com)
> - *
> - * This file is automatically generated from the OMAP hardware databases.
> - * We respectfully ask that any modifications to this file be coordinated
> - * with the public linux-omap@vger.kernel.org mailing list and the
> - * authors above to ensure that the autogeneration scripts are kept
> - * up-to-date with the file contents.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
> -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
> -
> -
> -/* Base address */
> -#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
> -
> -/* Registers offset */
> -#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
> -#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
> -#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
> -#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
> -
> -/* Registers shifts and masks */
> -
> -/* IP_REVISION */
> -#define OMAP4_IP_REV_SCHEME_SHIFT 30
> -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
> -#define OMAP4_IP_REV_FUNC_SHIFT 16
> -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
> -#define OMAP4_IP_REV_RTL_SHIFT 11
> -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
> -#define OMAP4_IP_REV_MAJOR_SHIFT 8
> -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
> -#define OMAP4_IP_REV_CUSTOM_SHIFT 6
> -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
> -#define OMAP4_IP_REV_MINOR_SHIFT 0
> -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
> -
> -/* IP_HWINFO */
> -#define OMAP4_IP_HWINFO_SHIFT 0
> -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
> -
> -/* IP_SYSCONFIG */
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
> -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
> -
> -/* CONF_DEBUG_SEL_TST_0 */
> -#define OMAP4_WKUP_MODE_SHIFT 0
> -#define OMAP4_WKUP_MODE_MASK (1 << 0)
> -
> -#endif
> --
> 1.7.7.6
>
>
^ permalink raw reply
* Re: [PATCH v3 0/7] OMAP System Control Module
From: Eduardo Valentin @ 2012-06-28 4:43 UTC (permalink / raw)
To: Konstantin Baydarov
Cc: balbi, kishon, amit.kucheria, linux-pm, linux-omap,
linux-arm-kernel
In-Reply-To: <4FEB4B30.2040305@dev.rtsoft.ru>
Hello,
On Wed, Jun 27, 2012 at 10:04:32PM +0400, Konstantin Baydarov wrote:
> Hello.
>
> This is a next version of series of patches(based on Eduardo Valentin's patch set) adding a basic support for system control module, on OMAP4+ context. It is a working in progress.
>
> Main changes since previous patch set version:
> - Bandgap and usb phy: drivers are now independent from control module driver, they use their own functions to acess scm registers.
Well, I believe the idea of having them with their own io resource was to avoid
children drivers accessing each other io areas. Is this now working?
> - omap-control-core: resources aren't hardcoded, they are specified in dts file.
> - omap-control-core: Control module is a built-in driver - added control module select to ARCH_HAS_CONTROL_MODULE and ARCH_OMAP4.
> Probably, no configuration option is required!
Why is this? I suppose the idea is to have the arch config selecting that flag.
> - omap-control-core: Added early init call that ioremaps control module IOMEM window, this allows access of SCM registers very early, for example from omap_type()
Is this going to be reserved as well? if yes, how children are going to have
their own access functions?
> - omap-control-core: Removed device pointer from omap-control-core API arguments, becuase there can be only one instance control
> module device.
> - omap-control-core: removed omap_control_get, omap_control_readl, omap_control_writel
fine, assuming the io split works...
> - omap-control-core: added omap_control_status_read that is used early in omap_type
> - Bandgap and usb phy: Added private spinlocks for bandgap and usb drivers.
> - Bandgap: Check the type of bandgap dynamically in bandgap driver probe function by reading
> omap core control module revision register CONTROL_GEN_CORE_REVISION.
this has some issue... I will post comment on the patch
> - Bandgap and usb phy: Parent SCM platform device IOMEM resources is used to get the base address of SCM window.
Ohh.. Then what is the point of having them using their own io access functions,
nothing is again protected as you have only 1 io resource which is shared.
And now is even worse because you have several io access function..
I think this is moving backwards.
> - Bandgap masks defines were moved to drivers/thermal/omap-bandgap.c.
>
> TODO list for bandgap driver:
> - Reserve omap-control-core IOMEM window.
> - Improve thermal zone definition for OMAP4
> - Introduce the thermal zones for OMAP5
Based on the review comments on RFC patch series, there are more
things to be done.
I have the O4 and O5 zone definition ready. But that work depends
on generic CPU cooling patches. I have also looked the driver support
for 4430. But the probing and io resource split is still based on
previous design. I have also a patch which does the remapping in the
bandgap driver. But really, for this to work it would require to have
several entries in the reg property. And that is going to change from
BG version to BG version.
I can prepare some patches for this.
^ permalink raw reply
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