* Re: [PATCH 2/2] interconnect: qcom: add Hawi interconnect provider driver
From: Dmitry Baryshkov @ 2026-03-31 0:47 UTC (permalink / raw)
To: Vivek Aknurwar
Cc: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton
In-Reply-To: <20260330-icc-hawi-v1-2-4b54a9e7d38c@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 05:40:01PM -0700, Vivek Aknurwar wrote:
> Add driver for the Qualcomm interconnect buses found in Hawi
> based platforms. The topology consists of several NoCs that are
> controlled by a remote processor that collects the aggregated
> bandwidth for each master-slave pairs.
>
> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
> ---
> drivers/interconnect/qcom/Kconfig | 9 +
> drivers/interconnect/qcom/Makefile | 2 +
> drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 2032 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH 2/2] interconnect: qcom: add Hawi interconnect provider driver
From: Vivek Aknurwar @ 2026-03-31 0:40 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar
In-Reply-To: <20260330-icc-hawi-v1-0-4b54a9e7d38c@oss.qualcomm.com>
Add driver for the Qualcomm interconnect buses found in Hawi
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
---
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++++++++++++++++++
3 files changed, 2032 insertions(+)
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index bb1cb8a640c1..896b07589386 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -17,6 +17,15 @@ config INTERCONNECT_QCOM_GLYMUR
This is a driver for the Qualcomm Network-on-Chip on glymur-based
platforms.
+config INTERCONNECT_QCOM_HAWI
+ tristate "Qualcomm HAWI interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on hawi-based
+ platforms.
+
config INTERCONNECT_QCOM_KAANAPALI
tristate "Qualcomm KAANAPALI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 6eedff043b41..750ff9fd5b46 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o
interconnect_qcom-y := icc-common.o
icc-bcm-voter-objs := bcm-voter.o
qnoc-glymur-objs := glymur.o
+qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
@@ -49,6 +50,7 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
+obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
diff --git a/drivers/interconnect/qcom/hawi.c b/drivers/interconnect/qcom/hawi.c
new file mode 100644
index 000000000000..ef01ed5624d2
--- /dev/null
+++ b/drivers/interconnect/qcom/hawi.c
@@ -0,0 +1,2021 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+static struct qcom_icc_node ddr_eff_veto_slave = {
+ .name = "ddr_eff_veto_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup3_core_slave = {
+ .name = "qup3_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup4_core_slave = {
+ .name = "qup4_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_aoss = {
+ .name = "qhs_aoss",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router_fence = {
+ .name = "qhs_ipc_router_fence",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_soccp = {
+ .name = "qhs_soccp",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tme_cfg = {
+ .name = "qhs_tme_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_ddrss_cfg = {
+ .name = "qss_ddrss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie = {
+ .name = "xs_pcie",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_lpi_cc = {
+ .name = "qhs_lpi_cc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_lb = {
+ .name = "qns_lb",
+ .channels = 4,
+ .buswidth = 32,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc = {
+ .name = "srvc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc_chipcx = {
+ .name = "srvc_llclpi_noc_chipcx",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ddr_rt_slave = {
+ .name = "ddr_rt_slave",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_pcie_aggre_noc = {
+ .name = "srvc_pcie_aggre_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy0 = {
+ .name = "qhs_ahb2phy0",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_boot_rom = {
+ .name = "qhs_boot_rom",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_cfg = {
+ .name = "qhs_camera_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_crypto_cfg = {
+ .name = "qhs_crypto_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display_cfg = {
+ .name = "qhs_display_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_eva_cfg = {
+ .name = "qhs_eva_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpuss_cfg = {
+ .name = "qhs_gpuss_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_i2c = {
+ .name = "qhs_i2c",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_iris_cfg = {
+ .name = "qhs_iris_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mss_cfg = {
+ .name = "qhs_mss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_cfg = {
+ .name = "qhs_pcie_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_g4x1_cfg = {
+ .name = "qhs_pcie_g4x1_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_prng = {
+ .name = "qhs_prng",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qspi = {
+ .name = "qhs_qspi",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup1 = {
+ .name = "qhs_qup1",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup2 = {
+ .name = "qhs_qup2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup3 = {
+ .name = "qhs_qup3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup4 = {
+ .name = "qhs_qup4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc2 = {
+ .name = "qhs_sdc2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc4 = {
+ .name = "qhs_sdc4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+ .name = "qhs_ufs_mem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3 = {
+ .name = "qhs_usb3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
+ .name = "qhs_vsense_ctrl_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_cfg = {
+ .name = "qss_qdss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_stm = {
+ .name = "qss_qdss_stm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_tcsr = {
+ .name = "qss_tcsr",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node ddr_eff_veto_master = {
+ .name = "ddr_eff_veto_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_node qup3_core_master = {
+ .name = "qup3_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_node qup4_core_master = {
+ .name = "qup4_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &xs_pcie },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = {
+ .name = "qnm_lpiaon_noc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 4,
+ .link_nodes = { &qhs_lpi_cc, &qns_lb,
+ &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ebi },
+};
+
+static struct qcom_icc_node ddr_rt_mc = {
+ .name = "ddr_rt_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_node qsm_pcie_anoc_cfg = {
+ .name = "qsm_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &srvc_pcie_aggre_noc },
+};
+
+static struct qcom_icc_node qsm_cfg_east = {
+ .name = "qsm_cfg_east",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 4,
+ .link_nodes = { &qhs_crypto_cfg, &qhs_gpuss_cfg,
+ &qhs_qup2, &qhs_vsense_ctrl_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_mm = {
+ .name = "qsm_cfg_mm",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 5,
+ .link_nodes = { &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_display_cfg, &qhs_eva_cfg,
+ &qhs_iris_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_north = {
+ .name = "qsm_cfg_north",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 5,
+ .link_nodes = { &qhs_pcie_cfg, &qhs_pcie_g4x1_cfg,
+ &qhs_qup3, &qhs_qup4,
+ &qhs_sdc2 },
+};
+
+static struct qcom_icc_node qsm_cfg_south = {
+ .name = "qsm_cfg_south",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 6,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_qspi,
+ &qhs_qup1, &qhs_sdc4,
+ &qhs_ufs_mem_cfg, &qhs_usb3 },
+};
+
+static struct qcom_icc_node qsm_cfg_southwest = {
+ .name = "qsm_cfg_southwest",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_ipc_router, &qhs_mss_cfg },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &llcc_mc },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_pcie },
+};
+
+static struct qcom_icc_node qns_llc_lpinoc = {
+ .name = "qns_llc_lpinoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },
+};
+
+static struct qcom_icc_node qss_pcie_anoc_cfg = {
+ .name = "qss_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_east_cfg = {
+ .name = "qss_stdst_east_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_east },
+};
+
+static struct qcom_icc_node qss_stdst_mm_cfg = {
+ .name = "qss_stdst_mm_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm },
+};
+
+static struct qcom_icc_node qss_stdst_north_cfg = {
+ .name = "qss_stdst_north_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_north },
+};
+
+static struct qcom_icc_node qss_stdst_south_cfg = {
+ .name = "qss_stdst_south_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_south },
+};
+
+static struct qcom_icc_node qss_stdst_southwest_cfg = {
+ .name = "qss_stdst_southwest_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_southwest },
+};
+
+static struct qcom_icc_node alm_gic = {
+ .name = "alm_gic",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14d000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_qpace = {
+ .name = "qnm_qpace",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x153000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qsm_cfg_center = {
+ .name = "qsm_cfg_center",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 10,
+ .link_nodes = { &qhs_clk_ctl, &qhs_i2c,
+ &qhs_imem_cfg, &qhs_prng,
+ &qhs_tlmm, &qss_pcie_anoc_cfg,
+ &qss_qdss_cfg, &qss_qdss_stm,
+ &qss_tcsr, &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_center_cfg = {
+ .name = "qss_stdst_center_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_center },
+};
+
+static struct qcom_icc_node qsm_cnoc_main = {
+ .name = "qsm_cnoc_main",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 6,
+ .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg,
+ &qss_stdst_mm_cfg, &qss_stdst_north_cfg,
+ &qss_stdst_south_cfg, &qss_stdst_southwest_cfg },
+};
+
+static struct qcom_icc_node qss_cfg = {
+ .name = "qss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cnoc_main },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 8,
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+ .name = "qns_gem_noc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_cnoc },
+};
+
+static struct qcom_icc_node alm_gpu_tcu = {
+ .name = "alm_gpu_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x145000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x147000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_gpu = {
+ .name = "qnm_gpu",
+ .channels = 4,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 4,
+ .port_offsets = { 0x51000, 0x53000, 0xd1000, 0xd3000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_lpass_gemnoc = {
+ .name = "qnm_lpass_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x149000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mdsp = {
+ .name = "qnm_mdsp",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf = {
+ .name = "qnm_mnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x55000, 0xd5000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf = {
+ .name = "qnm_mnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x57000, 0xd7000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_nsp_gemnoc = {
+ .name = "qnm_nsp_gemnoc",
+ .channels = 4,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 4,
+ .port_offsets = { 0x59000, 0x5b000, 0xd9000, 0xdb000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14b000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14f000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_wlan_q6 = {
+ .name = "qnm_wlan_q6",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
+ .name = "qns_lpass_ag_noc_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_gemnoc },
+};
+
+static struct qcom_icc_node qns_mem_noc_hf = {
+ .name = "qns_mem_noc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_hf },
+};
+
+static struct qcom_icc_node qns_mem_noc_sf = {
+ .name = "qns_mem_noc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_sf },
+};
+
+static struct qcom_icc_node qns_nsp_gemnoc = {
+ .name = "qns_nsp_gemnoc",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_nsp_gemnoc },
+};
+
+static struct qcom_icc_node qns_pcie_gemnoc = {
+ .name = "qns_pcie_gemnoc",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_pcie },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_snoc_sf },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc = {
+ .name = "qnm_lpiaon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc },
+};
+
+static struct qcom_icc_node qnm_camnoc_hf = {
+ .name = "qnm_camnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2a000, 0x2b000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
+ .name = "qnm_camnoc_nrt_icp_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x2c000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
+ .name = "qnm_camnoc_rt_cdm_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x38000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_sf = {
+ .name = "qnm_camnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2d000, 0x2e000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_mdp = {
+ .name = "qnm_mdp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x2f000, 0x30000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_mdss_dcp = {
+ .name = "qnm_mdss_dcp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x39000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_vapss_hcp = {
+ .name = "qnm_vapss_hcp",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_cv_cpu = {
+ .name = "qnm_video_cv_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x34000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_eva = {
+ .name = "qnm_video_eva",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x35000, 0x36000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_mvp = {
+ .name = "qnm_video_mvp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x32000, 0x33000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_v_cpu = {
+ .name = "qnm_video_v_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x37000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_nsp = {
+ .name = "qnm_nsp",
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie = {
+ .name = "xm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 3,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie_g4x1 = {
+ .name = "xm_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node qnm_aggre_noc = {
+ .name = "qnm_aggre_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_apss_noc = {
+ .name = "qnm_apss_noc",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1e000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_cnoc_data = {
+ .name = "qnm_cnoc_data",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1f000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+ .name = "qns_a1noc_snoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_node qns_lpass_aggnoc = {
+ .name = "qns_lpass_aggnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc },
+};
+
+static struct qcom_icc_node qhm_qspi = {
+ .name = "qhm_qspi",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x49000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup2 = {
+ .name = "qhm_qup2",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x48000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup3 = {
+ .name = "qhm_qup3",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x46000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup4 = {
+ .name = "qhm_qup4",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x47000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_crypto = {
+ .name = "qxm_crypto",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x40000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x41000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_qup1 = {
+ .name = "qxm_qup1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4d000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_soccp = {
+ .name = "qxm_soccp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x45000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_0 = {
+ .name = "xm_qdss_etr_0",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x42000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_1 = {
+ .name = "xm_qdss_etr_1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x43000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc2 = {
+ .name = "xm_sdc2",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x44000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc4 = {
+ .name = "xm_sdc4",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4a000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_ufs_mem = {
+ .name = "xm_ufs_mem",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4b000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_usb3 = {
+ .name = "xm_usb3",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4c000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qnm_lpass_lpinoc = {
+ .name = "qnm_lpass_lpinoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 2,
+ .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_node qns_lpi_aon_noc = {
+ .name = "qns_lpi_aon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_lpinoc },
+};
+
+static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
+ .name = "qnm_lpinoc_dsp_qns4m",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpi_aon_noc },
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+ .name = "ACV",
+ .enable_mask = BIT(3),
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 1,
+ .nodes = { &qxm_crypto },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .enable_mask = BIT(0),
+ .keepalive = true,
+ .num_nodes = 23,
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
+ &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem,
+ &xs_pcie, &qsm_cfg_center,
+ &qsm_cfg_east, &qsm_cfg_mm,
+ &qsm_cfg_north, &qsm_cfg_south,
+ &qsm_cfg_southwest, &qhs_ahb2phy0,
+ &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_crypto_cfg,
+ &qhs_eva_cfg },
+};
+
+static struct qcom_icc_bcm bcm_cn1 = {
+ .name = "CN1",
+ .num_nodes = 1,
+ .nodes = { &qhs_display_cfg },
+};
+
+static struct qcom_icc_bcm bcm_co0 = {
+ .name = "CO0",
+ .enable_mask = BIT(0),
+ .num_nodes = 2,
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_de0 = {
+ .name = "DE0",
+ .enable_mask = BIT(0),
+ .num_nodes = 1,
+ .nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_bcm bcm_lp0 = {
+ .name = "LP0",
+ .num_nodes = 5,
+ .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb,
+ &qnm_lpass_lpinoc, &qns_llc_lpinoc,
+ &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mc5 = {
+ .name = "MC5",
+ .num_nodes = 1,
+ .nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_bcm bcm_mm0 = {
+ .name = "MM0",
+ .num_nodes = 1,
+ .nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_bcm bcm_mm1 = {
+ .name = "MM1",
+ .enable_mask = BIT(0),
+ .num_nodes = 9,
+ .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
+ &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
+ &qnm_vapss_hcp, &qnm_video_cv_cpu,
+ &qnm_video_mvp, &qnm_video_v_cpu,
+ &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_bcm bcm_qpc0 = {
+ .name = "QPC0",
+ .num_nodes = 1,
+ .nodes = { &qnm_qpace },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup1 = {
+ .name = "QUP1",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup2 = {
+ .name = "QUP2",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup3 = {
+ .name = "QUP3",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup4 = {
+ .name = "QUP4",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh1 = {
+ .name = "SH1",
+ .enable_mask = BIT(0),
+ .num_nodes = 15,
+ .nodes = { &alm_gic, &alm_gpu_tcu,
+ &alm_sys_tcu, &chm_apps,
+ &qnm_gpu, &qnm_lpass_gemnoc,
+ &qnm_mdsp, &qnm_mnoc_hf,
+ &qnm_mnoc_sf, &qnm_nsp_gemnoc,
+ &qnm_pcie, &qnm_snoc_sf,
+ &qnm_wlan_q6, &qns_gem_noc_cnoc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 1,
+ .nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+ .name = "SN3",
+ .num_nodes = 1,
+ .nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
+ &bcm_ce0,
+};
+
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
+ [MASTER_QSPI_0] = &qhm_qspi,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_QUP_3] = &qhm_qup3,
+ [MASTER_QUP_4] = &qhm_qup4,
+ [MASTER_CRYPTO] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_QUP_1] = &qxm_qup1,
+ [MASTER_SOCCP_PROC] = &qxm_soccp,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3,
+ [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static const struct regmap_config hawi_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x54400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_aggre1_noc = {
+ .config = &hawi_aggre1_noc_regmap_config,
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const clk_virt_bcms[] = {
+ &bcm_de0,
+ &bcm_qup0,
+ &bcm_qup1,
+ &bcm_qup2,
+ &bcm_qup3,
+ &bcm_qup4,
+};
+
+static struct qcom_icc_node * const clk_virt_nodes[] = {
+ [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master,
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [MASTER_QUP_CORE_3] = &qup3_core_master,
+ [MASTER_QUP_CORE_4] = &qup4_core_master,
+ [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+ [SLAVE_QUP_CORE_3] = &qup3_core_slave,
+ [SLAVE_QUP_CORE_4] = &qup4_core_slave,
+};
+
+static const struct qcom_icc_desc hawi_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node * const cnoc_main_nodes[] = {
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence,
+ [SLAVE_SOCCP] = &qhs_soccp,
+ [SLAVE_TME_CFG] = &qhs_tme_cfg,
+ [SLAVE_CNOC_CFG] = &qss_cfg,
+ [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_PCIE_0] = &xs_pcie,
+};
+
+static const struct regmap_config hawi_cnoc_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_cnoc_main = {
+ .config = &hawi_cnoc_main_regmap_config,
+ .nodes = cnoc_main_nodes,
+ .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
+ .bcms = cnoc_main_bcms,
+ .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
+};
+
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
+ &bcm_qpc0,
+ &bcm_sh0,
+ &bcm_sh1,
+};
+
+static struct qcom_icc_node * const gem_noc_nodes[] = {
+ [MASTER_GIC] = &alm_gic,
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
+ [MASTER_MSS_PROC] = &qnm_mdsp,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_QPACE] = &qnm_qpace,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_WLAN_Q6] = &qnm_wlan_q6,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+};
+
+static const struct regmap_config hawi_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x160200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_gem_noc = {
+ .config = &hawi_gem_noc_regmap_config,
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const llclpi_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const llclpi_noc_nodes[] = {
+ [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc,
+ [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc,
+ [SLAVE_LLCC_ISLAND] = &qns_lb,
+ [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc,
+ [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,
+};
+
+static const struct regmap_config hawi_llclpi_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x17200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_llclpi_noc = {
+ .config = &hawi_llclpi_noc_regmap_config,
+ .nodes = llclpi_noc_nodes,
+ .num_nodes = ARRAY_SIZE(llclpi_noc_nodes),
+ .bcms = llclpi_noc_bcms,
+ .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
+ [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
+ [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
+};
+
+static const struct regmap_config hawi_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xc080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_ag_noc = {
+ .config = &hawi_lpass_ag_noc_regmap_config,
+ .nodes = lpass_ag_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
+ [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
+ [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc,
+ [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
+};
+
+static const struct regmap_config hawi_lpass_lpiaon_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x19080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_lpiaon_noc = {
+ .config = &hawi_lpass_lpiaon_noc_regmap_config,
+ .nodes = lpass_lpiaon_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
+ .bcms = lpass_lpiaon_noc_bcms,
+ .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
+ [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
+ [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
+};
+
+static const struct regmap_config hawi_lpass_lpicx_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x46080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_lpass_lpicx_noc = {
+ .config = &hawi_lpass_lpicx_noc_regmap_config,
+ .nodes = lpass_lpicx_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_mc0,
+ &bcm_mc5,
+};
+
+static struct qcom_icc_node * const mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_DDR_RT] = &ddr_rt_mc,
+ [SLAVE_EBI1] = &ebi,
+ [SLAVE_DDR_RT] = &ddr_rt_slave,
+};
+
+static const struct qcom_icc_desc hawi_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node * const mmss_noc_nodes[] = {
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
+ [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_MDP] = &qnm_mdp,
+ [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
+ [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
+ [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
+ [MASTER_VIDEO_EVA] = &qnm_video_eva,
+ [MASTER_VIDEO_MVP] = &qnm_video_mvp,
+ [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+};
+
+static const struct regmap_config hawi_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5f800,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_mmss_noc = {
+ .config = &hawi_mmss_noc_regmap_config,
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
+ &bcm_co0,
+};
+
+static struct qcom_icc_node * const nsp_noc_nodes[] = {
+ [MASTER_CDSP_PROC] = &qnm_nsp,
+ [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+};
+
+static const struct regmap_config hawi_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x21280,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_nsp_noc = {
+ .config = &hawi_nsp_noc_regmap_config,
+ .nodes = nsp_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
+ .bcms = nsp_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node * const pcie_anoc_nodes[] = {
+ [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
+ [MASTER_PCIE_0] = &xm_pcie,
+ [MASTER_PCIE_1] = &xm_pcie_g4x1,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
+ [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
+};
+
+static const struct regmap_config hawi_pcie_anoc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x12400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_pcie_anoc = {
+ .config = &hawi_pcie_anoc_regmap_config,
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const stdst_cfg_bcms[] = {
+ &bcm_cn0,
+ &bcm_cn1,
+};
+
+static struct qcom_icc_node * const stdst_cfg_nodes[] = {
+ [MASTER_CFG_CENTER] = &qsm_cfg_center,
+ [MASTER_CFG_EAST] = &qsm_cfg_east,
+ [MASTER_CFG_MM] = &qsm_cfg_mm,
+ [MASTER_CFG_NORTH] = &qsm_cfg_north,
+ [MASTER_CFG_SOUTH] = &qsm_cfg_south,
+ [MASTER_CFG_SOUTHWEST] = &qsm_cfg_southwest,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_BOOT_ROM] = &qhs_boot_rom,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_EVA_CFG] = &qhs_eva_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_I2C] = &qhs_i2c,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_IRIS_CFG] = &qhs_iris_cfg,
+ [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_QUP_3] = &qhs_qup3,
+ [SLAVE_QUP_4] = &qhs_qup4,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
+ [SLAVE_QDSS_CFG] = &qss_qdss_cfg,
+ [SLAVE_QDSS_STM] = &qss_qdss_stm,
+ [SLAVE_TCSR] = &qss_tcsr,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static const struct regmap_config hawi_stdst_cfg_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xb1000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_stdst_cfg = {
+ .config = &hawi_stdst_cfg_regmap_config,
+ .nodes = stdst_cfg_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_cfg_nodes),
+ .bcms = stdst_cfg_bcms,
+ .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),
+};
+
+static struct qcom_icc_node * const stdst_main_nodes[] = {
+ [MASTER_CNOC_STARDUST] = &qsm_cnoc_main,
+ [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg,
+ [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg,
+ [SLAVE_STARDUST_MM_CFG] = &qss_stdst_mm_cfg,
+ [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg,
+ [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg,
+ [SLAVE_STARDUST_SOUTHWEST_CFG] = &qss_stdst_southwest_cfg,
+};
+
+static const struct regmap_config hawi_stdst_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x10000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_stdst_main = {
+ .config = &hawi_stdst_main_regmap_config,
+ .nodes = stdst_main_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_main_nodes),
+};
+
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn2,
+};
+
+static struct qcom_icc_node * const system_noc_nodes[] = {
+ [MASTER_A1NOC_SNOC] = &qnm_aggre_noc,
+ [MASTER_APSS_NOC] = &qnm_apss_noc,
+ [MASTER_CNOC_SNOC] = &qnm_cnoc_data,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+};
+
+static const struct regmap_config hawi_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc hawi_system_noc = {
+ .config = &hawi_system_noc_regmap_config,
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,hawi-aggre1-noc", .data = &hawi_aggre1_noc },
+ { .compatible = "qcom,hawi-clk-virt", .data = &hawi_clk_virt },
+ { .compatible = "qcom,hawi-cnoc-main", .data = &hawi_cnoc_main },
+ { .compatible = "qcom,hawi-gem-noc", .data = &hawi_gem_noc },
+ { .compatible = "qcom,hawi-llclpi-noc", .data = &hawi_llclpi_noc },
+ { .compatible = "qcom,hawi-lpass-ag-noc", .data = &hawi_lpass_ag_noc },
+ { .compatible = "qcom,hawi-lpass-lpiaon-noc", .data = &hawi_lpass_lpiaon_noc },
+ { .compatible = "qcom,hawi-lpass-lpicx-noc", .data = &hawi_lpass_lpicx_noc },
+ { .compatible = "qcom,hawi-mc-virt", .data = &hawi_mc_virt },
+ { .compatible = "qcom,hawi-mmss-noc", .data = &hawi_mmss_noc },
+ { .compatible = "qcom,hawi-nsp-noc", .data = &hawi_nsp_noc },
+ { .compatible = "qcom,hawi-pcie-anoc", .data = &hawi_pcie_anoc },
+ { .compatible = "qcom,hawi-stdst-cfg", .data = &hawi_stdst_cfg },
+ { .compatible = "qcom,hawi-stdst-main", .data = &hawi_stdst_main },
+ { .compatible = "qcom,hawi-system-noc", .data = &hawi_system_noc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-hawi",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("Qualcomm Hawi NoC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Hawi SoC
From: Vivek Aknurwar @ 2026-03-31 0:40 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar
In-Reply-To: <20260330-icc-hawi-v1-0-4b54a9e7d38c@oss.qualcomm.com>
Document the RPMh Network-On-Chip Interconnect of the Hawi platform.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,hawi-rpmh.yaml | 126 ++++++++++++++++
include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 164 +++++++++++++++++++++
2 files changed, 290 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml
new file mode 100644
index 000000000000..f10701025647
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi
+
+maintainers:
+ - Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,hawi-aggre1-noc
+ - qcom,hawi-clk-virt
+ - qcom,hawi-cnoc-main
+ - qcom,hawi-gem-noc
+ - qcom,hawi-llclpi-noc
+ - qcom,hawi-lpass-ag-noc
+ - qcom,hawi-lpass-lpiaon-noc
+ - qcom,hawi-lpass-lpicx-noc
+ - qcom,hawi-mc-virt
+ - qcom,hawi-mmss-noc
+ - qcom,hawi-nsp-noc
+ - qcom,hawi-pcie-anoc
+ - qcom,hawi-stdst-cfg
+ - qcom,hawi-stdst-main
+ - qcom,hawi-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-clk-virt
+ - qcom,hawi-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-pcie-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre-NOC PCIe AXI clock
+ - description: cfg-NOC PCIe a-NOC AHB clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,hawi-aggre1-noc
+ - qcom,hawi-pcie-anoc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clk_virt: interconnect-0 {
+ compatible = "qcom,hawi-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre_noc: interconnect@f00000 {
+ compatible = "qcom,hawi-aggre1-noc";
+ reg = <0x0 0xf00000 0x0 0x54400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_aggre_ufs_phy_axi_clk>,
+ <&gcc_aggre_usb3_prim_axi_clk>,
+ <&rpmhcc_ipa_clk>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,hawi-rpmh.h b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h
new file mode 100644
index 000000000000..75312cbbb80e
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_2 1
+#define MASTER_QUP_3 2
+#define MASTER_QUP_4 3
+#define MASTER_CRYPTO 4
+#define MASTER_IPA 5
+#define MASTER_QUP_1 6
+#define MASTER_SOCCP_PROC 7
+#define MASTER_QDSS_ETR 8
+#define MASTER_QDSS_ETR_1 9
+#define MASTER_SDCC_2 10
+#define MASTER_SDCC_4 11
+#define MASTER_UFS_MEM 12
+#define MASTER_USB3 13
+#define SLAVE_A1NOC_SNOC 14
+
+#define MASTER_DDR_EFF_VETO 0
+#define MASTER_QUP_CORE_0 1
+#define MASTER_QUP_CORE_1 2
+#define MASTER_QUP_CORE_2 3
+#define MASTER_QUP_CORE_3 4
+#define MASTER_QUP_CORE_4 5
+#define SLAVE_DDR_EFF_VETO 6
+#define SLAVE_QUP_CORE_0 7
+#define SLAVE_QUP_CORE_1 8
+#define SLAVE_QUP_CORE_2 9
+#define SLAVE_QUP_CORE_3 10
+#define SLAVE_QUP_CORE_4 11
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_IPA_CFG 3
+#define SLAVE_IPC_ROUTER_FENCE 4
+#define SLAVE_SOCCP 5
+#define SLAVE_TME_CFG 6
+#define SLAVE_CNOC_CFG 7
+#define SLAVE_DDRSS_CFG 8
+#define SLAVE_IMEM 9
+#define SLAVE_PCIE_0 10
+
+#define MASTER_GIC 0
+#define MASTER_GPU_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MSS_PROC 6
+#define MASTER_MNOC_HF_MEM_NOC 7
+#define MASTER_MNOC_SF_MEM_NOC 8
+#define MASTER_COMPUTE_NOC 9
+#define MASTER_ANOC_PCIE_GEM_NOC 10
+#define MASTER_QPACE 11
+#define MASTER_SNOC_SF_MEM_NOC 12
+#define MASTER_WLAN_Q6 13
+#define SLAVE_GEM_NOC_CNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_MEM_NOC_PCIE_SNOC 16
+
+#define MASTER_LPIAON_NOC_LLCLPI_NOC 0
+#define SLAVE_LPASS_LPI_CC 1
+#define SLAVE_LLCC_ISLAND 2
+#define SLAVE_SERVICE_LLCLPI_NOC 3
+#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define MASTER_DDR_RT 1
+#define SLAVE_EBI1 2
+#define SLAVE_DDR_RT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_CAMNOC_NRT_ICP_SF 1
+#define MASTER_CAMNOC_RT_CDM_SF 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_MDP 4
+#define MASTER_MDSS_DCP 5
+#define MASTER_CDSP_HCP 6
+#define MASTER_VIDEO_CV_PROC 7
+#define MASTER_VIDEO_EVA 8
+#define MASTER_VIDEO_MVP 9
+#define MASTER_VIDEO_V_PROC 10
+#define SLAVE_MNOC_HF_MEM_NOC 11
+#define SLAVE_MNOC_SF_MEM_NOC 12
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_ANOC_CFG 0
+#define MASTER_PCIE_0 1
+#define MASTER_PCIE_1 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+#define SLAVE_SERVICE_PCIE_ANOC 4
+
+#define MASTER_CFG_CENTER 0
+#define MASTER_CFG_EAST 1
+#define MASTER_CFG_MM 2
+#define MASTER_CFG_NORTH 3
+#define MASTER_CFG_SOUTH 4
+#define MASTER_CFG_SOUTHWEST 5
+#define SLAVE_AHB2PHY_SOUTH 6
+#define SLAVE_BOOT_ROM 7
+#define SLAVE_CAMERA_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_CRYPTO_CFG 10
+#define SLAVE_DISPLAY_CFG 11
+#define SLAVE_EVA_CFG 12
+#define SLAVE_GFX3D_CFG 13
+#define SLAVE_I2C 14
+#define SLAVE_IMEM_CFG 15
+#define SLAVE_IPC_ROUTER_CFG 16
+#define SLAVE_IRIS_CFG 17
+#define SLAVE_CNOC_MSS 18
+#define SLAVE_PCIE_0_CFG 19
+#define SLAVE_PCIE_1_CFG 20
+#define SLAVE_PRNG 21
+#define SLAVE_QSPI_0 22
+#define SLAVE_QUP_1 23
+#define SLAVE_QUP_2 24
+#define SLAVE_QUP_3 25
+#define SLAVE_QUP_4 26
+#define SLAVE_SDCC_2 27
+#define SLAVE_SDCC_4 28
+#define SLAVE_TLMM 29
+#define SLAVE_UFS_MEM_CFG 30
+#define SLAVE_USB3 31
+#define SLAVE_VSENSE_CTRL_CFG 32
+#define SLAVE_PCIE_ANOC_CFG 33
+#define SLAVE_QDSS_CFG 34
+#define SLAVE_QDSS_STM 35
+#define SLAVE_TCSR 36
+#define SLAVE_TCU 37
+
+#define MASTER_CNOC_STARDUST 0
+#define SLAVE_STARDUST_CENTER_CFG 1
+#define SLAVE_STARDUST_EAST_CFG 2
+#define SLAVE_STARDUST_MM_CFG 3
+#define SLAVE_STARDUST_NORTH_CFG 4
+#define SLAVE_STARDUST_SOUTH_CFG 5
+#define SLAVE_STARDUST_SOUTHWEST_CFG 6
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_APSS_NOC 1
+#define MASTER_CNOC_SNOC 2
+#define SLAVE_SNOC_GEM_NOC_SF 3
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
From: Vivek Aknurwar @ 2026-03-31 0:39 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, Mike Tipton,
Vivek Aknurwar
Add interconnect bindings and RPMh-based interconnect
driver support for the upcoming Qualcomm Hawi SoC.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
---
Vivek Aknurwar (2):
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Hawi SoC
interconnect: qcom: add Hawi interconnect provider driver
.../bindings/interconnect/qcom,hawi-rpmh.yaml | 126 ++
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/hawi.c | 2021 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 164 ++
5 files changed, 2322 insertions(+)
---
base-commit: e3b32dcb9f23e3c3927ef3eec6a5842a988fb574
change-id: 20260311-icc-hawi-d6dc165f8935
Best regards,
--
Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH 5/6] platform/x86/intel/pmc: Retrieve PMC info only for available PMCs
From: Xi Pardee @ 2026-03-31 0:34 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: irenic.rajneesh, david.e.box, platform-driver-x86, LKML, linux-pm
In-Reply-To: <33f4caaf-8e1a-33d8-8521-357a80a70eb7@linux.intel.com>
On 3/20/26 03:58, Ilpo Järvinen wrote:
> On Mon, 2 Mar 2026, Xi Pardee wrote:
>
>> Update the Intel PMC Core driver to fetch PMC information only for
>> available PMCs. Previously, the driver attempted to retrieve PMC info
>> even when the corresponding PMC was not present.
>>
>> This change aligns with recent updates to the Intel SSRAM Telemetry
>> driver. Starting with NVL, the SSRAM Telemetry driver is probed for
>> each individual SSRAM device. The prior implementation could not
>> differentiate between an unavailable PMC and one that had not yet
>> completed information retrieval. To resolve this, the PMC Core driver
>> now skips obtaining PMC info for unavailable PMCs.
>>
>> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
>> ---
>> drivers/platform/x86/intel/pmc/arl.c | 5 +++++
>> drivers/platform/x86/intel/pmc/core.c | 19 +++++++++++--------
>> drivers/platform/x86/intel/pmc/core.h | 2 ++
>> drivers/platform/x86/intel/pmc/lnl.c | 3 +++
>> drivers/platform/x86/intel/pmc/mtl.c | 3 +++
>> drivers/platform/x86/intel/pmc/ptl.c | 3 +++
>> drivers/platform/x86/intel/pmc/wcl.c | 3 +++
>> 7 files changed, 30 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
>> index 4d91ee010f6d0..34506542c94da 100644
>> --- a/drivers/platform/x86/intel/pmc/arl.c
>> +++ b/drivers/platform/x86/intel/pmc/arl.c
>> @@ -672,6 +672,9 @@ static struct pmc_info arl_pmc_info_list[] = {
>> {}
>> };
>>
>> +static u8 arl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH, PMC_IDX_MAX};
>> +static u8 arl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};
> This seems a bit dangerous approach if somebody forgets to add that
> PMC_IDX_MAX. It would be better to do it with sizeof() for safety).
Will add another field num_pmcs in pmc_dev_info struct to store the
number of available PMCs.
Will use ARRAY_SIZE() on pmc_list variable to retrieve the number of
available PMCs and store in num_pmcs variable and check that in
pmc_core_ssram_get_reg_base().
>> +
>> #define ARL_NPU_PCI_DEV 0xad1d
>> #define ARL_GNA_PCI_DEV 0xae4c
>> #define ARL_H_NPU_PCI_DEV 0x7d1d
>> @@ -721,6 +724,7 @@ static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_
>> static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
>> struct pmc_dev_info arl_pmc_dev = {
>> .dmu_guids = ARL_PMT_DMU_GUIDS,
>> + .pmc_list = arl_pmc_list,
>> .regmap_list = arl_pmc_info_list,
>> .map = &arl_socs_reg_map,
>> .sub_req_show = &pmc_core_substate_req_regs_fops,
>> @@ -735,6 +739,7 @@ struct pmc_dev_info arl_pmc_dev = {
>> static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
>> struct pmc_dev_info arl_h_pmc_dev = {
>> .dmu_guids = ARL_H_PMT_DMU_GUIDS,
>> + .pmc_list = arl_h_pmc_list,
>> .regmap_list = arl_pmc_info_list,
>> .map = &mtl_socm_reg_map,
>> .sub_req_show = &pmc_core_substate_req_regs_fops,
>> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
>> index 7bd0e1eaa32e2..85fff5e3abe0d 100644
>> --- a/drivers/platform/x86/intel/pmc/core.c
>> +++ b/drivers/platform/x86/intel/pmc/core.c
>> @@ -1744,16 +1744,19 @@ static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_idx)
>> return 0;
>> }
>>
>> -static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev)
>> +static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev, u8 *pmc_list)
>> {
>> + unsigned int i;
>> int ret;
>>
>> - ret = pmc_core_pmc_add(pmcdev, PMC_IDX_MAIN);
>> - if (ret)
>> - return ret;
>> -
>> - pmc_core_pmc_add(pmcdev, PMC_IDX_IOE);
>> - pmc_core_pmc_add(pmcdev, PMC_IDX_PCH);
>> + for (i = 0; pmc_list[i] != PMC_IDX_MAX; ++i) {
>> + if (pmc_list[i] == PMC_IDX_MAIN) {
>> + ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
>> + if (ret)
>> + return ret;
>> + } else
>> + pmc_core_pmc_add(pmcdev, pmc_list[i]);
> Isn't this same as:
>
> /* Non-MAIN PMCs are allowed to fail */
> ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
> if (ret && (pmc_list[i] == PMC_IDX_MAIN))
> return ret;
>
>
Will change to this format in next version.
Thanks!
Xi
>> + }
>>
>> return 0;
>> }
>> @@ -1775,7 +1778,7 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>> ssram = pmc_dev_info->regmap_list != NULL;
>> if (ssram) {
>> pmcdev->regmap_list = pmc_dev_info->regmap_list;
>> - ret = pmc_core_ssram_get_reg_base(pmcdev);
>> + ret = pmc_core_ssram_get_reg_base(pmcdev, pmc_dev_info->pmc_list);
>> /*
>> * EAGAIN error code indicates Intel PMC SSRAM Telemetry driver
>> * has not finished probe and PMC info is not available yet. Try
>> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
>> index f09791f866223..c4984e44f7b80 100644
>> --- a/drivers/platform/x86/intel/pmc/core.h
>> +++ b/drivers/platform/x86/intel/pmc/core.h
>> @@ -501,6 +501,7 @@ enum pmc_index {
>> * @pc_guid: GUID for telemetry region to read PKGC blocker info
>> * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
>> * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
>> + * @pmc_list: Index list of available PMC
>> * @regmap_list: Pointer to a list of pmc_info structure that could be
>> * available for the platform. When set, this field implies
>> * SSRAM support.
>> @@ -521,6 +522,7 @@ struct pmc_dev_info {
>> u32 pc_guid;
>> u32 pkgc_ltr_blocker_offset;
>> u32 pkgc_blocker_offset;
>> + u8 *pmc_list;
>> struct pmc_info *regmap_list;
>> const struct pmc_reg_map *map;
>> const struct file_operations *sub_req_show;
>> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
>> index 18f303af328e3..7b09b59e1326c 100644
>> --- a/drivers/platform/x86/intel/pmc/lnl.c
>> +++ b/drivers/platform/x86/intel/pmc/lnl.c
>> @@ -544,6 +544,8 @@ static struct pmc_info lnl_pmc_info_list[] = {
>> {}
>> };
>>
>> +static u8 lnl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
>> +
>> #define LNL_NPU_PCI_DEV 0x643e
>> #define LNL_IPU_PCI_DEV 0x645d
>>
>> @@ -571,6 +573,7 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>> }
>>
>> struct pmc_dev_info lnl_pmc_dev = {
>> + .pmc_list = lnl_pmc_list,
>> .regmap_list = lnl_pmc_info_list,
>> .map = &lnl_socm_reg_map,
>> .sub_req_show = &pmc_core_substate_req_regs_fops,
>> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
>> index b724dd8c34dba..6438fca266392 100644
>> --- a/drivers/platform/x86/intel/pmc/mtl.c
>> +++ b/drivers/platform/x86/intel/pmc/mtl.c
>> @@ -965,6 +965,8 @@ static struct pmc_info mtl_pmc_info_list[] = {
>> {}
>> };
>>
>> +static u8 mtl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};
>> +
>> #define MTL_GNA_PCI_DEV 0x7e4c
>> #define MTL_IPU_PCI_DEV 0x7d19
>> #define MTL_VPU_PCI_DEV 0x7d1d
>> @@ -995,6 +997,7 @@ static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>> static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
>> struct pmc_dev_info mtl_pmc_dev = {
>> .dmu_guids = MTL_PMT_DMU_GUIDS,
>> + .pmc_list = mtl_pmc_list,
>> .regmap_list = mtl_pmc_info_list,
>> .map = &mtl_socm_reg_map,
>> .sub_req_show = &pmc_core_substate_req_regs_fops,
>> diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
>> index 6c68772e738c8..538ca5ae2e9ec 100644
>> --- a/drivers/platform/x86/intel/pmc/ptl.c
>> +++ b/drivers/platform/x86/intel/pmc/ptl.c
>> @@ -543,6 +543,8 @@ static struct pmc_info ptl_pmc_info_list[] = {
>> {}
>> };
>>
>> +static u8 ptl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
>> +
>> #define PTL_NPU_PCI_DEV 0xb03e
>> #define PTL_IPU_PCI_DEV 0xb05d
>>
>> @@ -569,6 +571,7 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>> }
>>
>> struct pmc_dev_info ptl_pmc_dev = {
>> + .pmc_list = ptl_pmc_list,
>> .regmap_list = ptl_pmc_info_list,
>> .map = &ptl_pcdp_reg_map,
>> .sub_req_show = &pmc_core_substate_blk_req_fops,
>> diff --git a/drivers/platform/x86/intel/pmc/wcl.c b/drivers/platform/x86/intel/pmc/wcl.c
>> index b55069945e9e7..429f53f22a89f 100644
>> --- a/drivers/platform/x86/intel/pmc/wcl.c
>> +++ b/drivers/platform/x86/intel/pmc/wcl.c
>> @@ -469,6 +469,8 @@ static struct pmc_info wcl_pmc_info_list[] = {
>> {}
>> };
>>
>> +static u8 wcl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
>> +
>> #define WCL_NPU_PCI_DEV 0xfd3e
>>
>> /*
>> @@ -494,6 +496,7 @@ static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>>
>> struct pmc_dev_info wcl_pmc_dev = {
>> .regmap_list = wcl_pmc_info_list,
>> + .pmc_list = wcl_pmc_list,
>> .map = &wcl_pcdn_reg_map,
>> .sub_req_show = &pmc_core_substate_blk_req_fops,
>> .suspend = cnl_suspend,
>>
^ permalink raw reply
* Re: [PATCH 2/6] platform/x86/intel/pmc: Enable Pkgc blocking residency counter
From: Xi Pardee @ 2026-03-31 0:28 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: irenic.rajneesh, david.e.box, platform-driver-x86, LKML, linux-pm
In-Reply-To: <c78bc413-d946-9a2e-ec90-670320e3a8a0@linux.intel.com>
On 3/20/26 03:27, Ilpo Järvinen wrote:
> On Mon, 2 Mar 2026, Xi Pardee wrote:
>
>> Enable the Package C-state blocking counter in the PMT telemetry
>> region. This counter reports the number of 10 µs intervals during
>> which a Package C-state 10.2/3 entry was blocked for the specified
>> reasons.
>>
>> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
>> ---
>> drivers/platform/x86/intel/pmc/core.c | 27 +++++++++++++++++++++++++++
>> drivers/platform/x86/intel/pmc/core.h | 8 ++++++++
>> 2 files changed, 35 insertions(+)
>>
>> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
>> index bf95a1f2ba428..e5b48a68cf495 100644
>> --- a/drivers/platform/x86/intel/pmc/core.c
>> +++ b/drivers/platform/x86/intel/pmc/core.c
>> @@ -1093,6 +1093,28 @@ static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
>> }
>> DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
>>
>> +static int pmc_core_pkgc_blocker_residency_show(struct seq_file *s, void *unused)
>> +{
>> + struct pmc_dev *pmcdev = s->private;
>> + const char **pkgc_blocker_counters;
>> + u32 counter, offset;
>> + unsigned int i;
>> + int ret;
>> +
>> + offset = pmcdev->pkgc_blocker_offset;
>> + pkgc_blocker_counters = pmcdev->pkgc_blocker_counters;
>> + for (i = 0; pkgc_blocker_counters[i]; i++, offset++) {
>> + ret = pmt_telem_read32(pmcdev->pc_ep, offset,
>> + &counter, 1);
>> + if (ret)
>> + return ret;
>> + seq_printf(s, "%-30s %-30u\n", pkgc_blocker_counters[i], counter);
>> + }
>> +
>> + return 0;
> I wonder if it would be create a common helper as this looks practically
> the same as pmc_core_pkgc_ltr_blocker_show() added in the previous patch?
Thanks!
Will add a common helper in next version.
Xi
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_blocker_residency);
>> +
>> static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
>> {
>> struct pmc_dev *pmcdev = s->private;
>> @@ -1380,6 +1402,8 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_de
>> pmcdev->pc_ep = ep;
>> pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
>> pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
>> + pmcdev->pkgc_blocker_counters = pmc_dev_info->pkgc_blocker_counters;
>> + pmcdev->pkgc_blocker_offset = pmc_dev_info->pkgc_blocker_offset;
>> }
>>
>> release_dev:
>> @@ -1512,6 +1536,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev_info
>> debugfs_create_file("pkgc_ltr_blocker_show", 0444,
>> pmcdev->dbgfs_dir, pmcdev,
>> &pmc_core_pkgc_ltr_blocker_fops);
>> + debugfs_create_file("pkgc_blocker_residency_show", 0444,
>> + pmcdev->dbgfs_dir, pmcdev,
>> + &pmc_core_pkgc_blocker_residency_fops);
>> }
>>
>> }
>> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
>> index a20aab73c1409..829b1dee3f636 100644
>> --- a/drivers/platform/x86/intel/pmc/core.h
>> +++ b/drivers/platform/x86/intel/pmc/core.h
>> @@ -455,6 +455,8 @@ struct pmc {
>> *
>> * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
>> * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
>> + * @pkgc_blocker_counters: Array of PKGC blocker counters
>> + * @pkgc_blocker_offset: Offset to PKGC blocker in telemetry region
>> *
>> * pmc_dev contains info about power management controller device.
>> */
>> @@ -480,6 +482,8 @@ struct pmc_dev {
>>
>> const char **pkgc_ltr_blocker_counters;
>> u32 pkgc_ltr_blocker_offset;
>> + const char **pkgc_blocker_counters;
>> + u32 pkgc_blocker_offset;
>> };
>>
>> enum pmc_index {
>> @@ -495,6 +499,7 @@ enum pmc_index {
>> * @dmu_guids: List of Die Management Unit GUID
>> * @pc_guid: GUID for telemetry region to read PKGC blocker info
>> * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
>> + * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
>> * @regmap_list: Pointer to a list of pmc_info structure that could be
>> * available for the platform. When set, this field implies
>> * SSRAM support.
>> @@ -502,6 +507,7 @@ enum pmc_index {
>> * specific attributes of the primary PMC
>> * @sub_req_show: File operations to show substate requirements
>> * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
>> + * @pkgc_blocker_counters: Array of PKGC blocker counters
>> * @suspend: Function to perform platform specific suspend
>> * @resume: Function to perform platform specific resume
>> * @init: Function to perform platform specific init action
>> @@ -512,10 +518,12 @@ struct pmc_dev_info {
>> u32 *dmu_guids;
>> u32 pc_guid;
>> u32 pkgc_ltr_blocker_offset;
>> + u32 pkgc_blocker_offset;
>> struct pmc_info *regmap_list;
>> const struct pmc_reg_map *map;
>> const struct file_operations *sub_req_show;
>> const char **pkgc_ltr_blocker_counters;
>> + const char **pkgc_blocker_counters;
>> void (*suspend)(struct pmc_dev *pmcdev);
>> int (*resume)(struct pmc_dev *pmcdev);
>> int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
>>
^ permalink raw reply
* Re: [PATCH 1/6] platform/x86/intel/pmc: Enable PkgC LTR blocking counter
From: Xi Pardee @ 2026-03-31 0:27 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: irenic.rajneesh, david.e.box, platform-driver-x86, LKML, linux-pm
In-Reply-To: <9a428ef0-4511-25df-e8fe-988d96d0e2f6@linux.intel.com>
On 3/20/26 03:25, Ilpo Järvinen wrote:
> On Mon, 2 Mar 2026, Xi Pardee wrote:
>
>> Enable the Package C-state LTR blocking counter in the PMT telemetry
>> region. This counter records how many times any Package C-state entry
>> is blocked for the specified reasons.
>>
>> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
>> ---
>> drivers/platform/x86/intel/pmc/core.c | 77 ++++++++++++++++++++++-----
>> drivers/platform/x86/intel/pmc/core.h | 15 +++++-
>> 2 files changed, 79 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
>> index 02b303418d185..bf95a1f2ba428 100644
>> --- a/drivers/platform/x86/intel/pmc/core.c
>> +++ b/drivers/platform/x86/intel/pmc/core.c
>> @@ -1071,6 +1071,28 @@ static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
>> }
>> DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
>>
>> +static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
>> +{
>> + struct pmc_dev *pmcdev = s->private;
>> + const char **pkgc_ltr_blocker_counters;
>> + u32 counter, offset;
>> + unsigned int i;
>> + int ret;
>> +
>> + offset = pmcdev->pkgc_ltr_blocker_offset;
>> + pkgc_ltr_blocker_counters = pmcdev->pkgc_ltr_blocker_counters;
>> + for (i = 0; pkgc_ltr_blocker_counters[i]; i++, offset++) {
>> + ret = pmt_telem_read32(pmcdev->pc_ep, offset,
>> + &counter, 1);
> Fits easily to one line. Though, I'm not sure if offset variable improves
> things, more like it makes this more complex than it need to be. To me it
> would look more straightforward to do just:
>
> ret = pmt_telem_read32(pmcdev->pc_ep,
> pmcdev->pkgc_ltr_blocker_offset + i,
> ...);
Will change in next version.
>> + if (ret)
>> + return ret;
>> + seq_printf(s, "%-30s %-30u\n", pkgc_ltr_blocker_counters[i], counter);
>> + }
>> +
>> + return 0;
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
>> +
>> static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
>> {
>> struct pmc_dev *pmcdev = s->private;
>> @@ -1322,7 +1344,7 @@ static struct telem_endpoint *pmc_core_register_endpoint(struct pci_dev *pcidev,
>> return ERR_PTR(-ENODEV);
>> }
>>
>> -void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
>> +void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>> {
>> struct telem_endpoint *ep;
>> struct pci_dev *pcidev;
>> @@ -1333,17 +1355,35 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
>> return;
>> }
>>
>> - ep = pmc_core_register_endpoint(pcidev, guids);
>> - pci_dev_put(pcidev);
>> - if (IS_ERR(ep)) {
>> - dev_err(&pmcdev->pdev->dev,
>> - "pmc_core: couldn't get DMU telem endpoint %ld",
>> - PTR_ERR(ep));
>> - return;
>> + if (pmc_dev_info->dmu_guids) {
>> + ep = pmc_core_register_endpoint(pcidev, pmc_dev_info->dmu_guids);
>> + if (IS_ERR(ep)) {
>> + dev_err(&pmcdev->pdev->dev,
>> + "pmc_core: couldn't get DMU telem endpoint %ld",
>> + PTR_ERR(ep));
>> + goto release_dev;
>> + }
>> +
>> + pmcdev->punit_ep = ep;
>> + pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
>> + }
>> +
>> + if (pmc_dev_info->pc_guid) {
>> + ep = pmt_telem_find_and_register_endpoint(pcidev, pmc_dev_info->pc_guid, 0);
>> + if (IS_ERR(ep)) {
>> + dev_err(&pmcdev->pdev->dev,
>> + "pmc_core: couldn't get Package C-state telem endpoint %ld",
>> + PTR_ERR(ep));
>> + goto release_dev;
>> + }
>> +
>> + pmcdev->pc_ep = ep;
>> + pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
>> + pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
>> }
>>
>> - pmcdev->punit_ep = ep;
>> - pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
>> +release_dev:
>> + pci_dev_put(pcidev);
> Use __free(pci_dev_put) instead of complicating the code flow.
> Please remember to place the variable declaration at the place of
> assignment (no = NULL; assignments with __free()). You may want to do the
> __free() conversion in own patch preceeding this.
Thanks!
Will change and add another patch to convert to use __free() in next
version.
Xi
^ permalink raw reply
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Aaron Kling @ 2026-03-30 21:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
In-Reply-To: <acqJWzQHi7ajuzml@baldur>
On Mon, Mar 30, 2026 at 9:33 AM Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> > From: Aaron Kling <webgeek1234@gmail.com>
> >
> > Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> > to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> > frequency by aggregating bandwidth requests of all CPU core with referenc
> > to the current OPP they are configured in by the LMH/EPSS hardware.
> >
> > The effect is a proper caches & DDR frequency scaling when CPU cores
> > changes frequency.
> >
> > The OPP tables were built using the downstream memlat ddr, llcc & l3
> > tables for each cluster types with the actual EPSS cpufreq LUT tables
> > from running a QCS8550 device.
> >
> > Also add the OSC L3 Cache controller node.
> >
> > Also add the interconnect entry for each cpu, with 3 different paths:
> > - CPU to Last Level Cache Controller (LLCC)
> > - Last Level Cache Controller (LLCC) to DDR
> > - L3 Cache from CPU to DDR interface
> >
>
> "8 out of 11 hunks FAILED", it seems things moved since you wrote this.
> Can you please help me by rebasing this onto linux-next and resubmitting
> it?
This was a conflict from the EAS patch. I have sent a new revision
rebased on today's -next.
Aaron
> Regards,
> Bjorn
>
> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 367 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -17,6 +17,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interconnect/qcom,icc.h>
> > #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> > +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > #include <dt-bindings/power/qcom,rpmhpd.h>
> > @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_0: l2-cache {
> > compatible = "cache";
> > @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_100: l2-cache {
> > compatible = "cache";
> > @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_200: l2-cache {
> > compatible = "cache";
> > @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_300: l2-cache {
> > compatible = "cache";
> > @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_400: l2-cache {
> > compatible = "cache";
> > @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_500: l2-cache {
> > compatible = "cache";
> > @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_600: l2-cache {
> > compatible = "cache";
> > @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> > qcom,freq-domain = <&cpufreq_hw 2>;
> > capacity-dmips-mhz = <1894>;
> > dynamic-power-coefficient = <588>;
> > + operating-points-v2 = <&cpu7_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_700: l2-cache {
> > compatible = "cache";
> > @@ -397,6 +454,306 @@ memory@a0000000 {
> > reg = <0 0xa0000000 0 0>;
> > };
> >
> > + cpu0_opp_table: opp-table-cpu0 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-307200000 {
> > + opp-hz = /bits/ 64 <307200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-441600000 {
> > + opp-hz = /bits/ 64 <441600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> > + };
> > +
> > + opp-556800000 {
> > + opp-hz = /bits/ 64 <556800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-672000000 {
> > + opp-hz = /bits/ 64 <672000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-787200000 {
> > + opp-hz = /bits/ 64 <787200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-902400000 {
> > + opp-hz = /bits/ 64 <902400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> > + };
> > +
> > + opp-1017600000 {
> > + opp-hz = /bits/ 64 <1017600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1113600000 {
> > + opp-hz = /bits/ 64 <1113600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1228800000 {
> > + opp-hz = /bits/ 64 <1228800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> > + };
> > +
> > + opp-1344000000 {
> > + opp-hz = /bits/ 64 <1344000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1459200000 {
> > + opp-hz = /bits/ 64 <1459200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1555200000 {
> > + opp-hz = /bits/ 64 <1555200000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1670400000 {
> > + opp-hz = /bits/ 64 <1670400000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1900800000 {
> > + opp-hz = /bits/ 64 <1900800000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2016000000 {
> > + opp-hz = /bits/ 64 <2016000000>;
> > + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> > + };
> > + };
> > +
> > + cpu3_opp_table: opp-table-cpu3 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-499200000 {
> > + opp-hz = /bits/ 64 <499200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-614400000 {
> > + opp-hz = /bits/ 64 <614400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-844800000 {
> > + opp-hz = /bits/ 64 <844800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-940800000 {
> > + opp-hz = /bits/ 64 <940800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1056000000 {
> > + opp-hz = /bits/ 64 <1056000000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1171200000 {
> > + opp-hz = /bits/ 64 <1171200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1286400000 {
> > + opp-hz = /bits/ 64 <1286400000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1401600000 {
> > + opp-hz = /bits/ 64 <1401600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1536000000 {
> > + opp-hz = /bits/ 64 <1536000000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1651200000 {
> > + opp-hz = /bits/ 64 <1651200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1920000000 {
> > + opp-hz = /bits/ 64 <1920000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2054400000 {
> > + opp-hz = /bits/ 64 <2054400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2188800000 {
> > + opp-hz = /bits/ 64 <2188800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2323200000 {
> > + opp-hz = /bits/ 64 <2323200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2457600000 {
> > + opp-hz = /bits/ 64 <2457600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2707200000 {
> > + opp-hz = /bits/ 64 <2707200000>;
> > + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2803200000 {
> > + opp-hz = /bits/ 64 <2803200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > + cpu7_opp_table: opp-table-cpu7 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-595200000 {
> > + opp-hz = /bits/ 64 <595200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-864000000 {
> > + opp-hz = /bits/ 64 <864000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-998400000 {
> > + opp-hz = /bits/ 64 <998400000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1132800000 {
> > + opp-hz = /bits/ 64 <1132800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1248000000 {
> > + opp-hz = /bits/ 64 <1248000000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1363200000 {
> > + opp-hz = /bits/ 64 <1363200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1478400000 {
> > + opp-hz = /bits/ 64 <1478400000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1593600000 {
> > + opp-hz = /bits/ 64 <1593600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1708800000 {
> > + opp-hz = /bits/ 64 <1708800000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1843200000 {
> > + opp-hz = /bits/ 64 <1843200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1977600000 {
> > + opp-hz = /bits/ 64 <1977600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2092800000 {
> > + opp-hz = /bits/ 64 <2092800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2227200000 {
> > + opp-hz = /bits/ 64 <2227200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2342400000 {
> > + opp-hz = /bits/ 64 <2342400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2476800000 {
> > + opp-hz = /bits/ 64 <2476800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2726400000 {
> > + opp-hz = /bits/ 64 <2726400000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2841600000 {
> > + opp-hz = /bits/ 64 <2841600000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2956800000 {
> > + opp-hz = /bits/ 64 <2956800000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-3187200000 {
> > + opp-hz = /bits/ 64 <3187200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > pmu-a510 {
> > compatible = "arm,cortex-a510-pmu";
> > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> > @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> > };
> > };
> >
> > + epss_l3: interconnect@17d90000 {
> > + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> > + reg = <0 0x17d90000 0 0x1000>;
> > +
> > + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> > + clock-names = "xo", "alternate";
> > +
> > + #interconnect-cells = <1>;
> > + };
> > +
> > cpufreq_hw: cpufreq@17d91000 {
> > compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> > reg = <0 0x17d91000 0 0x1000>,
> >
> > --
> > 2.52.0
> >
> >
^ permalink raw reply
* [PATCH v4] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Aaron Kling via B4 Relay @ 2026-03-30 21:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm, Neil Armstrong,
Konrad Dybcio, Dmitry Baryshkov, Aaron Kling
From: Aaron Kling <webgeek1234@gmail.com>
Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
frequency by aggregating bandwidth requests of all CPU core with referenc
to the current OPP they are configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
changes frequency.
The OPP tables were built using the downstream memlat ddr, llcc & l3
tables for each cluster types with the actual EPSS cpufreq LUT tables
from running a QCS8550 device.
Also add the OSC L3 Cache controller node.
Also add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.
---
Changes in v4:
- Rebase on -next and resolve merge conflicts
- Drop patch 1 as it was already picked up
- Link to v3: https://lore.kernel.org/r/20260219-sm8550-ddr-bw-scaling-v3-0-75c19152e921@gmail.com
Changes in v3:
- Squash the last two patches
- Link to v2: https://lore.kernel.org/r/20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com
Changes in v2:
- Squash first two patches
- Update opp tables in last patch to match how the downstream driver
parses those tables
- Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..b7a7c49db077bd36f5705efeae427287eb23ffe4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -78,6 +79,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -104,6 +112,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_100: l2-cache {
compatible = "cache";
@@ -125,6 +140,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <326>;
dynamic-power-coefficient = <251>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
@@ -146,6 +168,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
@@ -167,6 +196,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
@@ -188,6 +224,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
@@ -209,6 +252,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <693>;
dynamic-power-coefficient = <447>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
@@ -230,6 +280,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <1057>;
+ operating-points-v2 = <&cpu7_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
@@ -397,6 +454,306 @@ memory@a0000000 {
reg = <0 0xa0000000 0 0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
+ };
+
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-499200000 {
+ opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1171200000 {
+ opp-hz = /bits/ 64 <1171200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2803200000 {
+ opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2092800000 {
+ opp-hz = /bits/ 64 <2092800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2227200000 {
+ opp-hz = /bits/ 64 <2227200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2476800000 {
+ opp-hz = /bits/ 64 <2476800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2726400000 {
+ opp-hz = /bits/ 64 <2726400000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2841600000 {
+ opp-hz = /bits/ 64 <2841600000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2956800000 {
+ opp-hz = /bits/ 64 <2956800000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-3187200000 {
+ opp-hz = /bits/ 64 <3187200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
pmu-a510 {
compatible = "arm,cortex-a510-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -5482,6 +5839,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ epss_l3: interconnect@17d90000 {
+ compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
+ reg = <0 0x17d90000 0 0x1000>;
+
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x17d91000 0 0x1000>,
---
base-commit: cf7c3c02fdd0dfccf4d6611714273dcb538af2cb
change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply related
* [rafael-pm:bleeding-edge 175/181] drivers/powercap/intel_rapl_common.c:1143:25: error: use of undeclared identifier 'IOSF_CPU_POWER_BUDGET_CTL_BYT'
From: kernel test robot @ 2026-03-30 21:24 UTC (permalink / raw)
To: Kuppuswamy Sathyanarayanan
Cc: llvm, oe-kbuild-all, linux-acpi, linux-pm, Rafael J. Wysocki
Hi Kuppuswamy,
FYI, the error/warning was bisected to this commit, please ignore it if it's irrelevant.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git bleeding-edge
head: a4b9106c1c54a3f214009aa006cf31f9329b6b27
commit: 6cec0a0079bc188fbb9f0363c11973a81f8fbf9c [175/181] powercap: intel_rapl: Remove unused macro definitions
config: x86_64-rhel-9.4-rust (https://download.01.org/0day-ci/archive/20260331/202603310544.0WC7CT1o-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
rustc: rustc 1.88.0 (6b00bc388 2025-06-23)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260331/202603310544.0WC7CT1o-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603310544.0WC7CT1o-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/powercap/intel_rapl_common.c:1143:25: error: use of undeclared identifier 'IOSF_CPU_POWER_BUDGET_CTL_BYT'
1143 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
| ^
>> drivers/powercap/intel_rapl_common.c:1150:25: error: use of undeclared identifier 'IOSF_CPU_POWER_BUDGET_CTL_TNG'
1150 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
| ^
2 errors generated.
vim +/IOSF_CPU_POWER_BUDGET_CTL_BYT +1143 drivers/powercap/intel_rapl_common.c
2d798d9f5967a3 drivers/powercap/intel_rapl_common.c Zhang Rui 2020-06-29 1141
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1142 static const struct rapl_defaults rapl_defaults_byt = {
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 @1143 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1144 .check_unit = rapl_check_unit_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1145 .set_floor_freq = set_floor_freq_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1146 .compute_time_window = rapl_compute_time_window_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1147 };
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1148
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1149 static const struct rapl_defaults rapl_defaults_tng = {
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 @1150 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1151 .check_unit = rapl_check_unit_atom,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1152 .set_floor_freq = set_floor_freq_atom,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1153 .compute_time_window = rapl_compute_time_window_atom,
087e9cbab5022f drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1154 };
087e9cbab5022f drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1155
:::::: The code at line 1143 was first introduced by commit
:::::: 51b63409b75980753f52edb45da7d1b3e2b9405d powercap / RAPL: Floor frequency setting in Atom SoC
:::::: TO: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [rafael-pm:testing 161/166] drivers/powercap/intel_rapl_common.c:1143:32: error: 'IOSF_CPU_POWER_BUDGET_CTL_BYT' undeclared here (not in a function)
From: kernel test robot @ 2026-03-30 20:38 UTC (permalink / raw)
To: Kuppuswamy Sathyanarayanan
Cc: oe-kbuild-all, linux-acpi, linux-pm, Rafael J. Wysocki
Hi Kuppuswamy,
FYI, the error/warning was bisected to this commit, please ignore it if it's irrelevant.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git testing
head: 42d55832a5e041da2575cf582669755d6d0f9a45
commit: 6cec0a0079bc188fbb9f0363c11973a81f8fbf9c [161/166] powercap: intel_rapl: Remove unused macro definitions
config: x86_64-rhel-9.4 (https://download.01.org/0day-ci/archive/20260331/202603310439.J9wmW1hQ-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260331/202603310439.J9wmW1hQ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603310439.J9wmW1hQ-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/powercap/intel_rapl_common.c:1143:32: error: 'IOSF_CPU_POWER_BUDGET_CTL_BYT' undeclared here (not in a function)
1143 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/powercap/intel_rapl_common.c:1150:32: error: 'IOSF_CPU_POWER_BUDGET_CTL_TNG' undeclared here (not in a function)
1150 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/IOSF_CPU_POWER_BUDGET_CTL_BYT +1143 drivers/powercap/intel_rapl_common.c
2d798d9f5967a3 drivers/powercap/intel_rapl_common.c Zhang Rui 2020-06-29 1141
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1142 static const struct rapl_defaults rapl_defaults_byt = {
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 @1143 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1144 .check_unit = rapl_check_unit_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1145 .set_floor_freq = set_floor_freq_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1146 .compute_time_window = rapl_compute_time_window_atom,
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1147 };
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1148
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 1149 static const struct rapl_defaults rapl_defaults_tng = {
51b63409b75980 drivers/powercap/intel_rapl.c Ajay Thomas 2015-04-30 @1150 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1151 .check_unit = rapl_check_unit_atom,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1152 .set_floor_freq = set_floor_freq_atom,
3c2c08454ce9ca drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1153 .compute_time_window = rapl_compute_time_window_atom,
087e9cbab5022f drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1154 };
087e9cbab5022f drivers/powercap/intel_rapl.c Jacob Pan 2014-11-07 1155
:::::: The code at line 1143 was first introduced by commit
:::::: 51b63409b75980753f52edb45da7d1b3e2b9405d powercap / RAPL: Floor frequency setting in Atom SoC
:::::: TO: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v8 0/2] cpufreq: Introduce boost frequency QoS
From: Rafael J. Wysocki @ 2026-03-30 19:58 UTC (permalink / raw)
To: Pierre Gondois
Cc: Viresh Kumar, linux-kernel, Lifeng Zheng, Huang Rui,
Gautham R. Shenoy, Mario Limonciello, Perry Yuan,
Rafael J. Wysocki, linux-pm
In-Reply-To: <d13a7a60-dcee-483e-8ea8-a551ca2db467@arm.com>
On Fri, Mar 27, 2026 at 5:09 PM Pierre Gondois <pierre.gondois@arm.com> wrote:
>
>
> On 3/27/26 04:43, Viresh Kumar wrote:
> > On 26-03-26, 21:43, Pierre Gondois wrote:
> >> Pierre Gondois (2):
> >> cpufreq: Remove max_freq_req update for pre-existing policy
> >> cpufreq: Add boost_freq_req QoS request
> >>
> >> drivers/cpufreq/amd-pstate.c | 2 --
> >> drivers/cpufreq/cppc_cpufreq.c | 10 ++-----
> >> drivers/cpufreq/cpufreq.c | 50 +++++++++++++++++++++-------------
> >> include/linux/cpufreq.h | 1 +
> >> 4 files changed, 34 insertions(+), 29 deletions(-)
> > Thanks Pierre for your patience.
> Thanks for the review (to Lifeng aswell)
> >
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied as 7.1 material, thanks!
^ permalink raw reply
* Re: [PATCH] PM: EM: Fix null-ptr-deref in get-perf-domains when ID is not found
From: Rafael J. Wysocki @ 2026-03-30 19:46 UTC (permalink / raw)
To: Changwoo Min
Cc: lukasz.luba, rafael, lenb, pavel, donald.hunter, kernel-dev,
linux-pm, linux-kernel, Yi Lai
In-Reply-To: <20260329073615.649976-1-changwoo@igalia.com>
On Sun, Mar 29, 2026 at 9:36 AM Changwoo Min <changwoo@igalia.com> wrote:
>
> dev_energymodel_nl_get_perf_domains_doit() calls
> em_perf_domain_get_by_id() but does not check the return value before
> passing it to __em_nl_get_pd_size(). When a caller supplies a
> non-existent perf domain ID, em_perf_domain_get_by_id() returns NULL,
> and __em_nl_get_pd_size() immediately dereferences pd->cpus
> (struct offset 0x30), causing a null-pointer dereference.
>
> The sister handler dev_energymodel_nl_get_perf_table_doit() already
> handles this correctly via __em_nl_get_pd_table_id(), which returns
> NULL and causes the caller to return -EINVAL. Add the same NULL check
> in the get-perf-domains do handler.
>
> Fixes: 380ff27af25e ("PM: EM: Add dump to get-perf-domains in the EM YNL spec")
> Reported-by: Yi Lai <yi1.lai@linux.intel.com>
> Closes: https://lore.kernel.org/lkml/aXiySM79UYfk+ytd@ly-workstation/
> Signed-off-by: Changwoo Min <changwoo@igalia.com>
> ---
> kernel/power/em_netlink.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/kernel/power/em_netlink.c b/kernel/power/em_netlink.c
> index 5a611d3950fd..4d4fd29bd2be 100644
> --- a/kernel/power/em_netlink.c
> +++ b/kernel/power/em_netlink.c
> @@ -109,6 +109,8 @@ int dev_energymodel_nl_get_perf_domains_doit(struct sk_buff *skb,
>
> id = nla_get_u32(info->attrs[DEV_ENERGYMODEL_A_PERF_DOMAIN_PERF_DOMAIN_ID]);
> pd = em_perf_domain_get_by_id(id);
> + if (!pd)
> + return -EINVAL;
>
> __em_nl_get_pd_size(pd, &msg_sz);
> msg = genlmsg_new(msg_sz, GFP_KERNEL);
> --
Applied as 7.0-rc material, thanks!
^ permalink raw reply
* Re: [PATCH v7 3/8] serdev: Do not return -ENODEV from of_serdev_register_devices() if external connector is used
From: Rob Herring @ 2026-03-30 19:29 UTC (permalink / raw)
To: manivannan.sadhasivam
Cc: Greg Kroah-Hartman, Jiri Slaby, Nathan Chancellor, Nicolas Schier,
Hans de Goede, Ilpo Järvinen, Mark Pearson, Derek J. Clark,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Marcel Holtmann, Luiz Augusto von Dentz, Bartosz Golaszewski,
Andy Shevchenko, Bartosz Golaszewski, linux-serial, linux-kernel,
linux-kbuild, platform-driver-x86, linux-pci, devicetree,
linux-arm-msm, linux-bluetooth, linux-pm, Stephan Gerhold,
Dmitry Baryshkov, linux-acpi, Hans de Goede
In-Reply-To: <20260326-pci-m2-e-v7-3-43324a7866e6@oss.qualcomm.com>
On Thu, Mar 26, 2026 at 01:36:31PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> If an external connector like M.2 is connected to the serdev controller
> in DT, then the serdev devices may be created dynamically by the connector
> driver. So do not return -ENODEV from of_serdev_register_devices() if the
> static nodes are not found and the graph node is used.
>
> Tested-by: Hans de Goede <johannes.goede@oss.qualcomm.com> # ThinkPad T14s gen6 (arm64)
> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> drivers/tty/serdev/core.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v7 2/8] serdev: Add an API to find the serdev controller associated with the devicetree node
From: Rob Herring @ 2026-03-30 19:28 UTC (permalink / raw)
To: manivannan.sadhasivam
Cc: Greg Kroah-Hartman, Jiri Slaby, Nathan Chancellor, Nicolas Schier,
Hans de Goede, Ilpo Järvinen, Mark Pearson, Derek J. Clark,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Marcel Holtmann, Luiz Augusto von Dentz, Bartosz Golaszewski,
Andy Shevchenko, Bartosz Golaszewski, linux-serial, linux-kernel,
linux-kbuild, platform-driver-x86, linux-pci, devicetree,
linux-arm-msm, linux-bluetooth, linux-pm, Stephan Gerhold,
Dmitry Baryshkov, linux-acpi, Hans de Goede, Bartosz Golaszewski
In-Reply-To: <20260326-pci-m2-e-v7-2-43324a7866e6@oss.qualcomm.com>
On Thu, Mar 26, 2026 at 01:36:30PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> Add of_find_serdev_controller_by_node() API to find the serdev controller
> device associated with the devicetree node.
>
> Tested-by: Hans de Goede <johannes.goede@oss.qualcomm.com> # ThinkPad T14s gen6 (arm64)
> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> drivers/tty/serdev/core.c | 19 +++++++++++++++++++
> include/linux/serdev.h | 9 +++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v7 1/8] serdev: Convert to_serdev_*() helpers to macros and use container_of_const()
From: Rob Herring @ 2026-03-30 19:28 UTC (permalink / raw)
To: manivannan.sadhasivam
Cc: Greg Kroah-Hartman, Jiri Slaby, Nathan Chancellor, Nicolas Schier,
Hans de Goede, Ilpo Järvinen, Mark Pearson, Derek J. Clark,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Marcel Holtmann, Luiz Augusto von Dentz, Bartosz Golaszewski,
Andy Shevchenko, Bartosz Golaszewski, linux-serial, linux-kernel,
linux-kbuild, platform-driver-x86, linux-pci, devicetree,
linux-arm-msm, linux-bluetooth, linux-pm, Stephan Gerhold,
Dmitry Baryshkov, linux-acpi, Hans de Goede
In-Reply-To: <20260326-pci-m2-e-v7-1-43324a7866e6@oss.qualcomm.com>
On Thu, Mar 26, 2026 at 01:36:29PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> If these helpers receive the 'const struct device' pointer, then the const
> qualifier will get dropped, leading to below warning:
>
> warning: passing argument 1 of ‘to_serdev_device_driver’ discards 'const'
> qualifier from pointer target type [-Wdiscarded-qualifiers]
>
> This is not an issue as of now, but with the future commits adding serdev
> device based driver matching, this warning will get triggered. Hence,
> convert these helpers to macros so that the qualifier get preserved and
> also use container_of_const() as container_of() is deprecated.
>
> Tested-by: Hans de Goede <johannes.goede@oss.qualcomm.com> # ThinkPad T14s gen6 (arm64)
> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> include/linux/serdev.h | 15 +++------------
> 1 file changed, 3 insertions(+), 12 deletions(-)
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* [PATCH] Documentation: amd-pstate: fix dead links in the reference section
From: Ninad Naik @ 2026-03-30 19:08 UTC (permalink / raw)
To: ray.huang, gautham.shenoy, mario.limonciello, perry.yuan, corbet,
skhan
Cc: linux-pm, linux-doc, linux-kernel, me, Ninad Naik
The links for AMD64 Architecture Programmer's Manual and PPR for AMD
Family 19h Model 51h, Revision A1 Processors redirect to a generic page.
Update the links to the working ones.
Signed-off-by: Ninad Naik <ninadnaik07@gmail.com>
---
Documentation/admin-guide/pm/amd-pstate.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
index e1771f2225d5..13d6580894bc 100644
--- a/Documentation/admin-guide/pm/amd-pstate.rst
+++ b/Documentation/admin-guide/pm/amd-pstate.rst
@@ -790,13 +790,13 @@ Reference
===========
.. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming,
- https://www.amd.com/system/files/TechDocs/24593.pdf
+ https://docs.amd.com/v/u/en-US/24593_3.44_APM_Vol2
.. [2] Advanced Configuration and Power Interface Specification,
https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
.. [3] Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors
- https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip
+ https://docs.amd.com/v/u/en-US/56569-A1-PUB_3.03
.. [4] Linux Kernel Selftests,
https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v5 2/2] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
From: Dmitry Baryshkov @ 2026-03-30 18:44 UTC (permalink / raw)
To: Richard Acayan
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Amit Kucheria, Thara Gopinath, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, linux-arm-msm, devicetree,
linux-pm
In-Reply-To: <20260330165237.101045-3-mailingradian@gmail.com>
On Mon, Mar 30, 2026 at 12:52:37PM -0400, Richard Acayan wrote:
> Add thermal zones to safeguard from overheating to high temperatures,
> along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
> The temperatures are very high, but should still be safeguard for
> devices that do not specify their own thermal zones.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 400 +++++++++++++++++++++++++++
> 1 file changed, 400 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v5 1/2] thermal/qcom/lmh: support SDM670 and its CPU clusters
From: Dmitry Baryshkov @ 2026-03-30 18:43 UTC (permalink / raw)
To: Richard Acayan
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Amit Kucheria, Thara Gopinath, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, linux-arm-msm, devicetree,
linux-pm
In-Reply-To: <20260330165237.101045-2-mailingradian@gmail.com>
On Mon, Mar 30, 2026 at 12:52:36PM -0400, Richard Acayan wrote:
> The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but
> some SoCs divide the CPUs into different sizes of clusters. In SDM670,
> the first 6 CPUs are in the little cluster and the next 2 are in the big
> cluster. Define the clusters in the match data and define the different
> cluster configuration for SDM670.
>
> Currently, this tolerates linking to any CPU in a given cluster.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> drivers/thermal/qcom/lmh.c | 54 ++++++++++++++++++++++++--------------
> 1 file changed, 34 insertions(+), 20 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v5 2/2] arm64: dts: qcom: sdm670: add thermal zones and thermal devices
From: Richard Acayan @ 2026-03-30 16:52 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Amit Kucheria, Thara Gopinath, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, linux-arm-msm, devicetree,
linux-pm
Cc: Richard Acayan
In-Reply-To: <20260330165237.101045-1-mailingradian@gmail.com>
Add thermal zones to safeguard from overheating to high temperatures,
along with the thermal sensors (TSENS) and CPU frequency limits (LMh).
The temperatures are very high, but should still be safeguard for
devices that do not specify their own thermal zones.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 400 +++++++++++++++++++++++++++
1 file changed, 400 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index f115bc6e64f3..c5f7655421a3 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -20,6 +20,7 @@
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -62,6 +63,7 @@ cpu0: cpu@0 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
@@ -89,6 +91,7 @@ cpu1: cpu@100 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
@@ -111,6 +114,7 @@ cpu2: cpu@200 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
@@ -133,6 +137,7 @@ cpu3: cpu@300 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
@@ -155,6 +160,7 @@ cpu4: cpu@400 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_400>;
l2_400: l2-cache {
compatible = "cache";
@@ -177,6 +183,7 @@ cpu5: cpu@500 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_500>;
l2_500: l2-cache {
compatible = "cache";
@@ -199,6 +206,7 @@ cpu6: cpu@600 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_600>;
l2_600: l2-cache {
compatible = "cache";
@@ -221,6 +229,7 @@ cpu7: cpu@700 {
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
+ #cooling-cells = <2>;
next-level-cache = <&l2_700>;
l2_700: l2-cache {
compatible = "cache";
@@ -1408,6 +1417,8 @@ gpu: gpu@5000000 {
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
+
status = "disabled";
gpu_zap_shader: zap-shader {
@@ -2100,6 +2111,28 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
};
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1000>,
+ <0 0x0c222000 0 0x1000>;
+ interrupts-extended = <&pdc 26 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 28 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <13>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sdm670-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1000>,
+ <0 0x0c223000 0 0x1000>;
+ interrupts-extended = <&pdc 27 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 29 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <8>;
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
@@ -2289,5 +2322,372 @@ cpufreq_hw: cpufreq@17d43000 {
#freq-domain-cells = <1>;
};
+
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu6>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu0>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cluster0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cluster0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cluster1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cluster1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu5_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ gpu0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-modem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ q6_modem_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ mem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ mem_crit: trip-point1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wlan-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ wlan_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-hvx-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ q6_hvx_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ camera_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ video_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ modem_crit: trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH v5 1/2] thermal/qcom/lmh: support SDM670 and its CPU clusters
From: Richard Acayan @ 2026-03-30 16:52 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Amit Kucheria, Thara Gopinath, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, linux-arm-msm, devicetree,
linux-pm
Cc: Richard Acayan
In-Reply-To: <20260330165237.101045-1-mailingradian@gmail.com>
The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but
some SoCs divide the CPUs into different sizes of clusters. In SDM670,
the first 6 CPUs are in the little cluster and the next 2 are in the big
cluster. Define the clusters in the match data and define the different
cluster configuration for SDM670.
Currently, this tolerates linking to any CPU in a given cluster.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
drivers/thermal/qcom/lmh.c | 54 ++++++++++++++++++++++++--------------
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
index 3d072b7a4a6d..81ab2f0be9c8 100644
--- a/drivers/thermal/qcom/lmh.c
+++ b/drivers/thermal/qcom/lmh.c
@@ -30,14 +30,17 @@
#define LMH_REG_DCVS_INTR_CLR 0x8
-#define LMH_ENABLE_ALGOS 1
-
struct lmh_hw_data {
void __iomem *base;
struct irq_domain *domain;
int irq;
};
+struct lmh_soc_data {
+ bool enable_algos;
+ unsigned int clus1_start_idx;
+};
+
static irqreturn_t lmh_handle_irq(int hw_irq, void *data)
{
struct lmh_hw_data *lmh_data = data;
@@ -100,8 +103,8 @@ static int lmh_probe(struct platform_device *pdev)
struct device_node *np = dev->of_node;
struct device_node *cpu_node;
struct lmh_hw_data *lmh_data;
+ const struct lmh_soc_data *match_data;
int temp_low, temp_high, temp_arm, cpu_id, ret;
- unsigned int enable_alg;
u32 node_id;
if (!qcom_scm_is_available())
@@ -121,6 +124,11 @@ static int lmh_probe(struct platform_device *pdev)
cpu_id = of_cpu_node_to_id(cpu_node);
of_node_put(cpu_node);
+ if (cpu_id < 0) {
+ dev_err(dev, "Wrong CPU id associated with LMh node\n");
+ return -EINVAL;
+ }
+
ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high);
if (ret) {
dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n");
@@ -139,26 +147,16 @@ static int lmh_probe(struct platform_device *pdev)
return ret;
}
- /*
- * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed
- * for other platforms, revisit this to check if the <cpu-id, node-id> should be part
- * of a dt match table.
- */
- if (cpu_id == 0) {
+ match_data = of_device_get_match_data(dev);
+ if (cpu_id < match_data->clus1_start_idx)
node_id = LMH_CLUSTER0_NODE_ID;
- } else if (cpu_id == 4) {
+ else
node_id = LMH_CLUSTER1_NODE_ID;
- } else {
- dev_err(dev, "Wrong CPU id associated with LMh node\n");
- return -EINVAL;
- }
if (!qcom_scm_lmh_dcvsh_available())
return -EINVAL;
- enable_alg = (uintptr_t)of_device_get_match_data(dev);
-
- if (enable_alg) {
+ if (match_data->enable_algos) {
ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
LMH_NODE_DCVS, node_id, 0);
if (ret)
@@ -231,10 +229,26 @@ static int lmh_probe(struct platform_device *pdev)
return 0;
}
+static const struct lmh_soc_data sdm670_lmh_data = {
+ .enable_algos = true,
+ .clus1_start_idx = 6,
+};
+
+static const struct lmh_soc_data sdm845_lmh_data = {
+ .enable_algos = true,
+ .clus1_start_idx = 4,
+};
+
+static const struct lmh_soc_data sm8150_lmh_data = {
+ .enable_algos = false,
+ .clus1_start_idx = 4,
+};
+
static const struct of_device_id lmh_table[] = {
- { .compatible = "qcom,sc8180x-lmh", },
- { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
- { .compatible = "qcom,sm8150-lmh", },
+ { .compatible = "qcom,sc8180x-lmh", .data = &sm8150_lmh_data },
+ { .compatible = "qcom,sdm670-lmh", .data = &sdm670_lmh_data },
+ { .compatible = "qcom,sdm845-lmh", .data = &sdm845_lmh_data },
+ { .compatible = "qcom,sm8150-lmh", .data = &sm8150_lmh_data },
{}
};
MODULE_DEVICE_TABLE(of, lmh_table);
--
2.53.0
^ permalink raw reply related
* [PATCH v5 0/2] SDM670 Basic SoC thermal zones
From: Richard Acayan @ 2026-03-30 16:52 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Amit Kucheria, Thara Gopinath, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, linux-arm-msm, devicetree,
linux-pm
Cc: Richard Acayan
This adds support for the thermal sensor, for thermal-based CPU
throttling via LMh, and for thermal zones.
Changes since v4 (https://lore.kernel.org/r/20260328014041.83777-1-mailingradian@gmail.com):
- use simple comparison to differentiate between cluster 0 and 1 (1/2)
- drop applied dt-bindings patches (previously 1-2/4)
Changes since v3 (https://lore.kernel.org/r/20260310002037.1863-1-mailingradian@gmail.com):
- support LMh clusters starting at CPU 6 (dt-bindings tag dropped) (3/4)
Changes since v2 (https://lore.kernel.org/r/20260304014530.27775-1-mailingradian@gmail.com):
- remove cooling from memory thermal zone (3/3)
Changes since v1 (https://lore.kernel.org/r/20260210021607.12576-1-mailingradian@gmail.com):
- add review tag from Krzysztof (1/3)
- replace CPU thermal zones with lmh (2/3, 3/3)
Richard Acayan (2):
thermal/qcom/lmh: support SDM670 and its CPU clusters
arm64: dts: qcom: sdm670: add thermal zones and thermal devices
arch/arm64/boot/dts/qcom/sdm670.dtsi | 400 +++++++++++++++++++++++++++
drivers/thermal/qcom/lmh.c | 54 ++--
2 files changed, 434 insertions(+), 20 deletions(-)
--
2.53.0
^ permalink raw reply
* Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path
From: Luca Weiss @ 2026-03-30 14:55 UTC (permalink / raw)
To: Mike Tipton, Konrad Dybcio
Cc: Krzysztof Kozlowski, Luca Weiss, Taniya Das, Georgi Djakov,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, ~postmarketos/upstreaming,
phone-devel, linux-pm, linux-kernel, linux-arm-msm, linux-clk,
devicetree
In-Reply-To: <acH7aEBvSbiNwhBz@hu-mdtipton-lv.qualcomm.com>
Hi Mike,
On Tue Mar 24, 2026 at 3:48 AM CET, Mike Tipton wrote:
> On Mon, Jan 19, 2026 at 11:28:07AM +0100, Konrad Dybcio wrote:
>>
>>
>> On 1/19/26 11:20 AM, Konrad Dybcio wrote:
>> > On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote:
>> >> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote:
>> >>> Document an interconnect path for camcc that's required to enable
>> >>> the CAMSS_TOP_GDSC power domain.
>> >>
>> >> I find it confusing. Enabling GDSC power domains is done via power
>> >> domains, not via interconnects. Do not represent power domains as
>> >> interconnects, it's something completely different.
>> >
>> > The name of the power domains is CAMSS_TOP_GDSC (seems you misread)
>> >
>> > For the power domain to successfully turn on, the MNoC needs to be
>> > turned on (empirical evidence). The way to do it is to request a
>> > nonzero vote on this interconnect path
>> >
>> > (presumably because the GDSC or its invisible providers require
>> > something connected over that bus to carry out their enable sequences).
>
> The GDSC itself shouldn't depend on MMNOC in order to turn on properly.
> It should turn on just fine without it. There *is* a dependency between
> CAM_TOP_GDSC and MMNOC, but it's in the opposite direction.
I can personally just write from practical experience, as Qualcomm
doesn't share any relevant documentation with OEMs.
Without this patch the GDSC refuses to turn on.
[ 291.055839] ------------[ cut here ]------------
[ 291.055860] cam_cc_camss_top_gdsc status stuck at 'off'
[ 291.055878] WARNING: drivers/clk/qcom/gdsc.c:178 at gdsc_toggle_logic+0x138/0x144, CPU#4: hexdump/1995
With the patch it turns on just fine, no issues seen.
As Konrad has written, originally I didn't see any issue because that
interconnect was being kept alive by simple-framebuffer where I've added
'interconnects' to keep the framebuffer alive. However when testing
without this, the GDSC would refuse to turn on, which led me to this
patch series.
Additionally you can see in downstream devicetree you can also see an
interconnect defined for the "cam_cc_camss_top_gdsc" node:
https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/qcom/proprietary/devicetree/+/refs/heads/odm/rc/target/15/fp6/fps_overlay/volcano.dtsi#2943
Regards
Luca
^ permalink raw reply
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
From: Bjorn Andersson @ 2026-03-30 14:33 UTC (permalink / raw)
To: webgeek1234
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
In-Reply-To: <20260219-sm8550-ddr-bw-scaling-v3-2-75c19152e921@gmail.com>
On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
>
> Also add the OSC L3 Cache controller node.
>
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
"8 out of 11 hunks FAILED", it seems things moved since you wrote this.
Can you please help me by rebasing this onto linux-next and resubmitting
it?
Regards,
Bjorn
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> 1 file changed, 367 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -17,6 +17,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_0: l2-cache {
> compatible = "cache";
> @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_100: l2-cache {
> compatible = "cache";
> @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_200: l2-cache {
> compatible = "cache";
> @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_300: l2-cache {
> compatible = "cache";
> @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_400: l2-cache {
> compatible = "cache";
> @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_500: l2-cache {
> compatible = "cache";
> @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_600: l2-cache {
> compatible = "cache";
> @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> qcom,freq-domain = <&cpufreq_hw 2>;
> capacity-dmips-mhz = <1894>;
> dynamic-power-coefficient = <588>;
> + operating-points-v2 = <&cpu7_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_700: l2-cache {
> compatible = "cache";
> @@ -397,6 +454,306 @@ memory@a0000000 {
> reg = <0 0xa0000000 0 0>;
> };
>
> + cpu0_opp_table: opp-table-cpu0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-441600000 {
> + opp-hz = /bits/ 64 <441600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> + };
> +
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-672000000 {
> + opp-hz = /bits/ 64 <672000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-787200000 {
> + opp-hz = /bits/ 64 <787200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> + };
> +
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> + };
> +
> + opp-1017600000 {
> + opp-hz = /bits/ 64 <1017600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> + };
> +
> + opp-1344000000 {
> + opp-hz = /bits/ 64 <1344000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1459200000 {
> + opp-hz = /bits/ 64 <1459200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1555200000 {
> + opp-hz = /bits/ 64 <1555200000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2016000000 {
> + opp-hz = /bits/ 64 <2016000000>;
> + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> + };
> + };
> +
> + cpu3_opp_table: opp-table-cpu3 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-499200000 {
> + opp-hz = /bits/ 64 <499200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-844800000 {
> + opp-hz = /bits/ 64 <844800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-940800000 {
> + opp-hz = /bits/ 64 <940800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1171200000 {
> + opp-hz = /bits/ 64 <1171200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1536000000 {
> + opp-hz = /bits/ 64 <1536000000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1651200000 {
> + opp-hz = /bits/ 64 <1651200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2323200000 {
> + opp-hz = /bits/ 64 <2323200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2457600000 {
> + opp-hz = /bits/ 64 <2457600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2707200000 {
> + opp-hz = /bits/ 64 <2707200000>;
> + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2803200000 {
> + opp-hz = /bits/ 64 <2803200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> + cpu7_opp_table: opp-table-cpu7 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-595200000 {
> + opp-hz = /bits/ 64 <595200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-864000000 {
> + opp-hz = /bits/ 64 <864000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-998400000 {
> + opp-hz = /bits/ 64 <998400000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1708800000 {
> + opp-hz = /bits/ 64 <1708800000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2092800000 {
> + opp-hz = /bits/ 64 <2092800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2227200000 {
> + opp-hz = /bits/ 64 <2227200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2476800000 {
> + opp-hz = /bits/ 64 <2476800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2726400000 {
> + opp-hz = /bits/ 64 <2726400000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2841600000 {
> + opp-hz = /bits/ 64 <2841600000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2956800000 {
> + opp-hz = /bits/ 64 <2956800000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-3187200000 {
> + opp-hz = /bits/ 64 <3187200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> pmu-a510 {
> compatible = "arm,cortex-a510-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> };
> };
>
> + epss_l3: interconnect@17d90000 {
> + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> + reg = <0 0x17d90000 0 0x1000>;
> +
> + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@17d91000 {
> compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> reg = <0 0x17d91000 0 0x1000>,
>
> --
> 2.52.0
>
>
^ permalink raw reply
* Re: [PATCH v4 3/4] thermal/qcom/lmh: support SDM670 and its CPU clusters
From: Dmitry Baryshkov @ 2026-03-30 14:04 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Richard Acayan, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Amit Kucheria, Thara Gopinath, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-pm, devicetree
In-Reply-To: <1fcecede-16f0-4ce1-b76c-32f569cb5e41@oss.qualcomm.com>
On Mon, Mar 30, 2026 at 03:50:12PM +0200, Konrad Dybcio wrote:
> On 3/30/26 12:59 PM, Dmitry Baryshkov wrote:
> > On Mon, Mar 30, 2026 at 12:32:29PM +0200, Konrad Dybcio wrote:
> >> On 3/29/26 12:44 PM, Dmitry Baryshkov wrote:
> >>> On Fri, Mar 27, 2026 at 09:40:40PM -0400, Richard Acayan wrote:
> >>>> The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but
> >>>> some SoCs divide the CPUs into different sizes of clusters. In SDM670,
> >>>> the first 6 CPUs are in the little cluster and the next 2 are in the big
> >>>> cluster. Define the clusters in the match data and define the different
> >>>> cluster configuration for SDM670.
> >>>>
> >>>> Currently, this only supports 8 CPUs and tolerates linking to any CPU in
> >>>> the cluster.
> >>>>
> >>>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> >>>> ---
> >>>> drivers/thermal/qcom/lmh.c | 69 +++++++++++++++++++++++++++++++-------
> >>>> 1 file changed, 56 insertions(+), 13 deletions(-)
> >>>>
> >>>> +static const struct lmh_soc_data sdm670_lmh_data = {
> >>>> + .enable_algos = true,
> >>>> + .node_ids = {
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + },
> >>>> +};
> >>>> +
> >>>> +static const struct lmh_soc_data sdm845_lmh_data = {
> >>>> + .enable_algos = true,
> >>>> + .node_ids = {
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + },
> >>>> +};
> >>>
> >>> These tables made me wonder, can we determine this information from the
> >>> DT? For example, by reading the qcom,freq-domain property. But...
> >>>
> >>>> +
> >>>> +static const struct lmh_soc_data sm8150_lmh_data = {
> >>>> + .enable_algos = false,
> >>>> + .node_ids = {
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER0_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + LMH_CLUSTER1_NODE_ID,
> >>>> + },
> >>>> +};
> >>>
> >>> ... this might be problematic, unless this entry is broken. On SM8150 we
> >>> have three freq domains, but up to now we were programming two clustern
> >>> nodes. Of course it is possible to define that node_id is 0 for freq
> >>> domain 0 and 1 for domains 1 and 2.
> >>
> >> The third cluster situation on 8150 is not super good - we e.g. only have
> >> a single LMH irq that's shared between the big and prime cores. That
> >> was fixed with later SoCs (which is why it's not wired up in the DT today)
> >
> > Thanks!
> >
> > Anyway, from your point of view, would it be better to define mappings
> > in the driver (like it's done with this patch) or parse the DT?
>
> Well, we can spend a lot of time trying to be smart about it and handle
> the odd edge case, or add a simple comparison!
:-)
Then let's go with your suggestion of 'first core from second cluster'.
--
With best wishes
Dmitry
^ permalink raw reply
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