From: Xiubo Li <Li.Xiubo@freescale.com>
To: r65073@freescale.com, thierry.reding@gmail.com,
s.hauer@pengutronix.de, galak@codeaurora.org,
grant.likely@linaro.org, matt.porter@linaro.org,
tomasz.figa@gmail.com, swarren@wwwdotorg.org,
mark.rutland@arm.com
Cc: linux@arm.linux.org.uk, rob@landley.net, ian.campbell@citrix.com,
pawel.moll@arm.com, rob.herring@calxeda.com,
linux-pwm@vger.kernel.org, linux-doc@vger.kernel.org
Subject: [RFCv2 endianess 0/4] Add Freescale FTM PWM driver.
Date: Fri, 6 Dec 2013 13:52:10 +0800 [thread overview]
Message-ID: <1386309134-1822-1-git-send-email-Li.Xiubo@freescale.com> (raw)
I'm sending the RFCv2 patch series about the FTM IP block registers
read and write endian issue, and there is no buffers or descriptors
involved.
For the FTM IP block, in Vybird VF610 Tower the LE mode is in use,
in LS-1 the BE mode is in use. And the CPU always operates in LE mode.
So now I must take care of all these two cases. In this patch series I
have implemented two functions fsl_pwm_readl() and fsl_pwm_writel() to
replace readl() and writel(). At the same time there should add one
"big-endian" property for dt node.
And this patch is based the V6 series.
next reply other threads:[~2013-12-06 6:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-06 5:52 Xiubo Li [this message]
2013-12-06 5:52 ` [RFCv2 endianess 1/4] pwm: Add Freescale FTM PWM driver support Xiubo Li
2013-12-10 5:10 ` Li.Xiubo
2013-12-10 10:19 ` Mark Rutland
2013-12-10 11:37 ` Li.Xiubo
2013-12-12 2:43 ` Li.Xiubo
2013-12-12 12:42 ` Thierry Reding
2013-12-13 9:52 ` Li.Xiubo
2013-12-06 5:52 ` [RFCv2 endianess 2/4] ARM: dts: Add Freescale FTM PWM node for VF610 Xiubo Li
2013-12-06 5:52 ` [RFCv2 endianess 3/4] ARM: dts: Enables FTM PWM device for Vybrid VF610 TOWER board Xiubo Li
2013-12-06 5:52 ` [RFCv2 endianess 4/4] Documentation: Add device tree bindings for Freescale FTM PWM Xiubo Li
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