From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85A993C4B89; Thu, 14 May 2026 14:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778769093; cv=none; b=Aikna0NqvV/qvYFwTQ3n/ymNRfW8yaK0ElYjpYfisuCYck/QpaLPHhTMMMTAOFBWuuh1R7CpLXQC6N4VGsRNrWfyEu6A+RPxZAXW0AiUO5GsIu4l18RWZN0ZpLsqrd8haFT4siTDM82GCkWDGlp6XJ1aBiR1SRQEnhBFv9VItho= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778769093; c=relaxed/simple; bh=6iGfJZhncc8TZYCUGnqm+IpTKIkhFAcFKCIJIf6eUSQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Ach0kzZsaNSVWQ3FSZx0em+0CJHOaIJnO+jDKV3nzhniI8mau4ZAy5m1LpisJTFuMXXru5d4JboQ3n5iLNSCpAkXg6IwldqkqPeFIrvfaTUbO+6bcsW1EJYCGpY70867m6EaWGMFAO8+bu2Tq8vlGcfTPYI6oX81MDseAmpDkO8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BkDt38PE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BkDt38PE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C43CCC2BCB3; Thu, 14 May 2026 14:31:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778769093; bh=6iGfJZhncc8TZYCUGnqm+IpTKIkhFAcFKCIJIf6eUSQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=BkDt38PEb9XlTwH7zQZH6xmvM/K8ws918v/NQNjjIfW4RE4Z1lfJPmGTlY7lNb2Dw kjVJqtdvonYl5imzBcDzZAvVyr+/5/sp/gM/1SdF262ZtnWAYWf3YfqbgAoqEOHnnR ntXd5rGMT5K0GoF9whvlyKxGd+aNm4HGdMANdWj9G4m6z3KIsW7WjBVCjrKXqNctNg zv8WxNAtO+FtSz34keNchpmFILXSJLSf5qbQAxV3qjU8v//ESdHe68TiCOlNzhNtz+ DwR799y4GN7g/Z3+NH4IN5cNb23ElQEdg9Krlq6sl0Bh5z4JpWclM/ORijPtRiQ/DK jnezgCT3g80Zw== Message-ID: <1d1a21a6-720d-4e8d-9798-27f8cc593403@kernel.org> Date: Thu, 14 May 2026 16:31:27 +0200 Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/2] dt-bindings: pwm: dwc: add optional reset To: Xuyang Dong Cc: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ben-linux@fluff.org, ben.dooks@codethink.co.uk, p.zabel@pengutronix.de, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, xuxiang@eswincomputing.com, wangguosheng@eswincomputing.com, pinkesh.vaghela@einfochips.com References: <20260424094529.1691-1-dongxuyang@eswincomputing.com> <20260424095435.1721-1-dongxuyang@eswincomputing.com> <622e18f1.5bb3.19dd36d0c40.Coremail.dongxuyang@eswincomputing.com> <7bd6129a-dd37-48e8-a54c-cc149a2b84a2@kernel.org> <1ac7fae4.5c66.19dd892ec4d.Coremail.dongxuyang@eswincomputing.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 11/05/2026 09:10, Xuyang Dong wrote: >> >> On 29/04/2026 11:30, Xuyang Dong wrote: >>>>>>> >>>>>>> +allOf: >>>>>>> + - $ref: pwm.yaml# >>>>>>> + >>>>>>> + - if: >>>>>>> + properties: >>>>>>> + compatible: >>>>>>> + contains: >>>>>>> + const: eswin,eic7700-pwm >>>>>> >>>>>> Same problem as v3 which I commented. I do not understand why your new >>>>>> device has also 1 reset. >>>>>> >>>>>> Your commit msg MUST explain why 1 reset is valid. >>>>>> >>>>> >>>>> Hi Krzysztof, >>>>> >>>>> Although the PWM IP supports two clock domains, each requiring a reset,  >>>>> the EIC7700 implementation uses the same clock domain for both clock  >>>>> signals. Therefore, the eic7700-pwm only supports one reset. >>>>> >>>> >>>> If we speak about eic7700, explain why it has two resets now, according >>>> to schema, even though you say it has not. >>>> >>>> But I was speaking about dw-apb-timers-pwm, which has one reset as well! >>>> Why you are not having proper constraints? Please read writing bindings >>>> document. >>>> >>> >>> Hi Krzysztof, >>> >>> Let me clarify the reset signals. >>>   - snps,dw-apb-timers-pwm2: IP spec has 2 optional reset signals (one per >>> clock domain), SoC vendor decides whether to wire them — so maxItems: 2,  >>> optional in required. >> >> Two reset signals but what is exactly optional? Each of them? Only the >> first? Binding does not allow the first to be optional. >> > > Hi Krzysztof, > > Thank you for the review. > > For the generic snps,dw-apb-timers-pwm2 binding, both reset signals  > are now fully optional by not including resets in the required list. > > When a single optional reset signal is used, the interface bus reset  > (index 0) is used by default. > > Keep the YAML as follows: > +  resets: > +    minItems: 1 > +    items: > +      - description: Interface bus reset > +      - description: PWM timer logic reset > > Add the following description to the commit message: We speak about hardware, not binding. I asked, why your new device has only one reset. > > Whether each signal is wired on a given SoC is a board integration  > decision, so the resets property is optional for snps,dw-apb-timers-pwm2.  > When present, up to two handles may be supplied: the bus reset is always  > at index 0 and the timer reset at index 1. > >>>   - eswin,eic7700-pwm: SoC physically ties both signals to one reset — so >>> exactly 1, required. >> >> Then two would not be right and you need to restrict that. >> > > For the specific eswin,eic7700-pwm binding, the reset signal is required  > and fixed to one via conditional schema (if:then:), with maxItems: 1  > and resets added to required. And add an example for eswin,eic7700-pwm. > The changes are as follows: > > +allOf: > +  - $ref: pwm.yaml# > + > +  - if: > +      properties: > +        compatible: > +          contains: > +            const: eswin,eic7700-pwm > +    then: > +      properties: > +        resets: > +          maxItems: 1 > +      required: > +        - resets > + > > +  - | > +    pwm@50818000 { > +      compatible = "eswin,eic7700-pwm"; > +      reg = <0x50818000 0x4000>; > +      #pwm-cells = <3>; > +      clocks = <&bus>, <&timer>; > +      clock-names = "bus", "timer"; > +      resets = <&reset>; > +    }; > > Then change the binding's subject from "dt-bindings: pwm: dwc: add optional  > reset" to "dt-bindings: pwm: dwc: add eswin,eic7700-pwm compatible and resets". > > Do these changes look acceptable to you? So two resets or one reset? I am completely confused what you are replying to. Please read writing bindings document. Best regards, Krzysztof