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AJvYcCXP/YaAikWV0V/6vpiqc0q9xtTVt6gRK44IxPlLyYsO3x4ooVeE0l0hw0jozuLBrWPJ3rSlL4L3JeZS/TVGroqkPUAtE19KZi7s X-Gm-Message-State: AOJu0YyYBJDexMOcZ/0Z65hYsYxOQ29QaG7OQaxH8lPcRq1m8pq8OuVt XdIm6t60TDzb5ws8wIY29zZF6+J8iCDfTyrJASAWPjw2v4lr4UYh+VNNJb4CbJY= X-Google-Smtp-Source: AGHT+IG3y3s2abTIzMduavSusGk41h4eUyyiMJrCpnEXNNbVBBrdn+KPAsoARDJOB2DmaMtozMzthw== X-Received: by 2002:a05:600c:4da3:b0:426:6eac:8314 with SMTP id 5b1f17b1804b1-4266eac83bfmr5970605e9.1.1720444270774; Mon, 08 Jul 2024 06:11:10 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:5158:f510:c35c:9d0b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a21cb57sm163660395e9.21.2024.07.08.06.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jul 2024 06:11:10 -0700 (PDT) From: Jerome Brunet To: George Stark Cc: , , , , , , , , , , , , , , Dmitry Rokosov Subject: Re: [PATCH v3 1/2] dt-bindings: pwm: amlogic: Add new bindings for meson A1 PWM In-Reply-To: <20240702123425.584610-2-gnstark@salutedevices.com> (George Stark's message of "Tue, 2 Jul 2024 15:34:24 +0300") References: <20240702123425.584610-1-gnstark@salutedevices.com> <20240702123425.584610-2-gnstark@salutedevices.com> Date: Mon, 08 Jul 2024 15:11:09 +0200 Message-ID: <1j8qychvv6.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue 02 Jul 2024 at 15:34, George Stark wrote: > The chip has 3 dual-channel PWM modules PWM_AB, PWM_CD, PWM_EF. > > Signed-off-by: George Stark > Signed-off-by: Dmitry Rokosov > --- > .../devicetree/bindings/pwm/pwm-amlogic.yaml | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > index 1d71d4f8f328..e021cf59421a 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > @@ -37,6 +37,10 @@ properties: > - enum: > - amlogic,meson8-pwm-v2 > - amlogic,meson-s4-pwm > + - items: > + - enum: > + - amlogic,meson-a1-pwm > + - const: amlogic,meson-s4-pwm > - items: > - enum: > - amlogic,meson8b-pwm-v2 > @@ -56,6 +60,9 @@ properties: > minItems: 1 > maxItems: 2 > > + power-domains: > + maxItems: 1 > + The change is not only introducing a1 compatibility but also allowing a power-domain for the other SoC, even if optional. If that is intended, it should be stated in the description and probably a separate change. > "#pwm-cells": > const: 3 > > @@ -136,6 +143,16 @@ allOf: > required: > - clocks > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - amlogic,meson-a1-pwm > + then: > + required: > + - power-domains > + > additionalProperties: false > > examples: -- Jerome