[PATCH 0/3] FTM PWM adds regmap and endianness support.

[PATCH 0/3] FTM PWM adds regmap and endianness support.

[Xiubo Li]

Xiubo Li (3):
  pwm: ftm-pwm: Clean up the code.
  pwm: ftm-pwm: Convert to direct regmap API usage.
  pwm: ftm-pwm: Add big-endian support

 drivers/pwm/pwm-fsl-ftm.c | 96 ++++++++++++++++++++++++++---------------------
 1 file changed, 53 insertions(+), 43 deletions(-)

-- 
1.8.4

[PATCH 1/3] pwm: ftm-pwm: Clean up the code.

[Xiubo Li]

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
 drivers/pwm/pwm-fsl-ftm.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 420169e..4a4ad58 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -21,11 +21,10 @@
 #include <linux/slab.h>
 
 #define FTM_SC		0x00
-#define FTM_SC_CLK_MASK	0x3
-#define FTM_SC_CLK_SHIFT	3
-#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_SHIFT)
+#define FTM_SC_CLK_MASK_SHIFT	3
+#define FTM_SC_CLK_MASK	(3 << FTM_SC_CLK_MASK_SHIFT)
+#define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
 #define FTM_SC_PS_MASK	0x7
-#define FTM_SC_PS_SHIFT	0
 
 #define FTM_CNT		0x04
 #define FTM_MOD		0x08
@@ -258,7 +257,7 @@ static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		}
 
 		val = readl(fpc->base + FTM_SC);
-		val &= ~(FTM_SC_PS_MASK << FTM_SC_PS_SHIFT);
+		val &= ~FTM_SC_PS_MASK;
 		val |= fpc->clk_ps;
 		writel(val, fpc->base + FTM_SC);
 		writel(period - 1, fpc->base + FTM_MOD);
@@ -305,7 +304,7 @@ static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
 
 	/* select counter clock source */
 	val = readl(fpc->base + FTM_SC);
-	val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT);
+	val &= ~FTM_SC_CLK_MASK;
 	val |= FTM_SC_CLK(fpc->cnt_select);
 	writel(val, fpc->base + FTM_SC);
 
@@ -357,7 +356,7 @@ static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)
 
 	/* no users left, disable PWM counter clock */
 	val = readl(fpc->base + FTM_SC);
-	val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT);
+	val &= ~FTM_SC_CLK_MASK;
 	writel(val, fpc->base + FTM_SC);
 
 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
-- 
1.8.4

Re: [PATCH 1/3] pwm: ftm-pwm: Clean up the code.

[Thierry Reding]

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On Fri, Mar 21, 2014 at 12:53:08PM +0800, Xiubo Li wrote:
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
>  drivers/pwm/pwm-fsl-ftm.c | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)

The patch description here could explain that this is in preparation for
the conversion to regmap (which I assume it is).

Thierry

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RE: [PATCH 1/3] pwm: ftm-pwm: Clean up the code.

[Li.Xiubo]

> > Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> > ---
> >  drivers/pwm/pwm-fsl-ftm.c | 13 ++++++-------
> >  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> The patch description here could explain that this is in preparation for
> the conversion to regmap (which I assume it is).
>

Please see the next version, I`ll explain it.

Thanks,

BRs
Xiubo

[PATCH 2/3] pwm: ftm-pwm: Convert to direct regmap API usage.

[Xiubo Li]

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
 drivers/pwm/pwm-fsl-ftm.c | 83 +++++++++++++++++++++++++----------------------
 1 file changed, 44 insertions(+), 39 deletions(-)

diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 4a4ad58..5d999c1 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -18,6 +18,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/pwm.h>
+#include <linux/regmap.h>
 #include <linux/slab.h>
 
 #define FTM_SC		0x00
@@ -82,7 +83,7 @@ struct fsl_pwm_chip {
 	unsigned int cnt_select;
 	unsigned int clk_ps;
 
-	void __iomem *base;
+	struct regmap *regmap;
 
 	int period_ns;
 
@@ -218,10 +219,11 @@ static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
 					    unsigned long period_ns,
 					    unsigned long duty_ns)
 {
-	unsigned long long val, duty;
+	unsigned long long duty;
+	u32 val;
 
-	val = readl(fpc->base + FTM_MOD);
-	duty = duty_ns * (val + 1);
+	regmap_read(fpc->regmap, FTM_MOD, &val);
+	duty = (unsigned long long)duty_ns * (val + 1);
 	do_div(duty, period_ns);
 
 	return (unsigned long)duty;
@@ -231,7 +233,7 @@ static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			  int duty_ns, int period_ns)
 {
 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
-	u32 val, period, duty;
+	u32 period, duty;
 
 	mutex_lock(&fpc->lock);
 
@@ -256,11 +258,9 @@ static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			return -EINVAL;
 		}
 
-		val = readl(fpc->base + FTM_SC);
-		val &= ~FTM_SC_PS_MASK;
-		val |= fpc->clk_ps;
-		writel(val, fpc->base + FTM_SC);
-		writel(period - 1, fpc->base + FTM_MOD);
+		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
+				   fpc->clk_ps);
+		regmap_write(fpc->regmap, FTM_MOD, period - 1);
 
 		fpc->period_ns = period_ns;
 	}
@@ -269,8 +269,9 @@ static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);
 
-	writel(FTM_CSC_MSB | FTM_CSC_ELSB, fpc->base + FTM_CSC(pwm->hwpwm));
-	writel(duty, fpc->base + FTM_CV(pwm->hwpwm));
+	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
+		     FTM_CSC_MSB | FTM_CSC_ELSB);
+	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
 
 	return 0;
 }
@@ -282,31 +283,28 @@ static int fsl_pwm_set_polarity(struct pwm_chip *chip,
 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
 	u32 val;
 
-	val = readl(fpc->base + FTM_POL);
+	regmap_read(fpc->regmap, FTM_POL, &val);
 
 	if (polarity == PWM_POLARITY_INVERSED)
 		val |= BIT(pwm->hwpwm);
 	else
 		val &= ~BIT(pwm->hwpwm);
 
-	writel(val, fpc->base + FTM_POL);
+	regmap_write(fpc->regmap, FTM_POL, val);
 
 	return 0;
 }
 
 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
 {
-	u32 val;
 	int ret;
 
 	if (fpc->use_count != 0)
 		return 0;
 
 	/* select counter clock source */
-	val = readl(fpc->base + FTM_SC);
-	val &= ~FTM_SC_CLK_MASK;
-	val |= FTM_SC_CLK(fpc->cnt_select);
-	writel(val, fpc->base + FTM_SC);
+	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
+			   FTM_SC_CLK(fpc->cnt_select));
 
 	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
 	if (ret)
@@ -326,13 +324,10 @@ static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
 static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
-	u32 val;
 	int ret;
 
 	mutex_lock(&fpc->lock);
-	val = readl(fpc->base + FTM_OUTMASK);
-	val &= ~BIT(pwm->hwpwm);
-	writel(val, fpc->base + FTM_OUTMASK);
+	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);
 
 	ret = fsl_counter_clock_enable(fpc);
 	mutex_unlock(&fpc->lock);
@@ -342,8 +337,6 @@ static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 
 static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)
 {
-	u32 val;
-
 	/*
 	 * already disabled, do nothing
 	 */
@@ -355,9 +348,7 @@ static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)
 		return;
 
 	/* no users left, disable PWM counter clock */
-	val = readl(fpc->base + FTM_SC);
-	val &= ~FTM_SC_CLK_MASK;
-	writel(val, fpc->base + FTM_SC);
+	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0);
 
 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
 	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
@@ -369,14 +360,12 @@ static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	u32 val;
 
 	mutex_lock(&fpc->lock);
-	val = readl(fpc->base + FTM_OUTMASK);
-	val |= BIT(pwm->hwpwm);
-	writel(val, fpc->base + FTM_OUTMASK);
+	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
+			   BIT(pwm->hwpwm));
 
 	fsl_counter_clock_disable(fpc);
 
-	val = readl(fpc->base + FTM_OUTMASK);
-
+	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
 	if ((val & 0xFF) == 0xFF)
 		fpc->period_ns = 0;
 
@@ -401,19 +390,28 @@ static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
 	if (ret)
 		return ret;
 
-	writel(0x00, fpc->base + FTM_CNTIN);
-	writel(0x00, fpc->base + FTM_OUTINIT);
-	writel(0xFF, fpc->base + FTM_OUTMASK);
+	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
+	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
+	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
 
 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
 
 	return 0;
 }
 
+static struct regmap_config fsl_pwm_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+
+	.max_register = FTM_PWMLOAD,
+};
+
 static int fsl_pwm_probe(struct platform_device *pdev)
 {
 	struct fsl_pwm_chip *fpc;
 	struct resource *res;
+	void __iomem *base;
 	int ret;
 
 	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
@@ -425,9 +423,16 @@ static int fsl_pwm_probe(struct platform_device *pdev)
 	fpc->chip.dev = &pdev->dev;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	fpc->base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(fpc->base))
-		return PTR_ERR(fpc->base);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
+						&fsl_pwm_regmap_config);
+	if (IS_ERR(fpc->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(fpc->regmap);
+	}
 
 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
-- 
1.8.4

Re: [PATCH 2/3] pwm: ftm-pwm: Convert to direct regmap API usage.

[Thierry Reding]

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On Fri, Mar 21, 2014 at 12:53:09PM +0800, Xiubo Li wrote:
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
>  drivers/pwm/pwm-fsl-ftm.c | 83 +++++++++++++++++++++++++----------------------
>  1 file changed, 44 insertions(+), 39 deletions(-)

This could explain the advantages of converting to regmap. Looking at
this diffstat above, it's not immediately obvious that there's an
advantage because you end up adding 5 lines.

Again I'm guessing this is in preparation to add endianess support, and
it will be really easy to add that using regmap, so the gains will only
become obvious later on.

That's the kind of thing I'd like to see in the patch description. It
tells me why this patch makes sense.

Thierry

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RE: [PATCH 2/3] pwm: ftm-pwm: Convert to direct regmap API usage.

[Li.Xiubo]

> >  drivers/pwm/pwm-fsl-ftm.c | 83 +++++++++++++++++++++++++----------------------
> >  1 file changed, 44 insertions(+), 39 deletions(-)
> 
> This could explain the advantages of converting to regmap. Looking at
> this diffstat above, it's not immediately obvious that there's an
> advantage because you end up adding 5 lines.
> 
> Again I'm guessing this is in preparation to add endianess support, and
> it will be really easy to add that using regmap, so the gains will only
> become obvious later on.
> 
> That's the kind of thing I'd like to see in the patch description. It
> tells me why this patch makes sense.
> 

Yes, That`s why converting to use the regmap.

I`ll update this as you have mentioned.

Thanks,
BRs
Xiubo

[PATCH 3/3] pwm: ftm-pwm: Add big-endian support

[Xiubo Li]

Now for the following scenarios:

     SoC     |  CPU   | FTM-PWM | 'big-endian' property is needed?
-------------|--------|---------|---------------------------------
    Vybird   |  LE    |   LE    |     No
     LS1     |  LE    |   BE    |     Yes
     LS2     |  LE    |   LE    |     No

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
 drivers/pwm/pwm-fsl-ftm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 5d999c1..9a82741 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -409,6 +409,7 @@ static struct regmap_config fsl_pwm_regmap_config = {
 
 static int fsl_pwm_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	struct fsl_pwm_chip *fpc;
 	struct resource *res;
 	void __iomem *base;
@@ -422,6 +423,11 @@ static int fsl_pwm_probe(struct platform_device *pdev)
 
 	fpc->chip.dev = &pdev->dev;
 
+	if (of_property_read_bool(np, "big-endian"))
+		fsl_pwm_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
+	else
+		fsl_pwm_regmap_config.val_format_endian = REGMAP_ENDIAN_NATIVE;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(base))
-- 
1.8.4

Re: [PATCH 3/3] pwm: ftm-pwm: Add big-endian support

[Thierry Reding]

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On Fri, Mar 21, 2014 at 12:53:10PM +0800, Xiubo Li wrote:
> Now for the following scenarios:
> 
>      SoC     |  CPU   | FTM-PWM | 'big-endian' property is needed?
> -------------|--------|---------|---------------------------------
>     Vybird   |  LE    |   LE    |     No
>      LS1     |  LE    |   BE    |     Yes
>      LS2     |  LE    |   LE    |     No
> 
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
>  drivers/pwm/pwm-fsl-ftm.c | 6 ++++++
>  1 file changed, 6 insertions(+)

And this should probably describe in text what happens. The table may
look good, but you don't give a real description of what the change
does.

Oh, and doesn't this change need to update the device tree binding since
you now have an additional property?

Thierry

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RE: [PATCH 3/3] pwm: ftm-pwm: Add big-endian support

[Li.Xiubo]

> > Now for the following scenarios:
> >
> >      SoC     |  CPU   | FTM-PWM | 'big-endian' property is needed?
> > -------------|--------|---------|---------------------------------
> >     Vybird   |  LE    |   LE    |     No
> >     LS1     |  LE    |   BE    |     Yes
> >     LS2     |  LE    |   LE    |     No
> >
> > Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> > ---
> >  drivers/pwm/pwm-fsl-ftm.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> 
> And this should probably describe in text what happens. The table may
> look good, but you don't give a real description of what the change
> does.
> 

I will follow your advice.


> Oh, and doesn't this change need to update the device tree binding since
> you now have an additional property?
>

Yes, you are right. I just forgot it.

I will add update it.

Thanks very much.

BRs
XIubo

RE: [PATCH 0/3] FTM PWM adds regmap and endianness support.

[Li.Xiubo]

Therry,

Ping :)



> -----Original Message-----
> From: Xiubo Li [mailto:Li.Xiubo@freescale.com]
> Sent: Friday, March 21, 2014 12:53 PM
> To: thierry.reding@gmail.com; linux-pwm@vger.kernel.org
> Cc: broonie@kernel.org; swarren@nvidia.com; linux-kernel@vger.kernel.org;
> Xiubo Li-B47053
> Subject: [PATCH 0/3] FTM PWM adds regmap and endianness support.
> 
> 
> Xiubo Li (3):
>   pwm: ftm-pwm: Clean up the code.
>   pwm: ftm-pwm: Convert to direct regmap API usage.
>   pwm: ftm-pwm: Add big-endian support
> 
>  drivers/pwm/pwm-fsl-ftm.c | 96 ++++++++++++++++++++++++++--------------------
> -
>  1 file changed, 53 insertions(+), 43 deletions(-)
> 
> --
> 1.8.4
> 

Re: [PATCH 0/3] FTM PWM adds regmap and endianness support.

[Thierry Reding]

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On Fri, Mar 21, 2014 at 12:53:07PM +0800, Xiubo Li wrote:
> 
> Xiubo Li (3):
>   pwm: ftm-pwm: Clean up the code.
>   pwm: ftm-pwm: Convert to direct regmap API usage.
>   pwm: ftm-pwm: Add big-endian support
> 
>  drivers/pwm/pwm-fsl-ftm.c | 96 ++++++++++++++++++++++++++---------------------
>  1 file changed, 53 insertions(+), 43 deletions(-)

This leaves me with only very vague idea of why this is necessary and
why it should be merged.

Please describe in more detail (in both the cover-letter and each
individual patch) why you want me to apply these patches.

Thierry

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RE: [PATCH 0/3] FTM PWM adds regmap and endianness support.

[Li.Xiubo]

> > Xiubo Li (3):
> >   pwm: ftm-pwm: Clean up the code.
> >   pwm: ftm-pwm: Convert to direct regmap API usage.
> >   pwm: ftm-pwm: Add big-endian support
> >
> >  drivers/pwm/pwm-fsl-ftm.c | 96 ++++++++++++++++++++++++++---------------------
> >  1 file changed, 53 insertions(+), 43 deletions(-)
>
> This leaves me with only very vague idea of why this is necessary and
> why it should be merged.
>
> Please describe in more detail (in both the cover-letter and each
> individual patch) why you want me to apply these patches.
>

Thanks very much for your reply.

Should I resend this patch series? If so, I will add some thing like the following:

The FTM PWM driver will be used in our Vybrid, LS1 and LS2+ SoCs, and on Vybrid
and LS2 SoCs, the FTM devices are in LE mode, while on LS1 SoCs it in BE mode.

So this patch series add endianness support based on the regmap core, which has
already support the rich endiannesses for the same device.

Thanks,

BRs
Xiubo

Re: [PATCH 0/3] FTM PWM adds regmap and endianness support.

[Thierry Reding]

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On Mon, Apr 28, 2014 at 02:26:57PM +0000, Li.Xiubo@freescale.com wrote:
> 
> 
> 
> > > Xiubo Li (3):
> > >   pwm: ftm-pwm: Clean up the code.
> > >   pwm: ftm-pwm: Convert to direct regmap API usage.
> > >   pwm: ftm-pwm: Add big-endian support
> > >
> > >  drivers/pwm/pwm-fsl-ftm.c | 96 ++++++++++++++++++++++++++---------------------
> > >  1 file changed, 53 insertions(+), 43 deletions(-)
> >
> > This leaves me with only very vague idea of why this is necessary and
> > why it should be merged.
> >
> > Please describe in more detail (in both the cover-letter and each
> > individual patch) why you want me to apply these patches.
> >
> 
> Thanks very much for your reply.
> 
> Should I resend this patch series? If so, I will add some thing like the following:
> 
> The FTM PWM driver will be used in our Vybrid, LS1 and LS2+ SoCs, and on Vybrid
> and LS2 SoCs, the FTM devices are in LE mode, while on LS1 SoCs it in BE mode.
> 
> So this patch series add endianness support based on the regmap core, which has
> already support the rich endiannesses for the same device.

Yes, please resend with that description added where appropriate. I'd
like to see something like that in the cover letter and, more
importantly, in the individual patches.

Thierry

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RE: [PATCH 0/3] FTM PWM adds regmap and endianness support.

[Li.Xiubo]

> > Should I resend this patch series? If so, I will add some thing like the following:
> >
> > The FTM PWM driver will be used in our Vybrid, LS1 and LS2+ SoCs, and on Vybrid
> > and LS2 SoCs, the FTM devices are in LE mode, while on LS1 SoCs it in BE mode.
> >
> > So this patch series add endianness support based on the regmap core, which has
> > already support the rich endiannesses for the same device.
>
> Yes, please resend with that description added where appropriate. I'd
> like to see something like that in the cover letter and, more
> importantly, in the individual patches.
>

Okay, Please see the next version.

Thanks,

BRs
Xiubo