* [PATCHv3 0/7] Add Allwinner SoCs PWM support
@ 2014-04-28 16:17 Alexandre Belloni
2014-04-28 16:17 ` [PATCHv3 1/7] pwm: Add Allwinner SoC support Alexandre Belloni
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw)
To: Thierry Reding, Maxime Ripard
Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel,
Alexandre Belloni
Hi,
This patch set adds support for the PWM controller found on the Allwinner SoCs.
The first patch adds the driver itself.
The second patch adds the DT binding documentation
The third patch adds the bindings to the sun7i-a20 DTS include.
And finally, the la patch adds support for the PWMs to the cubietruck which is
the board I used to test.
Changes in v3:
- added COMPILE_TEST as a dependency
- fixed indentation
- modified the macros like suggested by Maxime
Changes in v2:
- changed the compatible string
- documented the clocks property
- Added support in the A10 dtsi
- split the patch adding pinctrl
- a few cosmetic changes (removed empty lines, PWM_PRESCAL_MASK, ...)
- fixed the period register calculation (the period is actually N + 1 cycles)
so write prd - 1
- properly locked accesses to PWM_CTRL_REG with a mutex
Alexandre Belloni (7):
pwm: Add Allwinner SoC support
pwm: sunxi: document OF bindings
ARM: sun4i: dt: add pinmux configuration for the PWM
ARM: sun4i: dt: add PWM support
ARM: sun7i: dt: add pinmux configuration for the PWM
ARM: sun7i: dt: add PWM support
ARM: sunxi: dt: add PWM support for the cubietruck
.../devicetree/bindings/pwm/pwm-sunxi.txt | 20 ++
arch/arm/boot/dts/sun4i-a10.dtsi | 22 ++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 +
arch/arm/boot/dts/sun7i-a20.dtsi | 22 ++
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sunxi.c | 345 +++++++++++++++++++++
7 files changed, 425 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sunxi.txt
create mode 100644 drivers/pwm/pwm-sunxi.c
--
1.9.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCHv3 1/7] pwm: Add Allwinner SoC support 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 19:10 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 2/7] pwm: sunxi: document OF bindings Alexandre Belloni ` (5 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni This adds a generic PWM framework driver for the PWM controller found on Allwinner SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sunxi.c | 345 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 drivers/pwm/pwm-sunxi.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 5b34ff29ea38..178b017be827 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -217,6 +217,15 @@ config PWM_SPEAR To compile this driver as a module, choose M here: the module will be called pwm-spear. +config PWM_SUNXI + tristate "Allwinner PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + help + Generic PWM framework driver for Allwinner SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sunxi. + config PWM_TEGRA tristate "NVIDIA Tegra PWM support" depends on ARCH_TEGRA diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index e57d2c38a794..39997ea2e276 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_PXA) += pwm-pxa.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o +obj-$(CONFIG_PWM_SUNXI) += pwm-sunxi.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o diff --git a/drivers/pwm/pwm-sunxi.c b/drivers/pwm/pwm-sunxi.c new file mode 100644 index 000000000000..0f2d65e8976b --- /dev/null +++ b/drivers/pwm/pwm-sunxi.c @@ -0,0 +1,345 @@ +/* + * Driver for Allwinner Pulse Width Modulation Controller + * + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> + * + * Licensed under GPLv2. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/slab.h> + +#define PWM_CTRL_REG 0x0 + +#define PWM_CH_PRD_BASE 0x4 +#define PWM_CH_PRD_OFF 0x4 +#define PWM_CH_PRD(x) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFF * (x)) + +#define PWMCH_OFFSET 15 +#define PWM_PRESCAL_MASK GENMASK(3,0) +#define PWM_PRESCAL_OFF 0 +#define PWM_EN BIT(4) +#define PWM_ACT_STATE BIT(5) +#define PWM_CLK_GATING BIT(6) +#define PWM_MODE BIT(7) +#define PWM_PULSE BIT(8) +#define PWM_BYPASS BIT(9) + +#define PWM_RDY_BASE 28 +#define PWM_RDY_OFF 1 +#define PWM_RDY(x) BIT(PWM_RDY_BASE + PWM_RDY_OFF * (x)) + +#define PWM_PRD_ACT_MASK 0xFF +#define PWM_PRD(x) ((x - 1) << 16) +#define PWM_PRD_MASK 0xFF + +#define BIT_CH(bit, chan) (bit << (chan * PWMCH_OFFSET)) + +u32 prescal_table[] = { 120, 180, 240, 360, 480, 0, 0, 0, + 12000, 24000, 36000, 48000, 72000, + 0, 0, 1 }; + +struct sunxi_pwm_data { + bool has_rdy; +}; + +struct sunxi_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + struct mutex ctrl_lock; + const struct sunxi_pwm_data *data; +}; + +#define to_sunxi_pwm_chip(chip) container_of(chip, struct sunxi_pwm_chip, chip) + +static inline u32 sunxi_pwm_readl(struct sunxi_pwm_chip *chip, + unsigned long offset) +{ + return readl_relaxed(chip->base + offset); +} + +static inline void sunxi_pwm_writel(struct sunxi_pwm_chip *chip, + unsigned long offset, unsigned long val) +{ + writel_relaxed(val, chip->base + offset); +} + +static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip); + u32 clk_rate, prd, dty; + u64 div; + u32 val, clk_gate; + int i, ret; + + clk_rate = clk_get_rate(sunxi_pwm->clk); + + /* First, test without any divider */ + i = PWM_PRESCAL_MASK; + div = clk_rate * period_ns; + do_div(div, 1000000000); + if (div > PWM_PRD_MASK) { + /* Then go up from the first divider */ + for (i = 0; i < PWM_PRESCAL_MASK; i++) { + if (!prescal_table[i]) + continue; + div = clk_rate / prescal_table[i]; + div = div * period_ns; + do_div(div, 1000000000); + if (div <= PWM_PRD_MASK) + break; + } + } + + if (div > PWM_PRD_MASK) { + dev_err(chip->dev, "prescaler exceeds the maximum value\n"); + return -EINVAL; + } + + prd = div; + div *= duty_ns; + do_div(div, period_ns); + dty = div; + + ret = clk_enable(sunxi_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + mutex_lock(&sunxi_pwm->ctrl_lock); + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + + if (sunxi_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) { + mutex_unlock(&sunxi_pwm->ctrl_lock); + clk_disable(sunxi_pwm->clk); + return -EBUSY; + } + + clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (clk_gate) { + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + } + + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); + val |= i; + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + + sunxi_pwm_writel(sunxi_pwm, PWM_CH_PRD(pwm->hwpwm), dty | PWM_PRD(prd)); + + if (clk_gate) { + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + val |= clk_gate; + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + } + + mutex_unlock(&sunxi_pwm->ctrl_lock); + clk_disable(sunxi_pwm->clk); + + return 0; +} + +static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_enable(sunxi_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + mutex_lock(&sunxi_pwm->ctrl_lock); + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + + if (polarity != PWM_POLARITY_NORMAL) + val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); + else + val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); + + + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + + mutex_unlock(&sunxi_pwm->ctrl_lock); + clk_disable(sunxi_pwm->clk); + + return 0; +} + +static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_enable(sunxi_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + mutex_lock(&sunxi_pwm->ctrl_lock); + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + val |= BIT_CH(PWM_EN, pwm->hwpwm); + val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + mutex_unlock(&sunxi_pwm->ctrl_lock); + + return 0; +} + +static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip); + u32 val; + + mutex_lock(&sunxi_pwm->ctrl_lock); + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG); + val &= ~BIT_CH(PWM_EN, pwm->hwpwm); + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val); + mutex_unlock(&sunxi_pwm->ctrl_lock); + + clk_disable(sunxi_pwm->clk); +} + +static const struct pwm_ops sunxi_pwm_ops = { + .config = sunxi_pwm_config, + .set_polarity = sunxi_pwm_set_polarity, + .enable = sunxi_pwm_enable, + .disable = sunxi_pwm_disable, + .owner = THIS_MODULE, +}; + +static const struct sunxi_pwm_data sunxi_pwm_data_a10 = { + .has_rdy = false, +}; + +static const struct sunxi_pwm_data sunxi_pwm_data_a20 = { + .has_rdy = true, +}; + +static const struct of_device_id sunxi_pwm_dt_ids[] = { + { + .compatible = "allwinner,sun4i-a10-pwm", + .data = &sunxi_pwm_data_a10, + }, { + .compatible = "allwinner,sun7i-a20-pwm", + .data = &sunxi_pwm_data_a20, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, sunxi_pwm_dt_ids); + +static int sunxi_pwm_probe(struct platform_device *pdev) +{ + struct sunxi_pwm_chip *sunxi_pwm; + struct resource *res; + int ret; + + const struct of_device_id *match; + + match = of_match_device(sunxi_pwm_dt_ids, &pdev->dev); + if (!match || !match->data) + return -ENODEV; + + sunxi_pwm = devm_kzalloc(&pdev->dev, sizeof(*sunxi_pwm), GFP_KERNEL); + if (!sunxi_pwm) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sunxi_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sunxi_pwm->base)) + return PTR_ERR(sunxi_pwm->base); + + sunxi_pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sunxi_pwm->clk)) + return PTR_ERR(sunxi_pwm->clk); + + ret = clk_prepare(sunxi_pwm->clk); + if (ret) { + dev_err(&pdev->dev, "failed to prepare PWM clock\n"); + return ret; + } + + sunxi_pwm->chip.dev = &pdev->dev; + sunxi_pwm->chip.ops = &sunxi_pwm_ops; + + sunxi_pwm->chip.base = -1; + sunxi_pwm->chip.npwm = 2; + sunxi_pwm->chip.can_sleep = true; + sunxi_pwm->chip.of_xlate = of_pwm_xlate_with_flags; + sunxi_pwm->chip.of_pwm_n_cells = 3; + sunxi_pwm->data = match->data; + + mutex_init(&sunxi_pwm->ctrl_lock); + + ret = clk_enable(sunxi_pwm->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable PWM clock\n"); + goto error; + } + + /* By default, the polarity is inversed, set it to normal */ + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, + BIT_CH(PWM_ACT_STATE, 0) | + BIT_CH(PWM_ACT_STATE, 1)); + clk_disable(sunxi_pwm->clk); + + ret = pwmchip_add(&sunxi_pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); + goto error; + } + + platform_set_drvdata(pdev, sunxi_pwm); + + return ret; + +error: + mutex_destroy(&sunxi_pwm->ctrl_lock); + clk_unprepare(sunxi_pwm->clk); + return ret; +} + +static int sunxi_pwm_remove(struct platform_device *pdev) +{ + struct sunxi_pwm_chip *sunxi_pwm = platform_get_drvdata(pdev); + + mutex_destroy(&sunxi_pwm->ctrl_lock); + clk_unprepare(sunxi_pwm->clk); + + return pwmchip_remove(&sunxi_pwm->chip); +} + +static struct platform_driver sunxi_pwm_driver = { + .driver = { + .name = "sunxi-pwm", + .of_match_table = sunxi_pwm_dt_ids, + }, + .probe = sunxi_pwm_probe, + .remove = sunxi_pwm_remove, +}; +module_platform_driver(sunxi_pwm_driver); + +MODULE_ALIAS("platform:sunxi-pwm"); +MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); +MODULE_DESCRIPTION("Allwinner PWM driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCHv3 1/7] pwm: Add Allwinner SoC support 2014-04-28 16:17 ` [PATCHv3 1/7] pwm: Add Allwinner SoC support Alexandre Belloni @ 2014-04-28 19:10 ` Maxime Ripard 0 siblings, 0 replies; 13+ messages in thread From: Maxime Ripard @ 2014-04-28 19:10 UTC (permalink / raw) To: Alexandre Belloni Cc: Thierry Reding, linux-pwm, linux-doc, linux-arm-kernel, linux-kernel [-- Attachment #1: Type: text/plain, Size: 4328 bytes --] Hi, On Mon, Apr 28, 2014 at 06:17:08PM +0200, Alexandre Belloni wrote: > This adds a generic PWM framework driver for the PWM controller > found on Allwinner SoCs. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > drivers/pwm/Kconfig | 9 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-sunxi.c | 345 ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 355 insertions(+) > create mode 100644 drivers/pwm/pwm-sunxi.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 5b34ff29ea38..178b017be827 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -217,6 +217,15 @@ config PWM_SPEAR > To compile this driver as a module, choose M here: the module > will be called pwm-spear. > > +config PWM_SUNXI > + tristate "Allwinner PWM support" > + depends on ARCH_SUNXI || COMPILE_TEST > + help > + Generic PWM framework driver for Allwinner SoCs. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-sunxi. > + > config PWM_TEGRA > tristate "NVIDIA Tegra PWM support" > depends on ARCH_TEGRA > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index e57d2c38a794..39997ea2e276 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_PXA) += pwm-pxa.o > obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o > obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o > obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o > +obj-$(CONFIG_PWM_SUNXI) += pwm-sunxi.o > obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o > obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o > obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o > diff --git a/drivers/pwm/pwm-sunxi.c b/drivers/pwm/pwm-sunxi.c > new file mode 100644 > index 000000000000..0f2d65e8976b > --- /dev/null > +++ b/drivers/pwm/pwm-sunxi.c > @@ -0,0 +1,345 @@ > +/* > + * Driver for Allwinner Pulse Width Modulation Controller > + * > + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Licensed under GPLv2. > + */ > + > +#include <linux/bitops.h> > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/module.h> > +#include <linux/mutex.h> > +#include <linux/slab.h> > + > +#define PWM_CTRL_REG 0x0 > + > +#define PWM_CH_PRD_BASE 0x4 > +#define PWM_CH_PRD_OFF 0x4 > +#define PWM_CH_PRD(x) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFF * (x)) > + > +#define PWMCH_OFFSET 15 > +#define PWM_PRESCAL_MASK GENMASK(3,0) > +#define PWM_PRESCAL_OFF 0 > +#define PWM_EN BIT(4) > +#define PWM_ACT_STATE BIT(5) > +#define PWM_CLK_GATING BIT(6) > +#define PWM_MODE BIT(7) > +#define PWM_PULSE BIT(8) > +#define PWM_BYPASS BIT(9) > + > +#define PWM_RDY_BASE 28 > +#define PWM_RDY_OFF 1 > +#define PWM_RDY(x) BIT(PWM_RDY_BASE + PWM_RDY_OFF * (x)) > + > +#define PWM_PRD_ACT_MASK 0xFF > +#define PWM_PRD(x) ((x - 1) << 16) > +#define PWM_PRD_MASK 0xFF > + > +#define BIT_CH(bit, chan) (bit << (chan * PWMCH_OFFSET)) > + > +u32 prescal_table[] = { 120, 180, 240, 360, 480, 0, 0, 0, > + 12000, 24000, 36000, 48000, 72000, > + 0, 0, 1 }; > + > +struct sunxi_pwm_data { > + bool has_rdy; > +}; > + > +struct sunxi_pwm_chip { > + struct pwm_chip chip; > + struct clk *clk; > + void __iomem *base; > + struct mutex ctrl_lock; > + const struct sunxi_pwm_data *data; > +}; > + > +#define to_sunxi_pwm_chip(chip) container_of(chip, struct sunxi_pwm_chip, chip) > + > +static inline u32 sunxi_pwm_readl(struct sunxi_pwm_chip *chip, > + unsigned long offset) > +{ > + return readl_relaxed(chip->base + offset); > +} > + > +static inline void sunxi_pwm_writel(struct sunxi_pwm_chip *chip, > + unsigned long offset, unsigned long val) > +{ > + writel_relaxed(val, chip->base + offset); Actually, this won't work with COMPILE_TEST, since the *_relaxed functions are not defined for all the architectures. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv3 2/7] pwm: sunxi: document OF bindings 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 1/7] pwm: Add Allwinner SoC support Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM Alexandre Belloni ` (4 subsequent siblings) 6 siblings, 0 replies; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni This is the documentation for the Allwinner Socs PWM bindings. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/pwm/pwm-sunxi.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sunxi.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt b/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt new file mode 100644 index 000000000000..9eda87e7d233 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt @@ -0,0 +1,20 @@ +Allwinner PWM controller + +Required properties: + - compatible: should be one of: + - "allwinner,sun4i-a10-pwm" + - "allwinner,sun7i-a20-pwm" + - reg: physical base address and length of the controller's registers + - #pwm-cells: should be 3. See pwm.txt in this directory for a description of + the cells format. + - clocks: from common clock binding, handle to the parent clock. + +Example: + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 1/7] pwm: Add Allwinner SoC support Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 2/7] pwm: sunxi: document OF bindings Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 19:09 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 4/7] ARM: sun4i: dt: add PWM support Alexandre Belloni ` (3 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni Add the pinctrl descriptions for both PWM channels of the Allwinner A10. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9174724571e2..109e796e4a69 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -477,6 +477,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM 2014-04-28 16:17 ` [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM Alexandre Belloni @ 2014-04-28 19:09 ` Maxime Ripard 0 siblings, 0 replies; 13+ messages in thread From: Maxime Ripard @ 2014-04-28 19:09 UTC (permalink / raw) To: Alexandre Belloni Cc: linux-pwm, Thierry Reding, linux-kernel, linux-arm-kernel, linux-doc [-- Attachment #1.1: Type: text/plain, Size: 387 bytes --] On Mon, Apr 28, 2014 at 06:17:10PM +0200, Alexandre Belloni wrote: > Add the pinctrl descriptions for both PWM channels of the Allwinner A10. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Applied to sunxi/dt-for-3.16, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #1.2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv3 4/7] ARM: sun4i: dt: add PWM support 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni ` (2 preceding siblings ...) 2014-04-28 16:17 ` [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 19:13 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM Alexandre Belloni ` (2 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni Add the PWM bindings for the Allwinner A10. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 109e796e4a69..bb11c422526b 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -563,6 +563,14 @@ interrupts = <24>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun4i-a10-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCHv3 4/7] ARM: sun4i: dt: add PWM support 2014-04-28 16:17 ` [PATCHv3 4/7] ARM: sun4i: dt: add PWM support Alexandre Belloni @ 2014-04-28 19:13 ` Maxime Ripard 0 siblings, 0 replies; 13+ messages in thread From: Maxime Ripard @ 2014-04-28 19:13 UTC (permalink / raw) To: Alexandre Belloni Cc: Thierry Reding, linux-pwm, linux-doc, linux-arm-kernel, linux-kernel [-- Attachment #1: Type: text/plain, Size: 326 bytes --] On Mon, Apr 28, 2014 at 06:17:11PM +0200, Alexandre Belloni wrote: > Add the PWM bindings for the Allwinner A10. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Applied, thanks -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni ` (3 preceding siblings ...) 2014-04-28 16:17 ` [PATCHv3 4/7] ARM: sun4i: dt: add PWM support Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 19:11 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 6/7] ARM: sun7i: dt: add PWM support Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 7/7] ARM: sunxi: dt: add PWM support for the cubietruck Alexandre Belloni 6 siblings, 1 reply; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni Add the pinctrl descriptions for both PWM channels of the Allwinner A20. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 32efc105df83..c6eb881a3ced 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -540,6 +540,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM 2014-04-28 16:17 ` [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM Alexandre Belloni @ 2014-04-28 19:11 ` Maxime Ripard 0 siblings, 0 replies; 13+ messages in thread From: Maxime Ripard @ 2014-04-28 19:11 UTC (permalink / raw) To: Alexandre Belloni Cc: linux-pwm, Thierry Reding, linux-kernel, linux-arm-kernel, linux-doc [-- Attachment #1.1: Type: text/plain, Size: 366 bytes --] On Mon, Apr 28, 2014 at 06:17:12PM +0200, Alexandre Belloni wrote: > Add the pinctrl descriptions for both PWM channels of the Allwinner A20. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #1.2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv3 6/7] ARM: sun7i: dt: add PWM support 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni ` (4 preceding siblings ...) 2014-04-28 16:17 ` [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 2014-04-28 19:13 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 7/7] ARM: sunxi: dt: add PWM support for the cubietruck Alexandre Belloni 6 siblings, 1 reply; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni Add the PWM bindings for the Allwinner A20. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c6eb881a3ced..19d1f60209c5 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -692,6 +692,14 @@ interrupts = <0 24 4>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCHv3 6/7] ARM: sun7i: dt: add PWM support 2014-04-28 16:17 ` [PATCHv3 6/7] ARM: sun7i: dt: add PWM support Alexandre Belloni @ 2014-04-28 19:13 ` Maxime Ripard 0 siblings, 0 replies; 13+ messages in thread From: Maxime Ripard @ 2014-04-28 19:13 UTC (permalink / raw) To: Alexandre Belloni Cc: linux-pwm, Thierry Reding, linux-kernel, linux-arm-kernel, linux-doc [-- Attachment #1.1: Type: text/plain, Size: 326 bytes --] On Mon, Apr 28, 2014 at 06:17:13PM +0200, Alexandre Belloni wrote: > Add the PWM bindings for the Allwinner A20. > > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Applied, thanks -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #1.2: Digital signature --] [-- Type: application/pgp-signature, Size: 836 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCHv3 7/7] ARM: sunxi: dt: add PWM support for the cubietruck 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni ` (5 preceding siblings ...) 2014-04-28 16:17 ` [PATCHv3 6/7] ARM: sun7i: dt: add PWM support Alexandre Belloni @ 2014-04-28 16:17 ` Alexandre Belloni 6 siblings, 0 replies; 13+ messages in thread From: Alexandre Belloni @ 2014-04-28 16:17 UTC (permalink / raw) To: Thierry Reding, Maxime Ripard Cc: linux-pwm, linux-doc, linux-arm-kernel, linux-kernel, Alexandre Belloni Enable the PWM for both PWM channels on the cubietruck. They can be found on connector CN8. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index cb25d3c8da58..0c3bd127a5fd 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -63,6 +63,12 @@ }; }; + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-04-28 19:13 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-04-28 16:17 [PATCHv3 0/7] Add Allwinner SoCs PWM support Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 1/7] pwm: Add Allwinner SoC support Alexandre Belloni 2014-04-28 19:10 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 2/7] pwm: sunxi: document OF bindings Alexandre Belloni 2014-04-28 16:17 ` [PATCHv3 3/7] ARM: sun4i: dt: add pinmux configuration for the PWM Alexandre Belloni 2014-04-28 19:09 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 4/7] ARM: sun4i: dt: add PWM support Alexandre Belloni 2014-04-28 19:13 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 5/7] ARM: sun7i: dt: add pinmux configuration for the PWM Alexandre Belloni 2014-04-28 19:11 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 6/7] ARM: sun7i: dt: add PWM support Alexandre Belloni 2014-04-28 19:13 ` Maxime Ripard 2014-04-28 16:17 ` [PATCHv3 7/7] ARM: sunxi: dt: add PWM support for the cubietruck Alexandre Belloni
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