From mboxrd@z Thu Jan 1 00:00:00 1970 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= Subject: Re: [PATCH v4 4/7] pwm: sun4i: Add support to output source clock directly Date: Wed, 13 Nov 2019 09:58:58 +0100 Message-ID: <20191113085858.76rad3vpszknu4cp@pengutronix.de> References: <20191108084517.21617-1-peron.clem@gmail.com> <20191108084517.21617-5-peron.clem@gmail.com> Reply-To: u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20191108084517.21617-5-peron.clem-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: =?iso-8859-1?Q?Cl=E9ment_P=E9ron?= Cc: Thierry Reding , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel , linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Jernej Skrabec List-Id: linux-pwm@vger.kernel.org On Fri, Nov 08, 2019 at 09:45:14AM +0100, Cl=C3=A9ment P=C3=A9ron wrote: > From: Jernej Skrabec >=20 > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. >=20 > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. >=20 > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip which is integrated into same > package as H6 SoC. >=20 > Signed-off-by: Jernej Skrabec > Signed-off-by: Cl=C3=A9ment P=C3=A9ron > --- > drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) >=20 > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index a10022d6c0fd..9cc928ab47bc 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be byp= assed > + * and the currently running period is not guaranteed to be completed > */ > =20 > #include > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] =3D { > =20 > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > =20 > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chi= p, > =20 > val =3D sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > =20 > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + sun4i_pwm->data->has_direct_mod_clk_output) { > + state->period =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle =3D DIV_ROUND_UP_ULL(state->period, 2); I first thought you're losing precision here by reusing state->period here, but with a divisor of 2 everything is fine. > + state->polarity =3D PWM_POLARITY_NORMAL; > + state->enabled =3D true; > + return; > + } > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) =3D=3D PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler =3D 1; > @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, > struct sun4i_pwm_chip *sun4i_pwm =3D to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > u32 ctrl; > + bool bypass =3D false; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, > } > } > =20 > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled"= . I don't understand this reasoning. sun4i_pwm_calculate knows about .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just add a bool *bypass as parameter and move the logic there? > + */ > + if (state->enabled) { > + u32 clk_rate =3D clk_get_rate(sun4i_pwm->clk); > + bypass =3D (state->period * clk_rate >=3D NSEC_PER_SEC) && > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > + (state->duty_cycle * clk_rate * 2 >=3D NSEC_PER_SEC); > + } > + This looks right now. Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=C3=B6nig = | Industrial Linux Solutions | https://www.pengutronix.de/ | --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org To view this discussion on the web, visit https://groups.google.com/d/msgid= /linux-sunxi/20191113085858.76rad3vpszknu4cp%40pengutronix.de.