From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD9CEC433E2 for ; Thu, 3 Sep 2020 12:46:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A9B42072A for ; Thu, 3 Sep 2020 12:46:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728967AbgICMp6 (ORCPT ); Thu, 3 Sep 2020 08:45:58 -0400 Received: from mga18.intel.com ([134.134.136.126]:34247 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728771AbgICMpg (ORCPT ); Thu, 3 Sep 2020 08:45:36 -0400 IronPort-SDR: FsCqo2lfqFd6T5Ux9fQqj2M1896awRgKlACqjakDr9ofjSw/xjDny1xHrf1256hUlM4bZ04IWj 3FUh8Jb2mC9Q== X-IronPort-AV: E=McAfee;i="6000,8403,9732"; a="145259251" X-IronPort-AV: E=Sophos;i="5.76,386,1592895600"; d="scan'208";a="145259251" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2020 05:44:17 -0700 IronPort-SDR: kZzwEjPFL76uAlYlWMeMwP4z7365CXK3tAGVLxNKwcYn4NWMzlwGRKUeewXpvnLxRLFf69q1Tl MvJhirGWhRzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,386,1592895600"; d="scan'208";a="331776177" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga008.jf.intel.com with ESMTP; 03 Sep 2020 05:44:14 -0700 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1kDob5-00E1m7-CU; Thu, 03 Sep 2020 15:44:11 +0300 Date: Thu, 3 Sep 2020 15:44:11 +0300 From: Andy Shevchenko To: Hans de Goede Cc: Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , "Rafael J . Wysocki" , Len Brown , linux-pwm@vger.kernel.org, intel-gfx , dri-devel@lists.freedesktop.org, Mika Westerberg , linux-acpi@vger.kernel.org Subject: Re: [PATCH v10 06/17] pwm: lpss: Make pwm_lpss_apply() not rely on existing hardware state Message-ID: <20200903124411.GZ1891694@smile.fi.intel.com> References: <20200903112337.4113-1-hdegoede@redhat.com> <20200903112337.4113-7-hdegoede@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200903112337.4113-7-hdegoede@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org On Thu, Sep 03, 2020 at 01:23:26PM +0200, Hans de Goede wrote: > Before this commit pwm_lpss_apply() was assuming 2 pre-conditions > were met by the existing hardware state: > > 1. That the base-unit and on-time-div read back from the > control register are those actually in use, so that it > can skip setting the update bit if the read-back value > matches the desired values. > > 2. That the controller is enabled when the cached > pwm_state.enabled says that the controller is enabled. > > As the long history of fixes for subtle (often suspend/resume) > lpss-pwm issues shows, these assumptions are not necessary > always true. > > 1. Specifically is not true on some (*) Cherry Trail devices > with a nasty GFX0._PS3 method which: a. saves the ctrl reg value. > b. sets the base-unit to 0 and writes the update bit to apply/commit > c. restores the original ctrl value without setting the update bit, > so that the 0 base-unit value is still in use. > > 2. Assumption 2. currently is true, but only because of the code which > saves/restores the state on suspend/resume. By convention restoring the > PWM state should be done by the PWM consumer and the presence of this > code in the pmw-lpss driver is a bug. Therefor the save/restore code will > be dropped in the next patch in this series, after which this assumption > also is no longer true. > > This commit changes the pwm_lpss_apply() to not make any assumptions about > the state the hardware is in. Instead it makes pwm_lpss_apply() always > fully program the PWM controller, making it much less fragile. > > *) Seen on the Acer One 10 S1003, Lenovo Ideapad Miix 310 and 320 models > and various Medion models. Good one! Reviewed-by: Andy Shevchenko > Acked-by: Thierry Reding > Signed-off-by: Hans de Goede > --- > Changes in v10: > - Fixup some wording / mistakes in the commit message > > Changes in v9: > - This is a new patch in v9 of this series > --- > drivers/pwm/pwm-lpss.c | 21 +++++++++------------ > 1 file changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c > index 8a136ba2a583..9c5c7217c9b6 100644 > --- a/drivers/pwm/pwm-lpss.c > +++ b/drivers/pwm/pwm-lpss.c > @@ -85,7 +85,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, > unsigned long long on_time_div; > unsigned long c = lpwm->info->clk_rate, base_unit_range; > unsigned long long base_unit, freq = NSEC_PER_SEC; > - u32 orig_ctrl, ctrl; > + u32 ctrl; > > do_div(freq, period_ns); > > @@ -104,16 +104,14 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, > do_div(on_time_div, period_ns); > on_time_div = 255ULL - on_time_div; > > - orig_ctrl = ctrl = pwm_lpss_read(pwm); > + ctrl = pwm_lpss_read(pwm); > ctrl &= ~PWM_ON_TIME_DIV_MASK; > ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); > ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; > ctrl |= on_time_div; > > - if (orig_ctrl != ctrl) { > - pwm_lpss_write(pwm, ctrl); > - pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE); > - } > + pwm_lpss_write(pwm, ctrl); > + pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE); > } > > static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) > @@ -124,8 +122,7 @@ static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) > > static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm, > struct pwm_device *pwm, > - const struct pwm_state *state, > - bool enable) > + const struct pwm_state *state) > { > int ret; > > @@ -134,12 +131,12 @@ static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm, > return ret; > > pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); > - pwm_lpss_cond_enable(pwm, enable && lpwm->info->bypass == false); > + pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); > ret = pwm_lpss_wait_for_update(pwm); > if (ret) > return ret; > > - pwm_lpss_cond_enable(pwm, enable && lpwm->info->bypass == true); > + pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); > return 0; > } > > @@ -152,11 +149,11 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, > if (state->enabled) { > if (!pwm_is_enabled(pwm)) { > pm_runtime_get_sync(chip->dev); > - ret = pwm_lpss_prepare_enable(lpwm, pwm, state, true); > + ret = pwm_lpss_prepare_enable(lpwm, pwm, state); > if (ret) > pm_runtime_put(chip->dev); > } else { > - ret = pwm_lpss_prepare_enable(lpwm, pwm, state, false); > + ret = pwm_lpss_prepare_enable(lpwm, pwm, state); > } > } else if (pwm_is_enabled(pwm)) { > pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); > -- > 2.28.0 > -- With Best Regards, Andy Shevchenko